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authorRodrigo Vivi <rodrigo.vivi@intel.com>2018-07-23 12:13:12 -0400
committerRodrigo Vivi <rodrigo.vivi@intel.com>2018-07-23 12:13:12 -0400
commitc74a7469f97c0f40b46e82ee979f9fb1bb6e847c (patch)
treef2690a1a916b73ef94657fbf0e0141ae57701825 /drivers/gpu/drm/i915
parent6f15a7de86c8cf2dc09fc9e6d07047efa40ef809 (diff)
parent500775074f88d9cf5416bed2ca19592812d62c41 (diff)
Merge drm/drm-next into drm-intel-next-queued
We need a backmerge to get DP_DPCD_REV_14 before we push other i915 changes to dinq that could break compilation. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r--drivers/gpu/drm/i915/Kconfig.debug2
-rw-r--r--drivers/gpu/drm/i915/gvt/cmd_parser.c1
-rw-r--r--drivers/gpu/drm/i915/gvt/display.h2
-rw-r--r--drivers/gpu/drm/i915/gvt/gtt.c5
-rw-r--r--drivers/gpu/drm/i915/gvt/handlers.c13
-rw-r--r--drivers/gpu/drm/i915/gvt/kvmgt.c34
-rw-r--r--drivers/gpu/drm/i915/gvt/mmio.c2
-rw-r--r--drivers/gpu/drm/i915/gvt/vgpu.c2
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c8
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h3
-rw-r--r--drivers/gpu/drm/i915/i915_gem_dmabuf.c11
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.c11
-rw-r--r--drivers/gpu/drm/i915/intel_atomic.c1
-rw-r--r--drivers/gpu/drm/i915/intel_atomic_plane.c12
-rw-r--r--drivers/gpu/drm/i915/intel_display.c142
-rw-r--r--drivers/gpu/drm/i915/intel_display.h4
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c23
-rw-r--r--drivers/gpu/drm/i915/intel_dp_mst.c15
-rw-r--r--drivers/gpu/drm/i915/intel_dpll_mgr.c6
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h3
-rw-r--r--drivers/gpu/drm/i915/intel_hdcp.c2
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c17
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c2
-rw-r--r--drivers/gpu/drm/i915/intel_modes.c2
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c2
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c7
-rw-r--r--drivers/gpu/drm/i915/intel_sprite.c291
-rw-r--r--drivers/gpu/drm/i915/selftests/intel_uncore.c2
-rw-r--r--drivers/gpu/drm/i915/selftests/mock_dmabuf.c14
29 files changed, 339 insertions, 300 deletions
diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug
index 96b577f62752..459f8f88a34c 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -26,7 +26,7 @@ config DRM_I915_DEBUG
26 select DRM_VGEM # used by igt/prime_vgem (dmabuf interop checks) 26 select DRM_VGEM # used by igt/prime_vgem (dmabuf interop checks)
27 select DRM_DEBUG_MM if DRM=y 27 select DRM_DEBUG_MM if DRM=y
28 select STACKDEPOT if DRM=y # for DRM_DEBUG_MM 28 select STACKDEPOT if DRM=y # for DRM_DEBUG_MM
29 select DRM_DEBUG_MM_SELFTEST 29 select DRM_DEBUG_SELFTEST
30 select SW_SYNC # signaling validation framework (igt/syncobj*) 30 select SW_SYNC # signaling validation framework (igt/syncobj*)
31 select DRM_I915_SW_FENCE_DEBUG_OBJECTS 31 select DRM_I915_SW_FENCE_DEBUG_OBJECTS
32 select DRM_I915_SELFTEST 32 select DRM_I915_SELFTEST
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 0dd88fe2e39a..0651e63b25fb 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -2902,6 +2902,7 @@ static int init_cmd_table(struct intel_gvt *gvt)
2902 if (info) { 2902 if (info) {
2903 gvt_err("%s %s duplicated\n", e->info->name, 2903 gvt_err("%s %s duplicated\n", e->info->name,
2904 info->name); 2904 info->name);
2905 kfree(e);
2905 return -EEXIST; 2906 return -EEXIST;
2906 } 2907 }
2907 2908
diff --git a/drivers/gpu/drm/i915/gvt/display.h b/drivers/gpu/drm/i915/gvt/display.h
index b46b86892d58..ea7c1c525b8c 100644
--- a/drivers/gpu/drm/i915/gvt/display.h
+++ b/drivers/gpu/drm/i915/gvt/display.h
@@ -67,7 +67,7 @@
67#define AUX_NATIVE_REPLY_NAK (0x1 << 4) 67#define AUX_NATIVE_REPLY_NAK (0x1 << 4)
68#define AUX_NATIVE_REPLY_DEFER (0x2 << 4) 68#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
69 69
70#define AUX_BURST_SIZE 16 70#define AUX_BURST_SIZE 20
71 71
72/* DPCD addresses */ 72/* DPCD addresses */
73#define DPCD_REV 0x000 73#define DPCD_REV 0x000
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 156ceeeb7446..39980dfbbebd 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1894,8 +1894,9 @@ static struct intel_vgpu_mm *intel_vgpu_create_ggtt_mm(struct intel_vgpu *vgpu)
1894 mm->type = INTEL_GVT_MM_GGTT; 1894 mm->type = INTEL_GVT_MM_GGTT;
1895 1895
1896 nr_entries = gvt_ggtt_gm_sz(vgpu->gvt) >> I915_GTT_PAGE_SHIFT; 1896 nr_entries = gvt_ggtt_gm_sz(vgpu->gvt) >> I915_GTT_PAGE_SHIFT;
1897 mm->ggtt_mm.virtual_ggtt = vzalloc(nr_entries * 1897 mm->ggtt_mm.virtual_ggtt =
1898 vgpu->gvt->device_info.gtt_entry_size); 1898 vzalloc(array_size(nr_entries,
1899 vgpu->gvt->device_info.gtt_entry_size));
1899 if (!mm->ggtt_mm.virtual_ggtt) { 1900 if (!mm->ggtt_mm.virtual_ggtt) {
1900 vgpu_free_mm(mm); 1901 vgpu_free_mm(mm);
1901 return ERR_PTR(-ENOMEM); 1902 return ERR_PTR(-ENOMEM);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index e2e252c67de8..6b50f850dc28 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -936,11 +936,14 @@ static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
936 } 936 }
937 937
938 /* 938 /*
939 * Write request format: (command + address) occupies 939 * Write request format: Headr (command + address + size) occupies
940 * 3 bytes, followed by (len + 1) bytes of data. 940 * 4 bytes, followed by (len + 1) bytes of data. See details at
941 * intel_dp_aux_transfer().
941 */ 942 */
942 if (WARN_ON((len + 4) > AUX_BURST_SIZE)) 943 if ((len + 1 + 4) > AUX_BURST_SIZE) {
944 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
943 return -EINVAL; 945 return -EINVAL;
946 }
944 947
945 /* unpack data from vreg to buf */ 948 /* unpack data from vreg to buf */
946 for (t = 0; t < 4; t++) { 949 for (t = 0; t < 4; t++) {
@@ -1004,8 +1007,10 @@ static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
1004 /* 1007 /*
1005 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 1008 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
1006 */ 1009 */
1007 if (WARN_ON((len + 2) > AUX_BURST_SIZE)) 1010 if ((len + 2) > AUX_BURST_SIZE) {
1011 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
1008 return -EINVAL; 1012 return -EINVAL;
1013 }
1009 1014
1010 /* read from virtual DPCD to vreg */ 1015 /* read from virtual DPCD to vreg */
1011 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 1016 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 685cb3de6dab..718ab307a500 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -185,6 +185,12 @@ static int gvt_dma_map_page(struct intel_vgpu *vgpu, unsigned long gfn,
185 if (ret) 185 if (ret)
186 return ret; 186 return ret;
187 187
188 if (!pfn_valid(pfn)) {
189 gvt_vgpu_err("pfn 0x%lx is not mem backed\n", pfn);
190 vfio_unpin_pages(mdev_dev(vgpu->vdev.mdev), &gfn, 1);
191 return -EINVAL;
192 }
193
188 /* Setup DMA mapping. */ 194 /* Setup DMA mapping. */
189 *dma_addr = dma_map_page(dev, page, 0, size, PCI_DMA_BIDIRECTIONAL); 195 *dma_addr = dma_map_page(dev, page, 0, size, PCI_DMA_BIDIRECTIONAL);
190 ret = dma_mapping_error(dev, *dma_addr); 196 ret = dma_mapping_error(dev, *dma_addr);
@@ -644,6 +650,17 @@ out:
644 return ret; 650 return ret;
645} 651}
646 652
653static void intel_vgpu_release_msi_eventfd_ctx(struct intel_vgpu *vgpu)
654{
655 struct eventfd_ctx *trigger;
656
657 trigger = vgpu->vdev.msi_trigger;
658 if (trigger) {
659 eventfd_ctx_put(trigger);
660 vgpu->vdev.msi_trigger = NULL;
661 }
662}
663
647static void __intel_vgpu_release(struct intel_vgpu *vgpu) 664static void __intel_vgpu_release(struct intel_vgpu *vgpu)
648{ 665{
649 struct kvmgt_guest_info *info; 666 struct kvmgt_guest_info *info;
@@ -668,6 +685,8 @@ static void __intel_vgpu_release(struct intel_vgpu *vgpu)
668 info = (struct kvmgt_guest_info *)vgpu->handle; 685 info = (struct kvmgt_guest_info *)vgpu->handle;
669 kvmgt_guest_exit(info); 686 kvmgt_guest_exit(info);
670 687
688 intel_vgpu_release_msi_eventfd_ctx(vgpu);
689
671 vgpu->vdev.kvm = NULL; 690 vgpu->vdev.kvm = NULL;
672 vgpu->handle = 0; 691 vgpu->handle = 0;
673} 692}
@@ -1048,7 +1067,8 @@ static int intel_vgpu_set_msi_trigger(struct intel_vgpu *vgpu,
1048 return PTR_ERR(trigger); 1067 return PTR_ERR(trigger);
1049 } 1068 }
1050 vgpu->vdev.msi_trigger = trigger; 1069 vgpu->vdev.msi_trigger = trigger;
1051 } 1070 } else if ((flags & VFIO_IRQ_SET_DATA_NONE) && !count)
1071 intel_vgpu_release_msi_eventfd_ctx(vgpu);
1052 1072
1053 return 0; 1073 return 0;
1054} 1074}
@@ -1653,6 +1673,18 @@ static int kvmgt_inject_msi(unsigned long handle, u32 addr, u16 data)
1653 info = (struct kvmgt_guest_info *)handle; 1673 info = (struct kvmgt_guest_info *)handle;
1654 vgpu = info->vgpu; 1674 vgpu = info->vgpu;
1655 1675
1676 /*
1677 * When guest is poweroff, msi_trigger is set to NULL, but vgpu's
1678 * config and mmio register isn't restored to default during guest
1679 * poweroff. If this vgpu is still used in next vm, this vgpu's pipe
1680 * may be enabled, then once this vgpu is active, it will get inject
1681 * vblank interrupt request. But msi_trigger is null until msi is
1682 * enabled by guest. so if msi_trigger is null, success is still
1683 * returned and don't inject interrupt into guest.
1684 */
1685 if (vgpu->vdev.msi_trigger == NULL)
1686 return 0;
1687
1656 if (eventfd_signal(vgpu->vdev.msi_trigger, 1) == 1) 1688 if (eventfd_signal(vgpu->vdev.msi_trigger, 1) == 1)
1657 return 0; 1689 return 0;
1658 1690
diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
index 2be1be2cf49a..994366035364 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.c
+++ b/drivers/gpu/drm/i915/gvt/mmio.c
@@ -267,7 +267,7 @@ int intel_vgpu_init_mmio(struct intel_vgpu *vgpu)
267{ 267{
268 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; 268 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
269 269
270 vgpu->mmio.vreg = vzalloc(info->mmio_size * 2); 270 vgpu->mmio.vreg = vzalloc(array_size(info->mmio_size, 2));
271 if (!vgpu->mmio.vreg) 271 if (!vgpu->mmio.vreg)
272 return -ENOMEM; 272 return -ENOMEM;
273 273
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index aa063b275e81..f6fa916517c3 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -125,7 +125,7 @@ int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
125 high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE; 125 high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
126 num_types = sizeof(vgpu_types) / sizeof(vgpu_types[0]); 126 num_types = sizeof(vgpu_types) / sizeof(vgpu_types[0]);
127 127
128 gvt->types = kzalloc(num_types * sizeof(struct intel_vgpu_type), 128 gvt->types = kcalloc(num_types, sizeof(struct intel_vgpu_type),
129 GFP_KERNEL); 129 GFP_KERNEL);
130 if (!gvt->types) 130 if (!gvt->types)
131 return -ENOMEM; 131 return -ENOMEM;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 23e9a86cbc2a..18a45e7a3d7c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2847,10 +2847,10 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
2847 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), 2847 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2848 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0), 2848 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2849 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), 2849 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2850 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW), 2850 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
2851 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW), 2851 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
2852 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW), 2852 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
2853 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW), 2853 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
2854 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2854 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2855 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), 2855 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2856 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), 2856 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ef1aabb751c6..0f49f9988dfa 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2230,9 +2230,6 @@ static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2230 **/ 2230 **/
2231static inline struct scatterlist *__sg_next(struct scatterlist *sg) 2231static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2232{ 2232{
2233#ifdef CONFIG_DEBUG_SG
2234 BUG_ON(sg->sg_magic != SG_MAGIC);
2235#endif
2236 return sg_is_last(sg) ? NULL : ____sg_next(sg); 2233 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2237} 2234}
2238 2235
diff --git a/drivers/gpu/drm/i915/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
index 69a7aec49e84..82e2ca17a441 100644
--- a/drivers/gpu/drm/i915/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
@@ -111,15 +111,6 @@ static void i915_gem_dmabuf_vunmap(struct dma_buf *dma_buf, void *vaddr)
111 i915_gem_object_unpin_map(obj); 111 i915_gem_object_unpin_map(obj);
112} 112}
113 113
114static void *i915_gem_dmabuf_kmap_atomic(struct dma_buf *dma_buf, unsigned long page_num)
115{
116 return NULL;
117}
118
119static void i915_gem_dmabuf_kunmap_atomic(struct dma_buf *dma_buf, unsigned long page_num, void *addr)
120{
121
122}
123static void *i915_gem_dmabuf_kmap(struct dma_buf *dma_buf, unsigned long page_num) 114static void *i915_gem_dmabuf_kmap(struct dma_buf *dma_buf, unsigned long page_num)
124{ 115{
125 struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf); 116 struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
@@ -225,9 +216,7 @@ static const struct dma_buf_ops i915_dmabuf_ops = {
225 .unmap_dma_buf = i915_gem_unmap_dma_buf, 216 .unmap_dma_buf = i915_gem_unmap_dma_buf,
226 .release = drm_gem_dmabuf_release, 217 .release = drm_gem_dmabuf_release,
227 .map = i915_gem_dmabuf_kmap, 218 .map = i915_gem_dmabuf_kmap,
228 .map_atomic = i915_gem_dmabuf_kmap_atomic,
229 .unmap = i915_gem_dmabuf_kunmap, 219 .unmap = i915_gem_dmabuf_kunmap,
230 .unmap_atomic = i915_gem_dmabuf_kunmap_atomic,
231 .mmap = i915_gem_dmabuf_mmap, 220 .mmap = i915_gem_dmabuf_mmap,
232 .vmap = i915_gem_dmabuf_vmap, 221 .vmap = i915_gem_dmabuf_vmap,
233 .vunmap = i915_gem_dmabuf_vunmap, 222 .vunmap = i915_gem_dmabuf_vunmap,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 81a2c340c091..1b476423bfab 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -4031,7 +4031,7 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
4031 4031
4032 mode = DRM_MM_INSERT_BEST; 4032 mode = DRM_MM_INSERT_BEST;
4033 if (flags & PIN_HIGH) 4033 if (flags & PIN_HIGH)
4034 mode = DRM_MM_INSERT_HIGH; 4034 mode = DRM_MM_INSERT_HIGHEST;
4035 if (flags & PIN_MAPPABLE) 4035 if (flags & PIN_MAPPABLE)
4036 mode = DRM_MM_INSERT_LOW; 4036 mode = DRM_MM_INSERT_LOW;
4037 4037
@@ -4051,6 +4051,15 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
4051 if (err != -ENOSPC) 4051 if (err != -ENOSPC)
4052 return err; 4052 return err;
4053 4053
4054 if (mode & DRM_MM_INSERT_ONCE) {
4055 err = drm_mm_insert_node_in_range(&vm->mm, node,
4056 size, alignment, color,
4057 start, end,
4058 DRM_MM_INSERT_BEST);
4059 if (err != -ENOSPC)
4060 return err;
4061 }
4062
4054 if (flags & PIN_NOEVICT) 4063 if (flags & PIN_NOEVICT)
4055 return -ENOSPC; 4064 return -ENOSPC;
4056 4065
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index fee026ca449b..b04952bacf77 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -126,6 +126,7 @@ int intel_digital_connector_atomic_check(struct drm_connector *conn,
126 if (new_conn_state->force_audio != old_conn_state->force_audio || 126 if (new_conn_state->force_audio != old_conn_state->force_audio ||
127 new_conn_state->broadcast_rgb != old_conn_state->broadcast_rgb || 127 new_conn_state->broadcast_rgb != old_conn_state->broadcast_rgb ||
128 new_conn_state->base.picture_aspect_ratio != old_conn_state->base.picture_aspect_ratio || 128 new_conn_state->base.picture_aspect_ratio != old_conn_state->base.picture_aspect_ratio ||
129 new_conn_state->base.content_type != old_conn_state->base.content_type ||
129 new_conn_state->base.scaling_mode != old_conn_state->base.scaling_mode) 130 new_conn_state->base.scaling_mode != old_conn_state->base.scaling_mode)
130 crtc_state->mode_changed = true; 131 crtc_state->mode_changed = true;
131 132
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 69a18d4ff59d..dcba645cabb8 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -120,12 +120,6 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
120 &crtc_state->base.adjusted_mode; 120 &crtc_state->base.adjusted_mode;
121 int ret; 121 int ret;
122 122
123 /*
124 * Both crtc and plane->crtc could be NULL if we're updating a
125 * property while the plane is disabled. We don't actually have
126 * anything driver-specific we need to test in that case, so
127 * just return success.
128 */
129 if (!intel_state->base.crtc && !old_plane_state->base.crtc) 123 if (!intel_state->base.crtc && !old_plane_state->base.crtc)
130 return 0; 124 return 0;
131 125
@@ -209,12 +203,6 @@ static int intel_plane_atomic_check(struct drm_plane *plane,
209 const struct drm_crtc_state *old_crtc_state; 203 const struct drm_crtc_state *old_crtc_state;
210 struct drm_crtc_state *new_crtc_state; 204 struct drm_crtc_state *new_crtc_state;
211 205
212 /*
213 * Both crtc and plane->crtc could be NULL if we're updating a
214 * property while the plane is disabled. We don't actually have
215 * anything driver-specific we need to test in that case, so
216 * just return success.
217 */
218 if (!crtc) 206 if (!crtc)
219 return 0; 207 return 0;
220 208
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8719c1a9d1ce..577b30dde45b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1022,7 +1022,7 @@ bool intel_crtc_active(struct intel_crtc *crtc)
1022 * We can ditch the adjusted_mode.crtc_clock check as soon 1022 * We can ditch the adjusted_mode.crtc_clock check as soon
1023 * as Haswell has gained clock readout/fastboot support. 1023 * as Haswell has gained clock readout/fastboot support.
1024 * 1024 *
1025 * We can ditch the crtc->primary->fb check as soon as we can 1025 * We can ditch the crtc->primary->state->fb check as soon as we can
1026 * properly reconstruct framebuffers. 1026 * properly reconstruct framebuffers.
1027 * 1027 *
1028 * FIXME: The intel_crtc->active here should be switched to 1028 * FIXME: The intel_crtc->active here should be switched to
@@ -2756,10 +2756,10 @@ intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2756 2756
2757 /* FIXME pre-g4x don't work like this */ 2757 /* FIXME pre-g4x don't work like this */
2758 if (visible) { 2758 if (visible) {
2759 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base)); 2759 crtc_state->base.plane_mask |= drm_plane_mask(&plane->base);
2760 crtc_state->active_planes |= BIT(plane->id); 2760 crtc_state->active_planes |= BIT(plane->id);
2761 } else { 2761 } else {
2762 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base)); 2762 crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base);
2763 crtc_state->active_planes &= ~BIT(plane->id); 2763 crtc_state->active_planes &= ~BIT(plane->id);
2764 } 2764 }
2765 2765
@@ -2882,9 +2882,8 @@ valid_fb:
2882 if (i915_gem_object_is_tiled(obj)) 2882 if (i915_gem_object_is_tiled(obj))
2883 dev_priv->preserve_bios_swizzle = true; 2883 dev_priv->preserve_bios_swizzle = true;
2884 2884
2885 drm_framebuffer_get(fb); 2885 plane_state->fb = fb;
2886 primary->fb = primary->state->fb = fb; 2886 plane_state->crtc = &intel_crtc->base;
2887 primary->crtc = primary->state->crtc = &intel_crtc->base;
2888 2887
2889 intel_set_plane_visible(to_intel_crtc_state(crtc_state), 2888 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2890 to_intel_plane_state(plane_state), 2889 to_intel_plane_state(plane_state),
@@ -3658,7 +3657,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
3658 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; 3657 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
3659 plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format); 3658 plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
3660 3659
3661 if (intel_format_is_yuv(fb->format->format)) { 3660 if (fb->format->is_yuv) {
3662 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709) 3661 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3663 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709; 3662 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
3664 else 3663 else
@@ -11899,7 +11898,7 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
11899 struct drm_crtc_state *new_state) 11898 struct drm_crtc_state *new_state)
11900{ 11899{
11901 struct intel_dpll_hw_state dpll_hw_state; 11900 struct intel_dpll_hw_state dpll_hw_state;
11902 unsigned crtc_mask; 11901 unsigned int crtc_mask;
11903 bool active; 11902 bool active;
11904 11903
11905 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); 11904 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
@@ -11926,7 +11925,7 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
11926 return; 11925 return;
11927 } 11926 }
11928 11927
11929 crtc_mask = 1 << drm_crtc_index(crtc); 11928 crtc_mask = drm_crtc_mask(crtc);
11930 11929
11931 if (new_state->active) 11930 if (new_state->active)
11932 I915_STATE_WARN(!(pll->active_mask & crtc_mask), 11931 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
@@ -11961,7 +11960,7 @@ verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11961 11960
11962 if (old_state->shared_dpll && 11961 if (old_state->shared_dpll &&
11963 old_state->shared_dpll != new_state->shared_dpll) { 11962 old_state->shared_dpll != new_state->shared_dpll) {
11964 unsigned crtc_mask = 1 << drm_crtc_index(crtc); 11963 unsigned int crtc_mask = drm_crtc_mask(crtc);
11965 struct intel_shared_dpll *pll = old_state->shared_dpll; 11964 struct intel_shared_dpll *pll = old_state->shared_dpll;
11966 11965
11967 I915_STATE_WARN(pll->active_mask & crtc_mask, 11966 I915_STATE_WARN(pll->active_mask & crtc_mask,
@@ -13305,8 +13304,17 @@ void intel_plane_destroy(struct drm_plane *plane)
13305 kfree(to_intel_plane(plane)); 13304 kfree(to_intel_plane(plane));
13306} 13305}
13307 13306
13308static bool i8xx_mod_supported(uint32_t format, uint64_t modifier) 13307static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
13308 u32 format, u64 modifier)
13309{ 13309{
13310 switch (modifier) {
13311 case DRM_FORMAT_MOD_LINEAR:
13312 case I915_FORMAT_MOD_X_TILED:
13313 break;
13314 default:
13315 return false;
13316 }
13317
13310 switch (format) { 13318 switch (format) {
13311 case DRM_FORMAT_C8: 13319 case DRM_FORMAT_C8:
13312 case DRM_FORMAT_RGB565: 13320 case DRM_FORMAT_RGB565:
@@ -13319,8 +13327,17 @@ static bool i8xx_mod_supported(uint32_t format, uint64_t modifier)
13319 } 13327 }
13320} 13328}
13321 13329
13322static bool i965_mod_supported(uint32_t format, uint64_t modifier) 13330static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
13331 u32 format, u64 modifier)
13323{ 13332{
13333 switch (modifier) {
13334 case DRM_FORMAT_MOD_LINEAR:
13335 case I915_FORMAT_MOD_X_TILED:
13336 break;
13337 default:
13338 return false;
13339 }
13340
13324 switch (format) { 13341 switch (format) {
13325 case DRM_FORMAT_C8: 13342 case DRM_FORMAT_C8:
13326 case DRM_FORMAT_RGB565: 13343 case DRM_FORMAT_RGB565:
@@ -13335,8 +13352,26 @@ static bool i965_mod_supported(uint32_t format, uint64_t modifier)
13335 } 13352 }
13336} 13353}
13337 13354
13338static bool skl_mod_supported(uint32_t format, uint64_t modifier) 13355static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
13356 u32 format, u64 modifier)
13339{ 13357{
13358 struct intel_plane *plane = to_intel_plane(_plane);
13359
13360 switch (modifier) {
13361 case DRM_FORMAT_MOD_LINEAR:
13362 case I915_FORMAT_MOD_X_TILED:
13363 case I915_FORMAT_MOD_Y_TILED:
13364 case I915_FORMAT_MOD_Yf_TILED:
13365 break;
13366 case I915_FORMAT_MOD_Y_TILED_CCS:
13367 case I915_FORMAT_MOD_Yf_TILED_CCS:
13368 if (!plane->has_ccs)
13369 return false;
13370 break;
13371 default:
13372 return false;
13373 }
13374
13340 switch (format) { 13375 switch (format) {
13341 case DRM_FORMAT_XRGB8888: 13376 case DRM_FORMAT_XRGB8888:
13342 case DRM_FORMAT_XBGR8888: 13377 case DRM_FORMAT_XBGR8888:
@@ -13368,38 +13403,36 @@ static bool skl_mod_supported(uint32_t format, uint64_t modifier)
13368 } 13403 }
13369} 13404}
13370 13405
13371static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane, 13406static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
13372 uint32_t format, 13407 u32 format, u64 modifier)
13373 uint64_t modifier)
13374{ 13408{
13375 struct drm_i915_private *dev_priv = to_i915(plane->dev); 13409 return modifier == DRM_FORMAT_MOD_LINEAR &&
13376 13410 format == DRM_FORMAT_ARGB8888;
13377 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
13378 return false;
13379
13380 if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
13381 modifier != DRM_FORMAT_MOD_LINEAR)
13382 return false;
13383
13384 if (INTEL_GEN(dev_priv) >= 9)
13385 return skl_mod_supported(format, modifier);
13386 else if (INTEL_GEN(dev_priv) >= 4)
13387 return i965_mod_supported(format, modifier);
13388 else
13389 return i8xx_mod_supported(format, modifier);
13390} 13411}
13391 13412
13392static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane, 13413static struct drm_plane_funcs skl_plane_funcs = {
13393 uint32_t format, 13414 .update_plane = drm_atomic_helper_update_plane,
13394 uint64_t modifier) 13415 .disable_plane = drm_atomic_helper_disable_plane,
13395{ 13416 .destroy = intel_plane_destroy,
13396 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) 13417 .atomic_get_property = intel_plane_atomic_get_property,
13397 return false; 13418 .atomic_set_property = intel_plane_atomic_set_property,
13419 .atomic_duplicate_state = intel_plane_duplicate_state,
13420 .atomic_destroy_state = intel_plane_destroy_state,
13421 .format_mod_supported = skl_plane_format_mod_supported,
13422};
13398 13423
13399 return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888; 13424static struct drm_plane_funcs i965_plane_funcs = {
13400} 13425 .update_plane = drm_atomic_helper_update_plane,
13426 .disable_plane = drm_atomic_helper_disable_plane,
13427 .destroy = intel_plane_destroy,
13428 .atomic_get_property = intel_plane_atomic_get_property,
13429 .atomic_set_property = intel_plane_atomic_set_property,
13430 .atomic_duplicate_state = intel_plane_duplicate_state,
13431 .atomic_destroy_state = intel_plane_destroy_state,
13432 .format_mod_supported = i965_plane_format_mod_supported,
13433};
13401 13434
13402static struct drm_plane_funcs intel_plane_funcs = { 13435static struct drm_plane_funcs i8xx_plane_funcs = {
13403 .update_plane = drm_atomic_helper_update_plane, 13436 .update_plane = drm_atomic_helper_update_plane,
13404 .disable_plane = drm_atomic_helper_disable_plane, 13437 .disable_plane = drm_atomic_helper_disable_plane,
13405 .destroy = intel_plane_destroy, 13438 .destroy = intel_plane_destroy,
@@ -13407,7 +13440,7 @@ static struct drm_plane_funcs intel_plane_funcs = {
13407 .atomic_set_property = intel_plane_atomic_set_property, 13440 .atomic_set_property = intel_plane_atomic_set_property,
13408 .atomic_duplicate_state = intel_plane_duplicate_state, 13441 .atomic_duplicate_state = intel_plane_duplicate_state,
13409 .atomic_destroy_state = intel_plane_destroy_state, 13442 .atomic_destroy_state = intel_plane_destroy_state,
13410 .format_mod_supported = intel_primary_plane_format_mod_supported, 13443 .format_mod_supported = i8xx_plane_format_mod_supported,
13411}; 13444};
13412 13445
13413static int 13446static int
@@ -13532,7 +13565,7 @@ static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13532 .atomic_set_property = intel_plane_atomic_set_property, 13565 .atomic_set_property = intel_plane_atomic_set_property,
13533 .atomic_duplicate_state = intel_plane_duplicate_state, 13566 .atomic_duplicate_state = intel_plane_duplicate_state,
13534 .atomic_destroy_state = intel_plane_destroy_state, 13567 .atomic_destroy_state = intel_plane_destroy_state,
13535 .format_mod_supported = intel_cursor_plane_format_mod_supported, 13568 .format_mod_supported = intel_cursor_format_mod_supported,
13536}; 13569};
13537 13570
13538static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv, 13571static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
@@ -13590,6 +13623,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13590{ 13623{
13591 struct intel_plane *primary = NULL; 13624 struct intel_plane *primary = NULL;
13592 struct intel_plane_state *state = NULL; 13625 struct intel_plane_state *state = NULL;
13626 const struct drm_plane_funcs *plane_funcs;
13593 const uint32_t *intel_primary_formats; 13627 const uint32_t *intel_primary_formats;
13594 unsigned int supported_rotations; 13628 unsigned int supported_rotations;
13595 unsigned int num_formats; 13629 unsigned int num_formats;
@@ -13645,6 +13679,9 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13645 primary->check_plane = intel_check_primary_plane; 13679 primary->check_plane = intel_check_primary_plane;
13646 13680
13647 if (INTEL_GEN(dev_priv) >= 9) { 13681 if (INTEL_GEN(dev_priv) >= 9) {
13682 primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
13683 PLANE_PRIMARY);
13684
13648 if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) { 13685 if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
13649 intel_primary_formats = skl_pri_planar_formats; 13686 intel_primary_formats = skl_pri_planar_formats;
13650 num_formats = ARRAY_SIZE(skl_pri_planar_formats); 13687 num_formats = ARRAY_SIZE(skl_pri_planar_formats);
@@ -13653,7 +13690,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13653 num_formats = ARRAY_SIZE(skl_primary_formats); 13690 num_formats = ARRAY_SIZE(skl_primary_formats);
13654 } 13691 }
13655 13692
13656 if (skl_plane_has_ccs(dev_priv, pipe, PLANE_PRIMARY)) 13693 if (primary->has_ccs)
13657 modifiers = skl_format_modifiers_ccs; 13694 modifiers = skl_format_modifiers_ccs;
13658 else 13695 else
13659 modifiers = skl_format_modifiers_noccs; 13696 modifiers = skl_format_modifiers_noccs;
@@ -13661,6 +13698,8 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13661 primary->update_plane = skl_update_plane; 13698 primary->update_plane = skl_update_plane;
13662 primary->disable_plane = skl_disable_plane; 13699 primary->disable_plane = skl_disable_plane;
13663 primary->get_hw_state = skl_plane_get_hw_state; 13700 primary->get_hw_state = skl_plane_get_hw_state;
13701
13702 plane_funcs = &skl_plane_funcs;
13664 } else if (INTEL_GEN(dev_priv) >= 4) { 13703 } else if (INTEL_GEN(dev_priv) >= 4) {
13665 intel_primary_formats = i965_primary_formats; 13704 intel_primary_formats = i965_primary_formats;
13666 num_formats = ARRAY_SIZE(i965_primary_formats); 13705 num_formats = ARRAY_SIZE(i965_primary_formats);
@@ -13669,6 +13708,8 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13669 primary->update_plane = i9xx_update_plane; 13708 primary->update_plane = i9xx_update_plane;
13670 primary->disable_plane = i9xx_disable_plane; 13709 primary->disable_plane = i9xx_disable_plane;
13671 primary->get_hw_state = i9xx_plane_get_hw_state; 13710 primary->get_hw_state = i9xx_plane_get_hw_state;
13711
13712 plane_funcs = &i965_plane_funcs;
13672 } else { 13713 } else {
13673 intel_primary_formats = i8xx_primary_formats; 13714 intel_primary_formats = i8xx_primary_formats;
13674 num_formats = ARRAY_SIZE(i8xx_primary_formats); 13715 num_formats = ARRAY_SIZE(i8xx_primary_formats);
@@ -13677,25 +13718,27 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13677 primary->update_plane = i9xx_update_plane; 13718 primary->update_plane = i9xx_update_plane;
13678 primary->disable_plane = i9xx_disable_plane; 13719 primary->disable_plane = i9xx_disable_plane;
13679 primary->get_hw_state = i9xx_plane_get_hw_state; 13720 primary->get_hw_state = i9xx_plane_get_hw_state;
13721
13722 plane_funcs = &i8xx_plane_funcs;
13680 } 13723 }
13681 13724
13682 if (INTEL_GEN(dev_priv) >= 9) 13725 if (INTEL_GEN(dev_priv) >= 9)
13683 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, 13726 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13684 0, &intel_plane_funcs, 13727 0, plane_funcs,
13685 intel_primary_formats, num_formats, 13728 intel_primary_formats, num_formats,
13686 modifiers, 13729 modifiers,
13687 DRM_PLANE_TYPE_PRIMARY, 13730 DRM_PLANE_TYPE_PRIMARY,
13688 "plane 1%c", pipe_name(pipe)); 13731 "plane 1%c", pipe_name(pipe));
13689 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) 13732 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13690 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, 13733 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13691 0, &intel_plane_funcs, 13734 0, plane_funcs,
13692 intel_primary_formats, num_formats, 13735 intel_primary_formats, num_formats,
13693 modifiers, 13736 modifiers,
13694 DRM_PLANE_TYPE_PRIMARY, 13737 DRM_PLANE_TYPE_PRIMARY,
13695 "primary %c", pipe_name(pipe)); 13738 "primary %c", pipe_name(pipe));
13696 else 13739 else
13697 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, 13740 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13698 0, &intel_plane_funcs, 13741 0, plane_funcs,
13699 intel_primary_formats, num_formats, 13742 intel_primary_formats, num_formats,
13700 modifiers, 13743 modifiers,
13701 DRM_PLANE_TYPE_PRIMARY, 13744 DRM_PLANE_TYPE_PRIMARY,
@@ -15666,9 +15709,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
15666 * rely on the connector_mask being accurate. 15709 * rely on the connector_mask being accurate.
15667 */ 15710 */
15668 encoder->base.crtc->state->connector_mask |= 15711 encoder->base.crtc->state->connector_mask |=
15669 1 << drm_connector_index(&connector->base); 15712 drm_connector_mask(&connector->base);
15670 encoder->base.crtc->state->encoder_mask |= 15713 encoder->base.crtc->state->encoder_mask |=
15671 1 << drm_encoder_index(&encoder->base); 15714 drm_encoder_mask(&encoder->base);
15672 } 15715 }
15673 15716
15674 } else { 15717 } else {
@@ -15968,8 +16011,7 @@ void intel_connector_attach_encoder(struct intel_connector *connector,
15968 struct intel_encoder *encoder) 16011 struct intel_encoder *encoder)
15969{ 16012{
15970 connector->encoder = encoder; 16013 connector->encoder = encoder;
15971 drm_mode_connector_attach_encoder(&connector->base, 16014 drm_connector_attach_encoder(&connector->base, &encoder->base);
15972 &encoder->base);
15973} 16015}
15974 16016
15975/* 16017/*
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 7559dfc235a2..9292001cdd14 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -265,7 +265,7 @@ struct intel_link_m_n {
265 &(dev)->mode_config.plane_list, \ 265 &(dev)->mode_config.plane_list, \
266 base.head) \ 266 base.head) \
267 for_each_if((plane_mask) & \ 267 for_each_if((plane_mask) & \
268 BIT(drm_plane_index(&intel_plane->base))) 268 drm_plane_mask(&intel_plane->base)))
269 269
270#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 270#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
271 list_for_each_entry(intel_plane, \ 271 list_for_each_entry(intel_plane, \
@@ -282,7 +282,7 @@ struct intel_link_m_n {
282 list_for_each_entry(intel_crtc, \ 282 list_for_each_entry(intel_crtc, \
283 &(dev)->mode_config.crtc_list, \ 283 &(dev)->mode_config.crtc_list, \
284 base.head) \ 284 base.head) \
285 for_each_if((crtc_mask) & BIT(drm_crtc_index(&intel_crtc->base))) 285 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base))
286 286
287#define for_each_intel_encoder(dev, intel_encoder) \ 287#define for_each_intel_encoder(dev, intel_encoder) \
288 list_for_each_entry(intel_encoder, \ 288 list_for_each_entry(intel_encoder, \
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fee23cf93a2b..cd0f649b57a5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4333,6 +4333,9 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
4333 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 4333 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4334 } 4334 }
4335 4335
4336 /* Handle CEC interrupts, if any */
4337 drm_dp_cec_irq(&intel_dp->aux);
4338
4336 /* defer to the hotplug work for link retraining if needed */ 4339 /* defer to the hotplug work for link retraining if needed */
4337 if (intel_dp_needs_link_retrain(intel_dp)) 4340 if (intel_dp_needs_link_retrain(intel_dp))
4338 return false; 4341 return false;
@@ -4642,6 +4645,7 @@ intel_dp_set_edid(struct intel_dp *intel_dp)
4642 intel_connector->detect_edid = edid; 4645 intel_connector->detect_edid = edid;
4643 4646
4644 intel_dp->has_audio = drm_detect_monitor_audio(edid); 4647 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4648 drm_dp_cec_set_edid(&intel_dp->aux, edid);
4645} 4649}
4646 4650
4647static void 4651static void
@@ -4649,6 +4653,7 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
4649{ 4653{
4650 struct intel_connector *intel_connector = intel_dp->attached_connector; 4654 struct intel_connector *intel_connector = intel_dp->attached_connector;
4651 4655
4656 drm_dp_cec_unset_edid(&intel_dp->aux);
4652 kfree(intel_connector->detect_edid); 4657 kfree(intel_connector->detect_edid);
4653 intel_connector->detect_edid = NULL; 4658 intel_connector->detect_edid = NULL;
4654 4659
@@ -4837,6 +4842,7 @@ static int
4837intel_dp_connector_register(struct drm_connector *connector) 4842intel_dp_connector_register(struct drm_connector *connector)
4838{ 4843{
4839 struct intel_dp *intel_dp = intel_attached_dp(connector); 4844 struct intel_dp *intel_dp = intel_attached_dp(connector);
4845 struct drm_device *dev = connector->dev;
4840 int ret; 4846 int ret;
4841 4847
4842 ret = intel_connector_register(connector); 4848 ret = intel_connector_register(connector);
@@ -4849,13 +4855,20 @@ intel_dp_connector_register(struct drm_connector *connector)
4849 intel_dp->aux.name, connector->kdev->kobj.name); 4855 intel_dp->aux.name, connector->kdev->kobj.name);
4850 4856
4851 intel_dp->aux.dev = connector->kdev; 4857 intel_dp->aux.dev = connector->kdev;
4852 return drm_dp_aux_register(&intel_dp->aux); 4858 ret = drm_dp_aux_register(&intel_dp->aux);
4859 if (!ret)
4860 drm_dp_cec_register_connector(&intel_dp->aux,
4861 connector->name, dev->dev);
4862 return ret;
4853} 4863}
4854 4864
4855static void 4865static void
4856intel_dp_connector_unregister(struct drm_connector *connector) 4866intel_dp_connector_unregister(struct drm_connector *connector)
4857{ 4867{
4858 drm_dp_aux_unregister(&intel_attached_dp(connector)->aux); 4868 struct intel_dp *intel_dp = intel_attached_dp(connector);
4869
4870 drm_dp_cec_unregister_connector(&intel_dp->aux);
4871 drm_dp_aux_unregister(&intel_dp->aux);
4859 intel_connector_unregister(connector); 4872 intel_connector_unregister(connector);
4860} 4873}
4861 4874
@@ -6051,7 +6064,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6051 edid = drm_get_edid(connector, &intel_dp->aux.ddc); 6064 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
6052 if (edid) { 6065 if (edid) {
6053 if (drm_add_edid_modes(connector, edid)) { 6066 if (drm_add_edid_modes(connector, edid)) {
6054 drm_mode_connector_update_edid_property(connector, 6067 drm_connector_update_edid_property(connector,
6055 edid); 6068 edid);
6056 } else { 6069 } else {
6057 kfree(edid); 6070 kfree(edid);
@@ -6140,8 +6153,8 @@ static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6140 /* Set connector link status to BAD and send a Uevent to notify 6153 /* Set connector link status to BAD and send a Uevent to notify
6141 * userspace to do a modeset. 6154 * userspace to do a modeset.
6142 */ 6155 */
6143 drm_mode_connector_set_link_status_property(connector, 6156 drm_connector_set_link_status_property(connector,
6144 DRM_MODE_LINK_STATUS_BAD); 6157 DRM_MODE_LINK_STATUS_BAD);
6145 mutex_unlock(&connector->dev->mode_config.mutex); 6158 mutex_unlock(&connector->dev->mode_config.mutex);
6146 /* Send Hotplug uevent so userspace can reprobe */ 6159 /* Send Hotplug uevent so userspace can reprobe */
6147 drm_kms_helper_hotplug_event(connector->dev); 6160 drm_kms_helper_hotplug_event(connector->dev);
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index d88d0f5abdce..18c65f8e4fe8 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -402,20 +402,10 @@ static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *c
402 return &intel_dp->mst_encoders[crtc->pipe]->base.base; 402 return &intel_dp->mst_encoders[crtc->pipe]->base.base;
403} 403}
404 404
405static struct drm_encoder *intel_mst_best_encoder(struct drm_connector *connector)
406{
407 struct intel_connector *intel_connector = to_intel_connector(connector);
408 struct intel_dp *intel_dp = intel_connector->mst_port;
409 if (!intel_dp)
410 return NULL;
411 return &intel_dp->mst_encoders[0]->base.base;
412}
413
414static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = { 405static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = {
415 .get_modes = intel_dp_mst_get_modes, 406 .get_modes = intel_dp_mst_get_modes,
416 .mode_valid = intel_dp_mst_mode_valid, 407 .mode_valid = intel_dp_mst_mode_valid,
417 .atomic_best_encoder = intel_mst_atomic_best_encoder, 408 .atomic_best_encoder = intel_mst_atomic_best_encoder,
418 .best_encoder = intel_mst_best_encoder,
419 .atomic_check = intel_dp_mst_atomic_check, 409 .atomic_check = intel_dp_mst_atomic_check,
420}; 410};
421 411
@@ -475,8 +465,7 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
475 struct drm_encoder *enc = 465 struct drm_encoder *enc =
476 &intel_dp->mst_encoders[pipe]->base.base; 466 &intel_dp->mst_encoders[pipe]->base.base;
477 467
478 ret = drm_mode_connector_attach_encoder(&intel_connector->base, 468 ret = drm_connector_attach_encoder(&intel_connector->base, enc);
479 enc);
480 if (ret) 469 if (ret)
481 goto err; 470 goto err;
482 } 471 }
@@ -484,7 +473,7 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
484 drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0); 473 drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0);
485 drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0); 474 drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0);
486 475
487 ret = drm_mode_connector_set_path_property(connector, pathprop); 476 ret = drm_connector_set_path_property(connector, pathprop);
488 if (ret) 477 if (ret)
489 goto err; 478 goto err;
490 479
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index e046c4f668e0..7e5e6eb5dfe2 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -163,8 +163,8 @@ void intel_enable_shared_dpll(struct intel_crtc *crtc)
163 struct drm_device *dev = crtc->base.dev; 163 struct drm_device *dev = crtc->base.dev;
164 struct drm_i915_private *dev_priv = to_i915(dev); 164 struct drm_i915_private *dev_priv = to_i915(dev);
165 struct intel_shared_dpll *pll = crtc->config->shared_dpll; 165 struct intel_shared_dpll *pll = crtc->config->shared_dpll;
166 unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base); 166 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
167 unsigned old_mask; 167 unsigned int old_mask;
168 168
169 if (WARN_ON(pll == NULL)) 169 if (WARN_ON(pll == NULL))
170 return; 170 return;
@@ -207,7 +207,7 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc)
207{ 207{
208 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 208 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
209 struct intel_shared_dpll *pll = crtc->config->shared_dpll; 209 struct intel_shared_dpll *pll = crtc->config->shared_dpll;
210 unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base); 210 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
211 211
212 /* PCH only available on ILK+ */ 212 /* PCH only available on ILK+ */
213 if (INTEL_GEN(dev_priv) < 5) 213 if (INTEL_GEN(dev_priv) < 5)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index edcfd85e7b94..c275f91244a6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -949,6 +949,7 @@ struct intel_plane {
949 enum pipe pipe; 949 enum pipe pipe;
950 bool can_scale; 950 bool can_scale;
951 bool has_fbc; 951 bool has_fbc;
952 bool has_ccs;
952 int max_downscale; 953 int max_downscale;
953 uint32_t frontbuffer_bit; 954 uint32_t frontbuffer_bit;
954 955
@@ -2086,7 +2087,6 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2086 2087
2087 2088
2088/* intel_sprite.c */ 2089/* intel_sprite.c */
2089bool intel_format_is_yuv(u32 format);
2090int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, 2090int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2091 int usecs); 2091 int usecs);
2092struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv, 2092struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
@@ -2102,7 +2102,6 @@ void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
2102bool skl_plane_get_hw_state(struct intel_plane *plane, enum pipe *pipe); 2102bool skl_plane_get_hw_state(struct intel_plane *plane, enum pipe *pipe);
2103bool skl_plane_has_ccs(struct drm_i915_private *dev_priv, 2103bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
2104 enum pipe pipe, enum plane_id plane_id); 2104 enum pipe pipe, enum plane_id plane_id);
2105bool intel_format_is_yuv(uint32_t format);
2106bool skl_plane_has_planar(struct drm_i915_private *dev_priv, 2105bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
2107 enum pipe pipe, enum plane_id plane_id); 2106 enum pipe pipe, enum plane_id plane_id);
2108 2107
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 2db5da550a1c..0cc6a861bcf8 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -429,7 +429,7 @@ int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
429 if (num_downstream == 0) 429 if (num_downstream == 0)
430 return -EINVAL; 430 return -EINVAL;
431 431
432 ksv_fifo = kzalloc(num_downstream * DRM_HDCP_KSV_LEN, GFP_KERNEL); 432 ksv_fifo = kcalloc(DRM_HDCP_KSV_LEN, num_downstream, GFP_KERNEL);
433 if (!ksv_fifo) 433 if (!ksv_fifo)
434 return -ENOMEM; 434 return -ENOMEM;
435 435
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 98ad4313d9f2..8363fbd18ee8 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -467,7 +467,8 @@ static void intel_write_infoframe(struct drm_encoder *encoder,
467} 467}
468 468
469static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, 469static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
470 const struct intel_crtc_state *crtc_state) 470 const struct intel_crtc_state *crtc_state,
471 const struct drm_connector_state *conn_state)
471{ 472{
472 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 473 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
473 const struct drm_display_mode *adjusted_mode = 474 const struct drm_display_mode *adjusted_mode =
@@ -497,6 +498,9 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
497 intel_hdmi->rgb_quant_range_selectable, 498 intel_hdmi->rgb_quant_range_selectable,
498 is_hdmi2_sink); 499 is_hdmi2_sink);
499 500
501 drm_hdmi_avi_infoframe_content_type(&frame.avi,
502 conn_state);
503
500 /* TODO: handle pixel repetition for YCBCR420 outputs */ 504 /* TODO: handle pixel repetition for YCBCR420 outputs */
501 intel_write_infoframe(encoder, crtc_state, &frame); 505 intel_write_infoframe(encoder, crtc_state, &frame);
502} 506}
@@ -592,7 +596,7 @@ static void g4x_set_infoframes(struct drm_encoder *encoder,
592 I915_WRITE(reg, val); 596 I915_WRITE(reg, val);
593 POSTING_READ(reg); 597 POSTING_READ(reg);
594 598
595 intel_hdmi_set_avi_infoframe(encoder, crtc_state); 599 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
596 intel_hdmi_set_spd_infoframe(encoder, crtc_state); 600 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
597 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state); 601 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
598} 602}
@@ -733,7 +737,7 @@ static void ibx_set_infoframes(struct drm_encoder *encoder,
733 I915_WRITE(reg, val); 737 I915_WRITE(reg, val);
734 POSTING_READ(reg); 738 POSTING_READ(reg);
735 739
736 intel_hdmi_set_avi_infoframe(encoder, crtc_state); 740 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
737 intel_hdmi_set_spd_infoframe(encoder, crtc_state); 741 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
738 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state); 742 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
739} 743}
@@ -776,7 +780,7 @@ static void cpt_set_infoframes(struct drm_encoder *encoder,
776 I915_WRITE(reg, val); 780 I915_WRITE(reg, val);
777 POSTING_READ(reg); 781 POSTING_READ(reg);
778 782
779 intel_hdmi_set_avi_infoframe(encoder, crtc_state); 783 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
780 intel_hdmi_set_spd_infoframe(encoder, crtc_state); 784 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
781 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state); 785 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
782} 786}
@@ -829,7 +833,7 @@ static void vlv_set_infoframes(struct drm_encoder *encoder,
829 I915_WRITE(reg, val); 833 I915_WRITE(reg, val);
830 POSTING_READ(reg); 834 POSTING_READ(reg);
831 835
832 intel_hdmi_set_avi_infoframe(encoder, crtc_state); 836 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
833 intel_hdmi_set_spd_infoframe(encoder, crtc_state); 837 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
834 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state); 838 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
835} 839}
@@ -862,7 +866,7 @@ static void hsw_set_infoframes(struct drm_encoder *encoder,
862 I915_WRITE(reg, val); 866 I915_WRITE(reg, val);
863 POSTING_READ(reg); 867 POSTING_READ(reg);
864 868
865 intel_hdmi_set_avi_infoframe(encoder, crtc_state); 869 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
866 intel_hdmi_set_spd_infoframe(encoder, crtc_state); 870 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
867 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state); 871 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
868} 872}
@@ -2092,6 +2096,7 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *c
2092 intel_attach_force_audio_property(connector); 2096 intel_attach_force_audio_property(connector);
2093 intel_attach_broadcast_rgb_property(connector); 2097 intel_attach_broadcast_rgb_property(connector);
2094 intel_attach_aspect_ratio_property(connector); 2098 intel_attach_aspect_ratio_property(connector);
2099 drm_connector_attach_content_type_property(connector);
2095 connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 2100 connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2096} 2101}
2097 2102
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index a35404119257..f9f3b0885ba5 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -999,7 +999,7 @@ void intel_lvds_init(struct drm_i915_private *dev_priv)
999 intel_gmbus_get_adapter(dev_priv, pin)); 999 intel_gmbus_get_adapter(dev_priv, pin));
1000 if (edid) { 1000 if (edid) {
1001 if (drm_add_edid_modes(connector, edid)) { 1001 if (drm_add_edid_modes(connector, edid)) {
1002 drm_mode_connector_update_edid_property(connector, 1002 drm_connector_update_edid_property(connector,
1003 edid); 1003 edid);
1004 } else { 1004 } else {
1005 kfree(edid); 1005 kfree(edid);
diff --git a/drivers/gpu/drm/i915/intel_modes.c b/drivers/gpu/drm/i915/intel_modes.c
index b39846613e3c..ca44bf368e24 100644
--- a/drivers/gpu/drm/i915/intel_modes.c
+++ b/drivers/gpu/drm/i915/intel_modes.c
@@ -40,7 +40,7 @@ int intel_connector_update_modes(struct drm_connector *connector,
40{ 40{
41 int ret; 41 int ret;
42 42
43 drm_mode_connector_update_edid_property(connector, edid); 43 drm_connector_update_edid_property(connector, edid);
44 ret = drm_add_edid_modes(connector, edid); 44 ret = drm_add_edid_modes(connector, edid);
45 45
46 return ret; 46 return ret;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 69bd7f697f6d..33faad3197fe 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1023,6 +1023,8 @@ int intel_ring_pin(struct intel_ring *ring,
1023 flags |= PIN_OFFSET_BIAS | offset_bias; 1023 flags |= PIN_OFFSET_BIAS | offset_bias;
1024 if (vma->obj->stolen) 1024 if (vma->obj->stolen)
1025 flags |= PIN_MAPPABLE; 1025 flags |= PIN_MAPPABLE;
1026 else
1027 flags |= PIN_HIGH;
1026 1028
1027 if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { 1029 if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1028 if (flags & PIN_MAPPABLE || map == I915_MAP_WC) 1030 if (flags & PIN_MAPPABLE || map == I915_MAP_WC)
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 5417c54f67da..812fe7b06f87 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1911,7 +1911,7 @@ static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1911 if (edid != NULL) { 1911 if (edid != NULL) {
1912 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), 1912 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1913 edid)) { 1913 edid)) {
1914 drm_mode_connector_update_edid_property(connector, edid); 1914 drm_connector_update_edid_property(connector, edid);
1915 drm_add_edid_modes(connector, edid); 1915 drm_add_edid_modes(connector, edid);
1916 } 1916 }
1917 1917
@@ -2798,9 +2798,8 @@ static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2798 return false; 2798 return false;
2799 2799
2800 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2800 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2801 drm_property_add_enum( 2801 drm_property_add_enum(intel_sdvo_connector->tv_format, i,
2802 intel_sdvo_connector->tv_format, i, 2802 tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
2803 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
2804 2803
2805 intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0]; 2804 intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0];
2806 drm_object_attach_property(&intel_sdvo_connector->base.base.base, 2805 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 3a4a26dd770f..f7026e887fa9 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -41,20 +41,6 @@
41#include <drm/i915_drm.h> 41#include <drm/i915_drm.h>
42#include "i915_drv.h" 42#include "i915_drv.h"
43 43
44bool intel_format_is_yuv(u32 format)
45{
46 switch (format) {
47 case DRM_FORMAT_YUYV:
48 case DRM_FORMAT_UYVY:
49 case DRM_FORMAT_VYUY:
50 case DRM_FORMAT_YVYU:
51 case DRM_FORMAT_NV12:
52 return true;
53 default:
54 return false;
55 }
56}
57
58int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, 44int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
59 int usecs) 45 int usecs)
60{ 46{
@@ -416,7 +402,7 @@ chv_update_csc(const struct intel_plane_state *plane_state)
416 const s16 *csc = csc_matrix[plane_state->base.color_encoding]; 402 const s16 *csc = csc_matrix[plane_state->base.color_encoding];
417 403
418 /* Seems RGB data bypasses the CSC always */ 404 /* Seems RGB data bypasses the CSC always */
419 if (!intel_format_is_yuv(fb->format->format)) 405 if (!fb->format->is_yuv)
420 return; 406 return;
421 407
422 I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0)); 408 I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
@@ -451,7 +437,7 @@ vlv_update_clrc(const struct intel_plane_state *plane_state)
451 enum plane_id plane_id = plane->id; 437 enum plane_id plane_id = plane->id;
452 int contrast, brightness, sh_scale, sh_sin, sh_cos; 438 int contrast, brightness, sh_scale, sh_sin, sh_cos;
453 439
454 if (intel_format_is_yuv(fb->format->format) && 440 if (fb->format->is_yuv &&
455 plane_state->base.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) { 441 plane_state->base.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
456 /* 442 /*
457 * Expand limited range to full range: 443 * Expand limited range to full range:
@@ -978,22 +964,12 @@ intel_check_sprite_plane(struct intel_plane *plane,
978 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 964 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
979 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 965 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
980 struct drm_framebuffer *fb = state->base.fb; 966 struct drm_framebuffer *fb = state->base.fb;
981 int crtc_x, crtc_y;
982 unsigned int crtc_w, crtc_h;
983 uint32_t src_x, src_y, src_w, src_h;
984 struct drm_rect *src = &state->base.src;
985 struct drm_rect *dst = &state->base.dst;
986 struct drm_rect clip = {};
987 int max_stride = INTEL_GEN(dev_priv) >= 9 ? 32768 : 16384; 967 int max_stride = INTEL_GEN(dev_priv) >= 9 ? 32768 : 16384;
988 int hscale, vscale;
989 int max_scale, min_scale; 968 int max_scale, min_scale;
990 bool can_scale; 969 bool can_scale;
991 int ret; 970 int ret;
992 uint32_t pixel_format = 0; 971 uint32_t pixel_format = 0;
993 972
994 *src = drm_plane_state_src(&state->base);
995 *dst = drm_plane_state_dest(&state->base);
996
997 if (!fb) { 973 if (!fb) {
998 state->base.visible = false; 974 state->base.visible = false;
999 return 0; 975 return 0;
@@ -1032,64 +1008,19 @@ intel_check_sprite_plane(struct intel_plane *plane,
1032 min_scale = plane->can_scale ? 1 : (1 << 16); 1008 min_scale = plane->can_scale ? 1 : (1 << 16);
1033 } 1009 }
1034 1010
1035 /* 1011 ret = drm_atomic_helper_check_plane_state(&state->base,
1036 * FIXME the following code does a bunch of fuzzy adjustments to the 1012 &crtc_state->base,
1037 * coordinates and sizes. We probably need some way to decide whether 1013 min_scale, max_scale,
1038 * more strict checking should be done instead. 1014 true, true);
1039 */ 1015 if (ret)
1040 drm_rect_rotate(src, fb->width << 16, fb->height << 16, 1016 return ret;
1041 state->base.rotation);
1042
1043 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
1044 BUG_ON(hscale < 0);
1045
1046 vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
1047 BUG_ON(vscale < 0);
1048
1049 if (crtc_state->base.enable)
1050 drm_mode_get_hv_timing(&crtc_state->base.mode,
1051 &clip.x2, &clip.y2);
1052
1053 state->base.visible = drm_rect_clip_scaled(src, dst, &clip, hscale, vscale);
1054
1055 crtc_x = dst->x1;
1056 crtc_y = dst->y1;
1057 crtc_w = drm_rect_width(dst);
1058 crtc_h = drm_rect_height(dst);
1059 1017
1060 if (state->base.visible) { 1018 if (state->base.visible) {
1061 /* check again in case clipping clamped the results */ 1019 struct drm_rect *src = &state->base.src;
1062 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale); 1020 struct drm_rect *dst = &state->base.dst;
1063 if (hscale < 0) { 1021 unsigned int crtc_w = drm_rect_width(dst);
1064 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n"); 1022 unsigned int crtc_h = drm_rect_height(dst);
1065 drm_rect_debug_print("src: ", src, true); 1023 uint32_t src_x, src_y, src_w, src_h;
1066 drm_rect_debug_print("dst: ", dst, false);
1067
1068 return hscale;
1069 }
1070
1071 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
1072 if (vscale < 0) {
1073 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
1074 drm_rect_debug_print("src: ", src, true);
1075 drm_rect_debug_print("dst: ", dst, false);
1076
1077 return vscale;
1078 }
1079
1080 /* Make the source viewport size an exact multiple of the scaling factors. */
1081 drm_rect_adjust_size(src,
1082 drm_rect_width(dst) * hscale - drm_rect_width(src),
1083 drm_rect_height(dst) * vscale - drm_rect_height(src));
1084
1085 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
1086 state->base.rotation);
1087
1088 /* sanity check to make sure the src viewport wasn't enlarged */
1089 WARN_ON(src->x1 < (int) state->base.src_x ||
1090 src->y1 < (int) state->base.src_y ||
1091 src->x2 > (int) state->base.src_x + state->base.src_w ||
1092 src->y2 > (int) state->base.src_y + state->base.src_h);
1093 1024
1094 /* 1025 /*
1095 * Hardware doesn't handle subpixel coordinates. 1026 * Hardware doesn't handle subpixel coordinates.
@@ -1102,59 +1033,40 @@ intel_check_sprite_plane(struct intel_plane *plane,
1102 src_y = src->y1 >> 16; 1033 src_y = src->y1 >> 16;
1103 src_h = drm_rect_height(src) >> 16; 1034 src_h = drm_rect_height(src) >> 16;
1104 1035
1105 if (intel_format_is_yuv(fb->format->format) && 1036 src->x1 = src_x << 16;
1106 fb->format->format != DRM_FORMAT_NV12) { 1037 src->x2 = (src_x + src_w) << 16;
1107 src_x &= ~1; 1038 src->y1 = src_y << 16;
1108 src_w &= ~1; 1039 src->y2 = (src_y + src_h) << 16;
1109
1110 /*
1111 * Must keep src and dst the
1112 * same if we can't scale.
1113 */
1114 if (!can_scale)
1115 crtc_w &= ~1;
1116 1040
1117 if (crtc_w == 0) 1041 if (fb->format->is_yuv &&
1118 state->base.visible = false; 1042 fb->format->format != DRM_FORMAT_NV12 &&
1043 (src_x % 2 || src_w % 2)) {
1044 DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
1045 src_x, src_w);
1046 return -EINVAL;
1119 } 1047 }
1120 }
1121
1122 /* Check size restrictions when scaling */
1123 if (state->base.visible && (src_w != crtc_w || src_h != crtc_h)) {
1124 unsigned int width_bytes;
1125 int cpp = fb->format->cpp[0];
1126
1127 WARN_ON(!can_scale);
1128 1048
1129 /* FIXME interlacing min height is 6 */ 1049 /* Check size restrictions when scaling */
1050 if (src_w != crtc_w || src_h != crtc_h) {
1051 unsigned int width_bytes;
1052 int cpp = fb->format->cpp[0];
1130 1053
1131 if (crtc_w < 3 || crtc_h < 3) 1054 WARN_ON(!can_scale);
1132 state->base.visible = false;
1133 1055
1134 if (src_w < 3 || src_h < 3) 1056 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
1135 state->base.visible = false;
1136 1057
1137 width_bytes = ((src_x * cpp) & 63) + src_w * cpp; 1058 /* FIXME interlacing min height is 6 */
1138 1059 if (INTEL_GEN(dev_priv) < 9 && (
1139 if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 || 1060 src_w < 3 || src_h < 3 ||
1140 width_bytes > 4096 || fb->pitches[0] > 4096)) { 1061 src_w > 2048 || src_h > 2048 ||
1141 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n"); 1062 crtc_w < 3 || crtc_h < 3 ||
1142 return -EINVAL; 1063 width_bytes > 4096 || fb->pitches[0] > 4096)) {
1064 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
1065 return -EINVAL;
1066 }
1143 } 1067 }
1144 } 1068 }
1145 1069
1146 if (state->base.visible) {
1147 src->x1 = src_x << 16;
1148 src->x2 = (src_x + src_w) << 16;
1149 src->y1 = src_y << 16;
1150 src->y2 = (src_y + src_h) << 16;
1151 }
1152
1153 dst->x1 = crtc_x;
1154 dst->x2 = crtc_x + crtc_w;
1155 dst->y1 = crtc_y;
1156 dst->y2 = crtc_y + crtc_h;
1157
1158 if (INTEL_GEN(dev_priv) >= 9) { 1070 if (INTEL_GEN(dev_priv) >= 9) {
1159 ret = skl_check_plane_surface(crtc_state, state); 1071 ret = skl_check_plane_surface(crtc_state, state);
1160 if (ret) 1072 if (ret)
@@ -1385,8 +1297,17 @@ static const uint64_t skl_plane_format_modifiers_ccs[] = {
1385 DRM_FORMAT_MOD_INVALID 1297 DRM_FORMAT_MOD_INVALID
1386}; 1298};
1387 1299
1388static bool g4x_mod_supported(uint32_t format, uint64_t modifier) 1300static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
1301 u32 format, u64 modifier)
1389{ 1302{
1303 switch (modifier) {
1304 case DRM_FORMAT_MOD_LINEAR:
1305 case I915_FORMAT_MOD_X_TILED:
1306 break;
1307 default:
1308 return false;
1309 }
1310
1390 switch (format) { 1311 switch (format) {
1391 case DRM_FORMAT_XRGB8888: 1312 case DRM_FORMAT_XRGB8888:
1392 case DRM_FORMAT_YUYV: 1313 case DRM_FORMAT_YUYV:
@@ -1402,8 +1323,17 @@ static bool g4x_mod_supported(uint32_t format, uint64_t modifier)
1402 } 1323 }
1403} 1324}
1404 1325
1405static bool snb_mod_supported(uint32_t format, uint64_t modifier) 1326static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
1327 u32 format, u64 modifier)
1406{ 1328{
1329 switch (modifier) {
1330 case DRM_FORMAT_MOD_LINEAR:
1331 case I915_FORMAT_MOD_X_TILED:
1332 break;
1333 default:
1334 return false;
1335 }
1336
1407 switch (format) { 1337 switch (format) {
1408 case DRM_FORMAT_XRGB8888: 1338 case DRM_FORMAT_XRGB8888:
1409 case DRM_FORMAT_XBGR8888: 1339 case DRM_FORMAT_XBGR8888:
@@ -1420,8 +1350,17 @@ static bool snb_mod_supported(uint32_t format, uint64_t modifier)
1420 } 1350 }
1421} 1351}
1422 1352
1423static bool vlv_mod_supported(uint32_t format, uint64_t modifier) 1353static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
1354 u32 format, u64 modifier)
1424{ 1355{
1356 switch (modifier) {
1357 case DRM_FORMAT_MOD_LINEAR:
1358 case I915_FORMAT_MOD_X_TILED:
1359 break;
1360 default:
1361 return false;
1362 }
1363
1425 switch (format) { 1364 switch (format) {
1426 case DRM_FORMAT_RGB565: 1365 case DRM_FORMAT_RGB565:
1427 case DRM_FORMAT_ABGR8888: 1366 case DRM_FORMAT_ABGR8888:
@@ -1443,8 +1382,26 @@ static bool vlv_mod_supported(uint32_t format, uint64_t modifier)
1443 } 1382 }
1444} 1383}
1445 1384
1446static bool skl_mod_supported(uint32_t format, uint64_t modifier) 1385static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
1386 u32 format, u64 modifier)
1447{ 1387{
1388 struct intel_plane *plane = to_intel_plane(_plane);
1389
1390 switch (modifier) {
1391 case DRM_FORMAT_MOD_LINEAR:
1392 case I915_FORMAT_MOD_X_TILED:
1393 case I915_FORMAT_MOD_Y_TILED:
1394 case I915_FORMAT_MOD_Yf_TILED:
1395 break;
1396 case I915_FORMAT_MOD_Y_TILED_CCS:
1397 case I915_FORMAT_MOD_Yf_TILED_CCS:
1398 if (!plane->has_ccs)
1399 return false;
1400 break;
1401 default:
1402 return false;
1403 }
1404
1448 switch (format) { 1405 switch (format) {
1449 case DRM_FORMAT_XRGB8888: 1406 case DRM_FORMAT_XRGB8888:
1450 case DRM_FORMAT_XBGR8888: 1407 case DRM_FORMAT_XBGR8888:
@@ -1476,30 +1433,40 @@ static bool skl_mod_supported(uint32_t format, uint64_t modifier)
1476 } 1433 }
1477} 1434}
1478 1435
1479static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane, 1436static const struct drm_plane_funcs g4x_sprite_funcs = {
1480 uint32_t format, 1437 .update_plane = drm_atomic_helper_update_plane,
1481 uint64_t modifier) 1438 .disable_plane = drm_atomic_helper_disable_plane,
1482{ 1439 .destroy = intel_plane_destroy,
1483 struct drm_i915_private *dev_priv = to_i915(plane->dev); 1440 .atomic_get_property = intel_plane_atomic_get_property,
1484 1441 .atomic_set_property = intel_plane_atomic_set_property,
1485 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) 1442 .atomic_duplicate_state = intel_plane_duplicate_state,
1486 return false; 1443 .atomic_destroy_state = intel_plane_destroy_state,
1444 .format_mod_supported = g4x_sprite_format_mod_supported,
1445};
1487 1446
1488 if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL && 1447static const struct drm_plane_funcs snb_sprite_funcs = {
1489 modifier != DRM_FORMAT_MOD_LINEAR) 1448 .update_plane = drm_atomic_helper_update_plane,
1490 return false; 1449 .disable_plane = drm_atomic_helper_disable_plane,
1450 .destroy = intel_plane_destroy,
1451 .atomic_get_property = intel_plane_atomic_get_property,
1452 .atomic_set_property = intel_plane_atomic_set_property,
1453 .atomic_duplicate_state = intel_plane_duplicate_state,
1454 .atomic_destroy_state = intel_plane_destroy_state,
1455 .format_mod_supported = snb_sprite_format_mod_supported,
1456};
1491 1457
1492 if (INTEL_GEN(dev_priv) >= 9) 1458static const struct drm_plane_funcs vlv_sprite_funcs = {
1493 return skl_mod_supported(format, modifier); 1459 .update_plane = drm_atomic_helper_update_plane,
1494 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1460 .disable_plane = drm_atomic_helper_disable_plane,
1495 return vlv_mod_supported(format, modifier); 1461 .destroy = intel_plane_destroy,
1496 else if (INTEL_GEN(dev_priv) >= 6) 1462 .atomic_get_property = intel_plane_atomic_get_property,
1497 return snb_mod_supported(format, modifier); 1463 .atomic_set_property = intel_plane_atomic_set_property,
1498 else 1464 .atomic_duplicate_state = intel_plane_duplicate_state,
1499 return g4x_mod_supported(format, modifier); 1465 .atomic_destroy_state = intel_plane_destroy_state,
1500} 1466 .format_mod_supported = vlv_sprite_format_mod_supported,
1467};
1501 1468
1502static const struct drm_plane_funcs intel_sprite_plane_funcs = { 1469static const struct drm_plane_funcs skl_plane_funcs = {
1503 .update_plane = drm_atomic_helper_update_plane, 1470 .update_plane = drm_atomic_helper_update_plane,
1504 .disable_plane = drm_atomic_helper_disable_plane, 1471 .disable_plane = drm_atomic_helper_disable_plane,
1505 .destroy = intel_plane_destroy, 1472 .destroy = intel_plane_destroy,
@@ -1507,7 +1474,7 @@ static const struct drm_plane_funcs intel_sprite_plane_funcs = {
1507 .atomic_set_property = intel_plane_atomic_set_property, 1474 .atomic_set_property = intel_plane_atomic_set_property,
1508 .atomic_duplicate_state = intel_plane_duplicate_state, 1475 .atomic_duplicate_state = intel_plane_duplicate_state,
1509 .atomic_destroy_state = intel_plane_destroy_state, 1476 .atomic_destroy_state = intel_plane_destroy_state,
1510 .format_mod_supported = intel_sprite_plane_format_mod_supported, 1477 .format_mod_supported = skl_plane_format_mod_supported,
1511}; 1478};
1512 1479
1513bool skl_plane_has_ccs(struct drm_i915_private *dev_priv, 1480bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
@@ -1533,6 +1500,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1533{ 1500{
1534 struct intel_plane *intel_plane = NULL; 1501 struct intel_plane *intel_plane = NULL;
1535 struct intel_plane_state *state = NULL; 1502 struct intel_plane_state *state = NULL;
1503 const struct drm_plane_funcs *plane_funcs;
1536 unsigned long possible_crtcs; 1504 unsigned long possible_crtcs;
1537 const uint32_t *plane_formats; 1505 const uint32_t *plane_formats;
1538 const uint64_t *modifiers; 1506 const uint64_t *modifiers;
@@ -1557,6 +1525,9 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1557 intel_plane->can_scale = true; 1525 intel_plane->can_scale = true;
1558 state->scaler_id = -1; 1526 state->scaler_id = -1;
1559 1527
1528 intel_plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
1529 PLANE_SPRITE0 + plane);
1530
1560 intel_plane->update_plane = skl_update_plane; 1531 intel_plane->update_plane = skl_update_plane;
1561 intel_plane->disable_plane = skl_disable_plane; 1532 intel_plane->disable_plane = skl_disable_plane;
1562 intel_plane->get_hw_state = skl_plane_get_hw_state; 1533 intel_plane->get_hw_state = skl_plane_get_hw_state;
@@ -1570,10 +1541,12 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1570 num_plane_formats = ARRAY_SIZE(skl_plane_formats); 1541 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1571 } 1542 }
1572 1543
1573 if (skl_plane_has_ccs(dev_priv, pipe, PLANE_SPRITE0 + plane)) 1544 if (intel_plane->has_ccs)
1574 modifiers = skl_plane_format_modifiers_ccs; 1545 modifiers = skl_plane_format_modifiers_ccs;
1575 else 1546 else
1576 modifiers = skl_plane_format_modifiers_noccs; 1547 modifiers = skl_plane_format_modifiers_noccs;
1548
1549 plane_funcs = &skl_plane_funcs;
1577 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1550 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1578 intel_plane->can_scale = false; 1551 intel_plane->can_scale = false;
1579 intel_plane->max_downscale = 1; 1552 intel_plane->max_downscale = 1;
@@ -1585,6 +1558,8 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1585 plane_formats = vlv_plane_formats; 1558 plane_formats = vlv_plane_formats;
1586 num_plane_formats = ARRAY_SIZE(vlv_plane_formats); 1559 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1587 modifiers = i9xx_plane_format_modifiers; 1560 modifiers = i9xx_plane_format_modifiers;
1561
1562 plane_funcs = &vlv_sprite_funcs;
1588 } else if (INTEL_GEN(dev_priv) >= 7) { 1563 } else if (INTEL_GEN(dev_priv) >= 7) {
1589 if (IS_IVYBRIDGE(dev_priv)) { 1564 if (IS_IVYBRIDGE(dev_priv)) {
1590 intel_plane->can_scale = true; 1565 intel_plane->can_scale = true;
@@ -1601,6 +1576,8 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1601 plane_formats = snb_plane_formats; 1576 plane_formats = snb_plane_formats;
1602 num_plane_formats = ARRAY_SIZE(snb_plane_formats); 1577 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1603 modifiers = i9xx_plane_format_modifiers; 1578 modifiers = i9xx_plane_format_modifiers;
1579
1580 plane_funcs = &snb_sprite_funcs;
1604 } else { 1581 } else {
1605 intel_plane->can_scale = true; 1582 intel_plane->can_scale = true;
1606 intel_plane->max_downscale = 16; 1583 intel_plane->max_downscale = 16;
@@ -1613,9 +1590,13 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1613 if (IS_GEN6(dev_priv)) { 1590 if (IS_GEN6(dev_priv)) {
1614 plane_formats = snb_plane_formats; 1591 plane_formats = snb_plane_formats;
1615 num_plane_formats = ARRAY_SIZE(snb_plane_formats); 1592 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1593
1594 plane_funcs = &snb_sprite_funcs;
1616 } else { 1595 } else {
1617 plane_formats = g4x_plane_formats; 1596 plane_formats = g4x_plane_formats;
1618 num_plane_formats = ARRAY_SIZE(g4x_plane_formats); 1597 num_plane_formats = ARRAY_SIZE(g4x_plane_formats);
1598
1599 plane_funcs = &g4x_sprite_funcs;
1619 } 1600 }
1620 } 1601 }
1621 1602
@@ -1642,14 +1623,14 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1642 1623
1643 if (INTEL_GEN(dev_priv) >= 9) 1624 if (INTEL_GEN(dev_priv) >= 9)
1644 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base, 1625 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1645 possible_crtcs, &intel_sprite_plane_funcs, 1626 possible_crtcs, plane_funcs,
1646 plane_formats, num_plane_formats, 1627 plane_formats, num_plane_formats,
1647 modifiers, 1628 modifiers,
1648 DRM_PLANE_TYPE_OVERLAY, 1629 DRM_PLANE_TYPE_OVERLAY,
1649 "plane %d%c", plane + 2, pipe_name(pipe)); 1630 "plane %d%c", plane + 2, pipe_name(pipe));
1650 else 1631 else
1651 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base, 1632 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1652 possible_crtcs, &intel_sprite_plane_funcs, 1633 possible_crtcs, plane_funcs,
1653 plane_formats, num_plane_formats, 1634 plane_formats, num_plane_formats,
1654 modifiers, 1635 modifiers,
1655 DRM_PLANE_TYPE_OVERLAY, 1636 DRM_PLANE_TYPE_OVERLAY,
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index f76f2597df5c..47bc5b2ddb56 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -137,7 +137,7 @@ static int intel_uncore_check_forcewake_domains(struct drm_i915_private *dev_pri
137 if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN)) 137 if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN))
138 return 0; 138 return 0;
139 139
140 valid = kzalloc(BITS_TO_LONGS(FW_RANGE) * sizeof(*valid), 140 valid = kcalloc(BITS_TO_LONGS(FW_RANGE), sizeof(*valid),
141 GFP_KERNEL); 141 GFP_KERNEL);
142 if (!valid) 142 if (!valid)
143 return -ENOMEM; 143 return -ENOMEM;
diff --git a/drivers/gpu/drm/i915/selftests/mock_dmabuf.c b/drivers/gpu/drm/i915/selftests/mock_dmabuf.c
index 302f7d103635..ca682caf1062 100644
--- a/drivers/gpu/drm/i915/selftests/mock_dmabuf.c
+++ b/drivers/gpu/drm/i915/selftests/mock_dmabuf.c
@@ -94,18 +94,6 @@ static void mock_dmabuf_vunmap(struct dma_buf *dma_buf, void *vaddr)
94 vm_unmap_ram(vaddr, mock->npages); 94 vm_unmap_ram(vaddr, mock->npages);
95} 95}
96 96
97static void *mock_dmabuf_kmap_atomic(struct dma_buf *dma_buf, unsigned long page_num)
98{
99 struct mock_dmabuf *mock = to_mock(dma_buf);
100
101 return kmap_atomic(mock->pages[page_num]);
102}
103
104static void mock_dmabuf_kunmap_atomic(struct dma_buf *dma_buf, unsigned long page_num, void *addr)
105{
106 kunmap_atomic(addr);
107}
108
109static void *mock_dmabuf_kmap(struct dma_buf *dma_buf, unsigned long page_num) 97static void *mock_dmabuf_kmap(struct dma_buf *dma_buf, unsigned long page_num)
110{ 98{
111 struct mock_dmabuf *mock = to_mock(dma_buf); 99 struct mock_dmabuf *mock = to_mock(dma_buf);
@@ -130,9 +118,7 @@ static const struct dma_buf_ops mock_dmabuf_ops = {
130 .unmap_dma_buf = mock_unmap_dma_buf, 118 .unmap_dma_buf = mock_unmap_dma_buf,
131 .release = mock_dmabuf_release, 119 .release = mock_dmabuf_release,
132 .map = mock_dmabuf_kmap, 120 .map = mock_dmabuf_kmap,
133 .map_atomic = mock_dmabuf_kmap_atomic,
134 .unmap = mock_dmabuf_kunmap, 121 .unmap = mock_dmabuf_kunmap,
135 .unmap_atomic = mock_dmabuf_kunmap_atomic,
136 .mmap = mock_dmabuf_mmap, 122 .mmap = mock_dmabuf_mmap,
137 .vmap = mock_dmabuf_vmap, 123 .vmap = mock_dmabuf_vmap,
138 .vunmap = mock_dmabuf_vunmap, 124 .vunmap = mock_dmabuf_vunmap,