drm/i915/icl: Introduce initial Icelake Workarounds

Inherit workarounds from previous platforms that are still valid for
Icelake.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
  - Since it has been fixed already in upstream, removed the TODO
    comment about WA_SET_BIT for WaInPlaceDecompressionHang.
  - Squashed with this patch:
      drm/i915/icl: add icelake_init_clock_gating()
    from Paulo Zanoni <paulo.r.zanoni@intel.com>
  - Squashed with this patch:
      drm/i915/icl: WaForceEnableNonCoherent
    from Oscar Mateo <oscar.mateo@intel.com>
  - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
    applies to B0 as well.
  - WaPipeControlBefore3DStateSamplePattern WABB was being applied
    to ICL incorrectly.
v4:
  - Wrap the commit message
  - s/dev_priv/p to please checkpatch
v5: Rebased on top of the WA refactoring
v6: Rebased on top of further whitelist registers refactoring (Michel)
v7: Added WaRsForcewakeAddDelayForAck
v8: s/ICL_HDC_CHICKEN0/ICL_HDC_MODE (Mika)
v9:
  - C, not lisp (Chris)
  - WaIncreaseDefaultTLBEntries is the same for GEN > 9_LP (Tvrtko)

Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Tomasz Lis <tomasz.lis@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-2-git-send-email-oscar.mateo@intel.com

1 files changed, 46 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index ec9d340fcb00..73d02d3785d4 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -441,6 +441,27 @@ static int cnl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
         return 0;
 }
 
+static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
+{
+        /* Wa_1604370585:icl (pre-prod)
+         * Formerly known as WaPushConstantDereferenceHoldDisable
+         */
+        if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+                WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+                                  PUSH_CONSTANT_DEREF_DISABLE);
+
+        /* WaForceEnableNonCoherent:icl
+         * This is not the same workaround as in early Gen9 platforms, where
+         * lacking this could cause system hangs, but coherency performance
+         * overhead is high and only a few compute workloads really need it
+         * (the register is whitelisted in hardware now, so UMDs can opt in
+         * for coherency if they have a good reason).
+         */
+        WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
+
+        return 0;
+}
+
 int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 {
         int err = 0;
@@ -465,6 +486,8 @@ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
                 err = cfl_ctx_workarounds_init(dev_priv);
         else if (IS_CANNONLAKE(dev_priv))
                 err = cnl_ctx_workarounds_init(dev_priv);
+        else if (IS_ICELAKE(dev_priv))
+                err = icl_ctx_workarounds_init(dev_priv);
         else
                 MISSING_CASE(INTEL_GEN(dev_priv));
         if (err)
@@ -663,6 +686,21 @@ static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
                    _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
 }
 
+static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
+{
+        /* This is not an Wa. Enable for better image quality */
+        I915_WRITE(_3D_CHICKEN3,
+                   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
+
+        /* WaInPlaceDecompressionHang:icl */
+        I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+                                            GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+
+        /* WaPipelineFlushCoherentLines:icl */
+        I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
+                                   GEN8_LQSC_FLUSH_COHERENT_LINES);
+}
+
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 {
         if (INTEL_GEN(dev_priv) < 8)
@@ -683,6 +721,8 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
                 cfl_gt_workarounds_apply(dev_priv);
         else if (IS_CANNONLAKE(dev_priv))
                 cnl_gt_workarounds_apply(dev_priv);
+        else if (IS_ICELAKE(dev_priv))
+                icl_gt_workarounds_apply(dev_priv);
         else
                 MISSING_CASE(INTEL_GEN(dev_priv));
 }
@@ -761,6 +801,10 @@ static void cnl_whitelist_build(struct whitelist *w)
         whitelist_reg(w, GEN8_CS_CHICKEN1);
 }
 
+static void icl_whitelist_build(struct whitelist *w)
+{
+}
+
 static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
                                          struct whitelist *w)
 {
@@ -789,6 +833,8 @@ static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
                 cfl_whitelist_build(w);
         else if (IS_CANNONLAKE(i915))
                 cnl_whitelist_build(w);
+        else if (IS_ICELAKE(i915))
+                icl_whitelist_build(w);
         else
                 MISSING_CASE(INTEL_GEN(i915));