diff options
author | Oscar Mateo <oscar.mateo@intel.com> | 2018-05-08 17:29:23 -0400 |
---|---|---|
committer | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2018-05-11 08:53:20 -0400 |
commit | cc38cae7c4e9350c93aa2da506086415fecd6e4a (patch) | |
tree | f4463bcba92b8003574249bc4bb2c9df2ed34c7c | |
parent | ca6acc25250a1dc101c5a541b4f58bcc1dd65de5 (diff) |
drm/i915/icl: Introduce initial Icelake Workarounds
Inherit workarounds from previous platforms that are still valid for
Icelake.
v2: GEN7_ROW_CHICKEN2 is masked
v3:
- Since it has been fixed already in upstream, removed the TODO
comment about WA_SET_BIT for WaInPlaceDecompressionHang.
- Squashed with this patch:
drm/i915/icl: add icelake_init_clock_gating()
from Paulo Zanoni <paulo.r.zanoni@intel.com>
- Squashed with this patch:
drm/i915/icl: WaForceEnableNonCoherent
from Oscar Mateo <oscar.mateo@intel.com>
- WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
applies to B0 as well.
- WaPipeControlBefore3DStateSamplePattern WABB was being applied
to ICL incorrectly.
v4:
- Wrap the commit message
- s/dev_priv/p to please checkpatch
v5: Rebased on top of the WA refactoring
v6: Rebased on top of further whitelist registers refactoring (Michel)
v7: Added WaRsForcewakeAddDelayForAck
v8: s/ICL_HDC_CHICKEN0/ICL_HDC_MODE (Mika)
v9:
- C, not lisp (Chris)
- WaIncreaseDefaultTLBEntries is the same for GEN > 9_LP (Tvrtko)
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Tomasz Lis <tomasz.lis@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-2-git-send-email-oscar.mateo@intel.com
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 9 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem_gtt.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_lrc.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_uncore.c | 7 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_workarounds.c | 46 |
7 files changed, 69 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 24c5e4765afd..57fb3aa09db0 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
@@ -2470,6 +2470,15 @@ intel_info(const struct drm_i915_private *dev_priv) | |||
2470 | #define IS_CNL_REVID(p, since, until) \ | 2470 | #define IS_CNL_REVID(p, since, until) \ |
2471 | (IS_CANNONLAKE(p) && IS_REVID(p, since, until)) | 2471 | (IS_CANNONLAKE(p) && IS_REVID(p, since, until)) |
2472 | 2472 | ||
2473 | #define ICL_REVID_A0 0x0 | ||
2474 | #define ICL_REVID_A2 0x1 | ||
2475 | #define ICL_REVID_B0 0x3 | ||
2476 | #define ICL_REVID_B2 0x4 | ||
2477 | #define ICL_REVID_C0 0x5 | ||
2478 | |||
2479 | #define IS_ICL_REVID(p, since, until) \ | ||
2480 | (IS_ICELAKE(p) && IS_REVID(p, since, until)) | ||
2481 | |||
2473 | /* | 2482 | /* |
2474 | * The genX designation typically refers to the render engine, so render | 2483 | * The genX designation typically refers to the render engine, so render |
2475 | * capability related checks should use IS_GEN, while display and other checks | 2484 | * capability related checks should use IS_GEN, while display and other checks |
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 6eae9e1ed8be..c01d6dbe269a 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c | |||
@@ -2138,15 +2138,15 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv) | |||
2138 | * called on driver load and after a GPU reset, so you can place | 2138 | * called on driver load and after a GPU reset, so you can place |
2139 | * workarounds here even if they get overwritten by GPU reset. | 2139 | * workarounds here even if they get overwritten by GPU reset. |
2140 | */ | 2140 | */ |
2141 | /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */ | 2141 | /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */ |
2142 | if (IS_BROADWELL(dev_priv)) | 2142 | if (IS_BROADWELL(dev_priv)) |
2143 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); | 2143 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); |
2144 | else if (IS_CHERRYVIEW(dev_priv)) | 2144 | else if (IS_CHERRYVIEW(dev_priv)) |
2145 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); | 2145 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); |
2146 | else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv)) | ||
2147 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); | ||
2148 | else if (IS_GEN9_LP(dev_priv)) | 2146 | else if (IS_GEN9_LP(dev_priv)) |
2149 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); | 2147 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); |
2148 | else if (INTEL_GEN(dev_priv) >= 9) | ||
2149 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); | ||
2150 | 2150 | ||
2151 | /* | 2151 | /* |
2152 | * To support 64K PTEs we need to first enable the use of the | 2152 | * To support 64K PTEs we need to first enable the use of the |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 085928c9005e..2b22d4d3b0df 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -7238,6 +7238,7 @@ enum { | |||
7238 | /* GEN8 chicken */ | 7238 | /* GEN8 chicken */ |
7239 | #define HDC_CHICKEN0 _MMIO(0x7300) | 7239 | #define HDC_CHICKEN0 _MMIO(0x7300) |
7240 | #define CNL_HDC_CHICKEN0 _MMIO(0xE5F0) | 7240 | #define CNL_HDC_CHICKEN0 _MMIO(0xE5F0) |
7241 | #define ICL_HDC_MODE _MMIO(0xE5F4) | ||
7241 | #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15) | 7242 | #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15) |
7242 | #define HDC_FENCE_DEST_SLM_DISABLE (1<<14) | 7243 | #define HDC_FENCE_DEST_SLM_DISABLE (1<<14) |
7243 | #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) | 7244 | #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) |
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index d3c00f60c1b0..243d40369e6a 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c | |||
@@ -1682,6 +1682,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine) | |||
1682 | return -EINVAL; | 1682 | return -EINVAL; |
1683 | 1683 | ||
1684 | switch (INTEL_GEN(engine->i915)) { | 1684 | switch (INTEL_GEN(engine->i915)) { |
1685 | case 11: | ||
1686 | return 0; | ||
1685 | case 10: | 1687 | case 10: |
1686 | wa_bb_fn[0] = gen10_init_indirectctx_bb; | 1688 | wa_bb_fn[0] = gen10_init_indirectctx_bb; |
1687 | wa_bb_fn[1] = NULL; | 1689 | wa_bb_fn[1] = NULL; |
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 4126132eb707..9c6e48cc9514 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c | |||
@@ -9190,7 +9190,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv) | |||
9190 | */ | 9190 | */ |
9191 | void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) | 9191 | void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) |
9192 | { | 9192 | { |
9193 | if (IS_CANNONLAKE(dev_priv)) | 9193 | if (IS_ICELAKE(dev_priv)) |
9194 | dev_priv->display.init_clock_gating = nop_init_clock_gating; | ||
9195 | else if (IS_CANNONLAKE(dev_priv)) | ||
9194 | dev_priv->display.init_clock_gating = cnl_init_clock_gating; | 9196 | dev_priv->display.init_clock_gating = cnl_init_clock_gating; |
9195 | else if (IS_COFFEELAKE(dev_priv)) | 9197 | else if (IS_COFFEELAKE(dev_priv)) |
9196 | dev_priv->display.init_clock_gating = cfl_init_clock_gating; | 9198 | dev_priv->display.init_clock_gating = cfl_init_clock_gating; |
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index d6e20f0f4c28..448293eb638d 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c | |||
@@ -139,7 +139,9 @@ fw_domain_wait_ack_with_fallback(const struct drm_i915_private *i915, | |||
139 | * in the hope that the original ack will be delivered along with | 139 | * in the hope that the original ack will be delivered along with |
140 | * the fallback ack. | 140 | * the fallback ack. |
141 | * | 141 | * |
142 | * This workaround is described in HSDES #1604254524 | 142 | * This workaround is described in HSDES #1604254524 and it's known as: |
143 | * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl | ||
144 | * although the name is a bit misleading. | ||
143 | */ | 145 | */ |
144 | 146 | ||
145 | pass = 1; | 147 | pass = 1; |
@@ -1394,7 +1396,8 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) | |||
1394 | if (INTEL_GEN(dev_priv) >= 11) { | 1396 | if (INTEL_GEN(dev_priv) >= 11) { |
1395 | int i; | 1397 | int i; |
1396 | 1398 | ||
1397 | dev_priv->uncore.funcs.force_wake_get = fw_domains_get; | 1399 | dev_priv->uncore.funcs.force_wake_get = |
1400 | fw_domains_get_with_fallback; | ||
1398 | dev_priv->uncore.funcs.force_wake_put = fw_domains_put; | 1401 | dev_priv->uncore.funcs.force_wake_put = fw_domains_put; |
1399 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, | 1402 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1400 | FORCEWAKE_RENDER_GEN9, | 1403 | FORCEWAKE_RENDER_GEN9, |
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index ec9d340fcb00..73d02d3785d4 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c | |||
@@ -441,6 +441,27 @@ static int cnl_ctx_workarounds_init(struct drm_i915_private *dev_priv) | |||
441 | return 0; | 441 | return 0; |
442 | } | 442 | } |
443 | 443 | ||
444 | static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv) | ||
445 | { | ||
446 | /* Wa_1604370585:icl (pre-prod) | ||
447 | * Formerly known as WaPushConstantDereferenceHoldDisable | ||
448 | */ | ||
449 | if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0)) | ||
450 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, | ||
451 | PUSH_CONSTANT_DEREF_DISABLE); | ||
452 | |||
453 | /* WaForceEnableNonCoherent:icl | ||
454 | * This is not the same workaround as in early Gen9 platforms, where | ||
455 | * lacking this could cause system hangs, but coherency performance | ||
456 | * overhead is high and only a few compute workloads really need it | ||
457 | * (the register is whitelisted in hardware now, so UMDs can opt in | ||
458 | * for coherency if they have a good reason). | ||
459 | */ | ||
460 | WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); | ||
461 | |||
462 | return 0; | ||
463 | } | ||
464 | |||
444 | int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv) | 465 | int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv) |
445 | { | 466 | { |
446 | int err = 0; | 467 | int err = 0; |
@@ -465,6 +486,8 @@ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv) | |||
465 | err = cfl_ctx_workarounds_init(dev_priv); | 486 | err = cfl_ctx_workarounds_init(dev_priv); |
466 | else if (IS_CANNONLAKE(dev_priv)) | 487 | else if (IS_CANNONLAKE(dev_priv)) |
467 | err = cnl_ctx_workarounds_init(dev_priv); | 488 | err = cnl_ctx_workarounds_init(dev_priv); |
489 | else if (IS_ICELAKE(dev_priv)) | ||
490 | err = icl_ctx_workarounds_init(dev_priv); | ||
468 | else | 491 | else |
469 | MISSING_CASE(INTEL_GEN(dev_priv)); | 492 | MISSING_CASE(INTEL_GEN(dev_priv)); |
470 | if (err) | 493 | if (err) |
@@ -663,6 +686,21 @@ static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv) | |||
663 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); | 686 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); |
664 | } | 687 | } |
665 | 688 | ||
689 | static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv) | ||
690 | { | ||
691 | /* This is not an Wa. Enable for better image quality */ | ||
692 | I915_WRITE(_3D_CHICKEN3, | ||
693 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE)); | ||
694 | |||
695 | /* WaInPlaceDecompressionHang:icl */ | ||
696 | I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, I915_READ(GEN9_GAMT_ECO_REG_RW_IA) | | ||
697 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | ||
698 | |||
699 | /* WaPipelineFlushCoherentLines:icl */ | ||
700 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | ||
701 | GEN8_LQSC_FLUSH_COHERENT_LINES); | ||
702 | } | ||
703 | |||
666 | void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv) | 704 | void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv) |
667 | { | 705 | { |
668 | if (INTEL_GEN(dev_priv) < 8) | 706 | if (INTEL_GEN(dev_priv) < 8) |
@@ -683,6 +721,8 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv) | |||
683 | cfl_gt_workarounds_apply(dev_priv); | 721 | cfl_gt_workarounds_apply(dev_priv); |
684 | else if (IS_CANNONLAKE(dev_priv)) | 722 | else if (IS_CANNONLAKE(dev_priv)) |
685 | cnl_gt_workarounds_apply(dev_priv); | 723 | cnl_gt_workarounds_apply(dev_priv); |
724 | else if (IS_ICELAKE(dev_priv)) | ||
725 | icl_gt_workarounds_apply(dev_priv); | ||
686 | else | 726 | else |
687 | MISSING_CASE(INTEL_GEN(dev_priv)); | 727 | MISSING_CASE(INTEL_GEN(dev_priv)); |
688 | } | 728 | } |
@@ -761,6 +801,10 @@ static void cnl_whitelist_build(struct whitelist *w) | |||
761 | whitelist_reg(w, GEN8_CS_CHICKEN1); | 801 | whitelist_reg(w, GEN8_CS_CHICKEN1); |
762 | } | 802 | } |
763 | 803 | ||
804 | static void icl_whitelist_build(struct whitelist *w) | ||
805 | { | ||
806 | } | ||
807 | |||
764 | static struct whitelist *whitelist_build(struct intel_engine_cs *engine, | 808 | static struct whitelist *whitelist_build(struct intel_engine_cs *engine, |
765 | struct whitelist *w) | 809 | struct whitelist *w) |
766 | { | 810 | { |
@@ -789,6 +833,8 @@ static struct whitelist *whitelist_build(struct intel_engine_cs *engine, | |||
789 | cfl_whitelist_build(w); | 833 | cfl_whitelist_build(w); |
790 | else if (IS_CANNONLAKE(i915)) | 834 | else if (IS_CANNONLAKE(i915)) |
791 | cnl_whitelist_build(w); | 835 | cnl_whitelist_build(w); |
836 | else if (IS_ICELAKE(i915)) | ||
837 | icl_whitelist_build(w); | ||
792 | else | 838 | else |
793 | MISSING_CASE(INTEL_GEN(i915)); | 839 | MISSING_CASE(INTEL_GEN(i915)); |
794 | 840 | ||