diff options
author | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2016-07-20 07:26:12 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2016-07-25 02:28:50 -0400 |
commit | f15f6ca1e706e11fd07611bd4c7f903625349b33 (patch) | |
tree | 22e3270af2ed5ea088f8531262db3abefd7bacd7 /drivers/gpu/drm/i915/intel_ringbuffer.c | |
parent | c5f87f02f4e8a6fd83d34bd47e1c87f55e6d4afa (diff) |
drm/i915/gen9: Add WaInPlaceDecompressionHang
Add this workaround to prevent hang when in place compression
is used.
References: HSD#2135774
Cc: stable@vger.kernel.org
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
(cherry picked from commit 4ba9c1f7c7b8ca8c1d77f65d408e589dc87b9a2d)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index c8e77c082b21..cca7792f26d5 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c | |||
@@ -1109,6 +1109,11 @@ static int skl_init_workarounds(struct intel_engine_cs *engine) | |||
1109 | /* WaDisableGafsUnitClkGating:skl */ | 1109 | /* WaDisableGafsUnitClkGating:skl */ |
1110 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | 1110 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); |
1111 | 1111 | ||
1112 | /* WaInPlaceDecompressionHang:skl */ | ||
1113 | if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER)) | ||
1114 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | ||
1115 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | ||
1116 | |||
1112 | /* WaDisableLSQCROPERFforOCL:skl */ | 1117 | /* WaDisableLSQCROPERFforOCL:skl */ |
1113 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | 1118 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
1114 | if (ret) | 1119 | if (ret) |
@@ -1178,6 +1183,11 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine) | |||
1178 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | 1183 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, |
1179 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | 1184 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); |
1180 | 1185 | ||
1186 | /* WaInPlaceDecompressionHang:bxt */ | ||
1187 | if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) | ||
1188 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | ||
1189 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | ||
1190 | |||
1181 | return 0; | 1191 | return 0; |
1182 | } | 1192 | } |
1183 | 1193 | ||
@@ -1225,6 +1235,10 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine) | |||
1225 | GEN7_HALF_SLICE_CHICKEN1, | 1235 | GEN7_HALF_SLICE_CHICKEN1, |
1226 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | 1236 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); |
1227 | 1237 | ||
1238 | /* WaInPlaceDecompressionHang:kbl */ | ||
1239 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | ||
1240 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | ||
1241 | |||
1228 | /* WaDisableLSQCROPERFforOCL:kbl */ | 1242 | /* WaDisableLSQCROPERFforOCL:kbl */ |
1229 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | 1243 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
1230 | if (ret) | 1244 | if (ret) |