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-rw-r--r--drivers/gpu/drm/i915/i915_drv.h2
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h3
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c14
3 files changed, 19 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7c315475ae1b..915a3d0acff3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2746,6 +2746,8 @@ struct drm_i915_cmd_table {
2746#define SKL_REVID_D0 0x3 2746#define SKL_REVID_D0 0x3
2747#define SKL_REVID_E0 0x4 2747#define SKL_REVID_E0 0x4
2748#define SKL_REVID_F0 0x5 2748#define SKL_REVID_F0 0x5
2749#define SKL_REVID_G0 0x6
2750#define SKL_REVID_H0 0x7
2749 2751
2750#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) 2752#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2751 2753
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8bfde75789f6..ce14fe09d962 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1686,6 +1686,9 @@ enum skl_disp_power_wells {
1686 1686
1687#define GEN7_TLB_RD_ADDR _MMIO(0x4700) 1687#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
1688 1688
1689#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
1690#define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1<<18)
1691
1689#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8) 1692#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
1690#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28) 1693#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
1691 1694
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c8e77c082b21..cca7792f26d5 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1109,6 +1109,11 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
1109 /* WaDisableGafsUnitClkGating:skl */ 1109 /* WaDisableGafsUnitClkGating:skl */
1110 WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1110 WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1111 1111
1112 /* WaInPlaceDecompressionHang:skl */
1113 if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
1114 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
1115 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1116
1112 /* WaDisableLSQCROPERFforOCL:skl */ 1117 /* WaDisableLSQCROPERFforOCL:skl */
1113 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); 1118 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1114 if (ret) 1119 if (ret)
@@ -1178,6 +1183,11 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
1178 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 1183 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1179 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 1184 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1180 1185
1186 /* WaInPlaceDecompressionHang:bxt */
1187 if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
1188 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
1189 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1190
1181 return 0; 1191 return 0;
1182} 1192}
1183 1193
@@ -1225,6 +1235,10 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
1225 GEN7_HALF_SLICE_CHICKEN1, 1235 GEN7_HALF_SLICE_CHICKEN1,
1226 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 1236 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1227 1237
1238 /* WaInPlaceDecompressionHang:kbl */
1239 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
1240 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1241
1228 /* WaDisableLSQCROPERFforOCL:kbl */ 1242 /* WaDisableLSQCROPERFforOCL:kbl */
1229 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); 1243 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1230 if (ret) 1244 if (ret)