drm/i915: Remove HW semaphores for gen7 inter-engine synchronisation

The writing is on the wall for the existence of a single execution queue
along each engine, and as a consequence we will not be able to track
dependencies along the HW queue itself, i.e. we will not be able to use
HW semaphores on gen7 as they use a global set of registers (and unlike
gen8+ we can not effectively target memory to keep per-context seqno and
dependencies).

On the positive side, when we implement request reordering for gen7 we
also can not presume a simple execution queue and would also require
removing the current semaphore generation code. So this bring us another
step closer to request reordering for ringbuffer submission!

The negative side is that using interrupts to drive inter-engine
synchronisation is much slower (4us -> 15us to do a nop on each of the 3
engines on ivb). This is much better than it was at the time of introducing
the HW semaphores and equally important userspace weaned itself off
intermixing dependent BLT/RENDER operations (the prime culprit was glyph
rendering in UXA). So while we regress the microbenchmarks, it should not
impact the user.

References: https://bugs.freedesktop.org/show_bug.cgi?id=108888
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181228140736.32606-2-chris@chris-wilson.co.uk

1 files changed, 0 insertions, 138 deletions

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1102c2e98222..588294a3bbd2 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -556,13 +556,6 @@ static int init_ring_common(struct intel_engine_cs *engine)
 
         intel_engine_reset_breadcrumbs(engine);
 
-        if (HAS_LEGACY_SEMAPHORES(engine->i915)) {
-                I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
-                I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
-                if (HAS_VEBOX(dev_priv))
-                        I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
-        }
-
         /* Enforce ordering by reading HEAD register back */
         I915_READ_HEAD(engine);
 
@@ -745,33 +738,6 @@ static int init_render_ring(struct intel_engine_cs *engine)
         return 0;
 }
 
-static u32 *gen6_signal(struct i915_request *rq, u32 *cs)
-{
-        struct drm_i915_private *dev_priv = rq->i915;
-        struct intel_engine_cs *engine;
-        enum intel_engine_id id;
-        int num_rings = 0;
-
-        for_each_engine(engine, dev_priv, id) {
-                i915_reg_t mbox_reg;
-
-                if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK))
-                        continue;
-
-                mbox_reg = rq->engine->semaphore.mbox.signal[engine->hw_id];
-                if (i915_mmio_reg_valid(mbox_reg)) {
-                        *cs++ = MI_LOAD_REGISTER_IMM(1);
-                        *cs++ = i915_mmio_reg_offset(mbox_reg);
-                        *cs++ = rq->global_seqno;
-                        num_rings++;
-                }
-        }
-        if (num_rings & 1)
-                *cs++ = MI_NOOP;
-
-        return cs;
-}
-
 static void cancel_requests(struct intel_engine_cs *engine)
 {
         struct i915_request *request;
@@ -822,39 +788,6 @@ static void i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs)
 
 static const int i9xx_emit_breadcrumb_sz = 4;
 
-static void gen6_sema_emit_breadcrumb(struct i915_request *rq, u32 *cs)
-{
-        return i9xx_emit_breadcrumb(rq, rq->engine->semaphore.signal(rq, cs));
-}
-
-static int
-gen6_ring_sync_to(struct i915_request *rq, struct i915_request *signal)
-{
-        u32 dw1 = MI_SEMAPHORE_MBOX |
-                  MI_SEMAPHORE_COMPARE |
-                  MI_SEMAPHORE_REGISTER;
-        u32 wait_mbox = signal->engine->semaphore.mbox.wait[rq->engine->hw_id];
-        u32 *cs;
-
-        WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
-
-        cs = intel_ring_begin(rq, 4);
-        if (IS_ERR(cs))
-                return PTR_ERR(cs);
-
-        *cs++ = dw1 | wait_mbox;
-        /* Throughout all of the GEM code, seqno passed implies our current
-         * seqno is >= the last seqno executed. However for hardware the
-         * comparison is strictly greater than.
-         */
-        *cs++ = signal->global_seqno - 1;
-        *cs++ = 0;
-        *cs++ = MI_NOOP;
-        intel_ring_advance(rq, cs);
-
-        return 0;
-}
-
 static void
 gen5_seqno_barrier(struct intel_engine_cs *engine)
 {
@@ -2151,66 +2084,6 @@ static int gen6_ring_flush(struct i915_request *rq, u32 mode)
         return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB);
 }
 
-static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
-                                       struct intel_engine_cs *engine)
-{
-        int i;
-
-        if (!HAS_LEGACY_SEMAPHORES(dev_priv))
-                return;
-
-        GEM_BUG_ON(INTEL_GEN(dev_priv) < 6);
-        engine->semaphore.sync_to = gen6_ring_sync_to;
-        engine->semaphore.signal = gen6_signal;
-
-        /*
-         * The current semaphore is only applied on pre-gen8
-         * platform.  And there is no VCS2 ring on the pre-gen8
-         * platform. So the semaphore between RCS and VCS2 is
-         * initialized as INVALID.
-         */
-        for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) {
-                static const struct {
-                        u32 wait_mbox;
-                        i915_reg_t mbox_reg;
-                } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = {
-                        [RCS_HW] = {
-                                [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RV,  .mbox_reg = GEN6_VRSYNC },
-                                [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RB,  .mbox_reg = GEN6_BRSYNC },
-                                [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC },
-                        },
-                        [VCS_HW] = {
-                                [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VR,  .mbox_reg = GEN6_RVSYNC },
-                                [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VB,  .mbox_reg = GEN6_BVSYNC },
-                                [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC },
-                        },
-                        [BCS_HW] = {
-                                [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BR,  .mbox_reg = GEN6_RBSYNC },
-                                [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BV,  .mbox_reg = GEN6_VBSYNC },
-                                [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC },
-                        },
-                        [VECS_HW] = {
-                                [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC },
-                                [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC },
-                                [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC },
-                        },
-                };
-                u32 wait_mbox;
-                i915_reg_t mbox_reg;
-
-                if (i == engine->hw_id) {
-                        wait_mbox = MI_SEMAPHORE_SYNC_INVALID;
-                        mbox_reg = GEN6_NOSYNC;
-                } else {
-                        wait_mbox = sem_data[engine->hw_id][i].wait_mbox;
-                        mbox_reg = sem_data[engine->hw_id][i].mbox_reg;
-                }
-
-                engine->semaphore.mbox.wait[i] = wait_mbox;
-                engine->semaphore.mbox.signal[i] = mbox_reg;
-        }
-}
-
 static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
                                 struct intel_engine_cs *engine)
 {
@@ -2253,7 +2126,6 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
         GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8);
 
         intel_ring_init_irq(dev_priv, engine);
-        intel_ring_init_semaphores(dev_priv, engine);
 
         engine->init_hw = init_ring_common;
         engine->reset.prepare = reset_prepare;
@@ -2265,16 +2137,6 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
 
         engine->emit_breadcrumb = i9xx_emit_breadcrumb;
         engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz;
-        if (HAS_LEGACY_SEMAPHORES(dev_priv)) {
-                int num_rings;
-
-                engine->emit_breadcrumb = gen6_sema_emit_breadcrumb;
-
-                num_rings = INTEL_INFO(dev_priv)->num_rings - 1;
-                engine->emit_breadcrumb_sz += num_rings * 3;
-                if (num_rings & 1)
-                        engine->emit_breadcrumb_sz++;
-        }
 
         engine->set_default_submission = i9xx_set_default_submission;