Merge tag 'drm-intel-fixes-2014-06-06' of git://anongit.freedesktop.org/drm-intel into drm-next

> Bunch of stuff for 3.16 still:
> - Mipi dsi panel support for byt. Finally! From Shobhit&others. I've
>   squeezed this in since it's a regression compared to vbios and we've
>   been ridiculed about it a bit too often ...
> - connection_mutex deadlock fix in get_connector (only affects i915).
> - Core patches from Matt's primary plane from Matt Roper, I've pushed the
>   i915 stuff to 3.17.
> - vlv power well sequencing fixes from Jesse.
> - Fix for cursor size changes from Chris.
> - agpbusy fixes from Ville.
> - A few smaller things.
>

* tag 'drm-intel-fixes-2014-06-06' of git://anongit.freedesktop.org/drm-intel: (32 commits)
  drm/i915: BDW: Adding missing cursor offsets.
  drm: Fix getconnector connection_mutex locking
  drm/i915/bdw: Only use 2g GGTT for 32b platforms
  drm/i915: Nuke pipe A quirk on i830M
  drm/i915: fix display power sw state reporting
  drm/i915: Always apply cursor width changes
  drm/i915: tell the user if both KMS and UMS are disabled
  drm/plane-helper: Add drm_plane_helper_check_update() (v3)
  drm: Check CRTC compatibility in setplane
  drm/i915: use VBT to determine whether to enumerate the VGA port
  drm/i915: Don't WARN about ring idle bit on gen2
  drm/i915: Silence the WARN if the user tries to GTT mmap an incoherent object
  drm/i915: Move the C3 LP write bit setup to gen3_init_clock_gating() for KMS
  drm/i915: Enable interrupt-based AGPBUSY# enable on 85x
  drm/i915: Flip the sense of AGPBUSY_DIS bit
  drm/i915: Set AGPBUSY# bit in init_clock_gating
  drm/i915/vlv: add pll assertion when disabling DPIO common well
  drm/i915/vlv: move DPIO common reset de-assert into __vlv_set_power_well
  drm/i915/vlv: re-order power wells so DPIO common comes after TX
  drm/i915/vlv: move CRI refclk enable into __vlv_set_power_well
  ...

1 files changed, 83 insertions, 12 deletions

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 906d06f73e51..d1e53abec1b5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5388,8 +5388,11 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
         I915_WRITE(GEN6_UCGCTL2,
                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
 
-        /* WaDisableL3Bank2xClockGate:vlv */
-        I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
+        /* WaDisableL3Bank2xClockGate:vlv
+         * Disabling L3 clock gating- MMIO 940c[25] = 1
+         * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
+        I915_WRITE(GEN7_UCGCTL4,
+                   I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
 
         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
 
@@ -5541,6 +5544,12 @@ static void gen3_init_clock_gating(struct drm_device *dev)
 
         /* IIR "flip pending" means done if this bit is set */
         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
+
+        /* interrupts should cause a wake up from C3 */
+        I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
+
+        /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
+        I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
 }
 
 static void i85x_init_clock_gating(struct drm_device *dev)
@@ -5548,6 +5557,10 @@ static void i85x_init_clock_gating(struct drm_device *dev)
         struct drm_i915_private *dev_priv = dev->dev_private;
 
         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
+
+        /* interrupts should cause a wake up from C3 */
+        I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
+                   _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
 }
 
 static void i830_init_clock_gating(struct drm_device *dev)
@@ -5599,10 +5612,25 @@ bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
                                     enum intel_display_power_domain domain)
 {
         struct i915_power_domains *power_domains;
+        struct i915_power_well *power_well;
+        bool is_enabled;
+        int i;
+
+        if (dev_priv->pm.suspended)
+                return false;
 
         power_domains = &dev_priv->power_domains;
+        is_enabled = true;
+        for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
+                if (power_well->always_on)
+                        continue;
 
-        return power_domains->domain_use_count[domain];
+                if (!power_well->count) {
+                        is_enabled = false;
+                        break;
+                }
+        }
+        return is_enabled;
 }
 
 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
@@ -5745,13 +5773,34 @@ static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
         return true;
 }
 
-static void vlv_set_power_well(struct drm_i915_private *dev_priv,
-                               struct i915_power_well *power_well, bool enable)
+void __vlv_set_power_well(struct drm_i915_private *dev_priv,
+                          enum punit_power_well power_well_id, bool enable)
 {
-        enum punit_power_well power_well_id = power_well->data;
+        struct drm_device *dev = dev_priv->dev;
         u32 mask;
         u32 state;
         u32 ctrl;
+        enum pipe pipe;
+
+        if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
+                if (enable) {
+                        /*
+                         * Enable the CRI clock source so we can get at the
+                         * display and the reference clock for VGA
+                         * hotplug / manual detection.
+                         */
+                        I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
+                                   DPLL_REFA_CLK_ENABLE_VLV |
+                                   DPLL_INTEGRATED_CRI_CLK_VLV);
+                        udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
+                } else {
+                        for_each_pipe(pipe)
+                                assert_pll_disabled(dev_priv, pipe);
+                        /* Assert common reset */
+                        I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) &
+                                   ~DPIO_CMNRST);
+                }
+        }
 
         mask = PUNIT_PWRGT_MASK(power_well_id);
         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
@@ -5779,6 +5828,28 @@ static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 
 out:
         mutex_unlock(&dev_priv->rps.hw_lock);
+
+        /*
+         * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
+         *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
+         *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
+         *   b. The other bits such as sfr settings / modesel may all
+         *      be set to 0.
+         *
+         * This should only be done on init and resume from S3 with
+         * both PLLs disabled, or we risk losing DPIO and PLL
+         * synchronization.
+         */
+        if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC && enable)
+                I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
+}
+
+static void vlv_set_power_well(struct drm_i915_private *dev_priv,
+                               struct i915_power_well *power_well, bool enable)
+{
+        enum punit_power_well power_well_id = power_well->data;
+
+        __vlv_set_power_well(dev_priv, power_well_id, enable);
 }
 
 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
@@ -6114,12 +6185,6 @@ static struct i915_power_well vlv_power_wells[] = {
                 .ops = &vlv_display_power_well_ops,
         },
         {
-                .name = "dpio-common",
-                .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
-                .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
-                .ops = &vlv_dpio_power_well_ops,
-        },
-        {
                 .name = "dpio-tx-b-01",
                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
@@ -6155,6 +6220,12 @@ static struct i915_power_well vlv_power_wells[] = {
                 .ops = &vlv_dpio_power_well_ops,
                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
         },
+        {
+                .name = "dpio-common",
+                .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
+                .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
+                .ops = &vlv_dpio_power_well_ops,
+        },
 };
 
 #define set_power_wells(power_domains, __power_wells) ({                \