Merge tag 'drm-intel-next-2018-07-09' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

Higlights here goes to many PSR fixes and improvements; to the Ice lake work with
power well support and begin of DSI support addition. Also there were many improvements
on execlists and interrupts for minimal latency on command submission; and many fixes
on selftests, mostly caught by our CI.

General driver:
- Clean-up on aux irq (Lucas)
- Mark expected switch fall-through for dealing with static analysis tools (Gustavo)

Gem:
- Different fixes for GuC (Chris, Anusha, Michal)
- Avoid self-relocation BIAS if no relocation (Chris)
- Improve debugging cases in on EINVAL return and vma allocation (Chris)
- Fixes and improvements on context destroying and freeing (Chris)
- Wait for engines to idle before retiring (Chris)
- Many improvements on execlists and interrupts for minimal latency on command submission (Chris)
- Many fixes in selftests, specially on cases highlighted on CI (Chris)
- Other fixes and improvements around GGTT (Chris)
- Prevent background reaping of active objects (Chris)

Display:
- Parallel modeset cleanup to fix driver reset (Chris)
- Get AUX power domain for DP main link (Imre)
- Clean-up on PSR unused func pointers (Rodrigo)
- Many PSR/PSR2 fixes and improvements (DK, Jose, Tarun)
- Add a PSR1 live status (Vathsala)
- Replace old drm_*_{un/reference} with put,get functions (Thomas)
- FBC fixes (Maarten)
- Abstract and document the usage of picking macros (Jani)
- Remove unnecessary check for unsupported modifiers for NV12. (DK)
- Interrupt fixes for display (Ville)
- Clean up on sdvo code (Ville)
- Clean up on current DSI code (Jani)
- Remove support for legacy debugfs crc interface (Maarten)
- Simplify get_encoder_power_domains (Imre)

Icelake:
- MG PLL fixes (Imre)
- Add hw workaround for alpha blending (Vandita)
- Add power well support (Imre)
- Add Interrupt Support (Anusha)
- Start to add support for DSI on Ice Lake (Madhav)

Signed-off-by: Dave Airlie <airlied@redhat.com>

# gpg: Signature made Tue 10 Jul 2018 08:41:37 AM AEST
# gpg:                using RSA key FA625F640EEB13CA
# gpg: Good signature from "Rodrigo Vivi <rodrigo.vivi@intel.com>"
# gpg:                 aka "Rodrigo Vivi <rodrigo.vivi@gmail.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6D20 7068 EEDD 6509 1C2C  E2A3 FA62 5F64 0EEB 13CA
Link: https://patchwork.freedesktop.org/patch/msgid/20180710234349.GA16562@intel.com

1 files changed, 12 insertions, 22 deletions

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 32bf3a408d46..0ac497275a51 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -25,7 +25,6 @@
 #include <drm/drm_print.h>
 
 #include "i915_drv.h"
-#include "i915_vgpu.h"
 #include "intel_ringbuffer.h"
 #include "intel_lrc.h"
 
@@ -230,6 +229,7 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
                 break;
         default:
                 MISSING_CASE(class);
+                /* fall through */
         case VIDEO_DECODE_CLASS:
         case VIDEO_ENHANCEMENT_CLASS:
         case COPY_ENGINE_CLASS:
@@ -302,6 +302,8 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
                                                            engine->class);
         if (WARN_ON(engine->context_size > BIT(20)))
                 engine->context_size = 0;
+        if (engine->context_size)
+                DRIVER_CAPS(dev_priv)->has_logical_contexts = true;
 
         /* Nothing to do here, execute in order of dependencies */
         engine->schedule = NULL;
@@ -456,21 +458,10 @@ static void intel_engine_init_batch_pool(struct intel_engine_cs *engine)
         i915_gem_batch_pool_init(&engine->batch_pool, engine);
 }
 
-static bool csb_force_mmio(struct drm_i915_private *i915)
-{
-        /* Older GVT emulation depends upon intercepting CSB mmio */
-        if (intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915))
-                return true;
-
-        return false;
-}
-
 static void intel_engine_init_execlist(struct intel_engine_cs *engine)
 {
         struct intel_engine_execlists * const execlists = &engine->execlists;
 
-        execlists->csb_use_mmio = csb_force_mmio(engine->i915);
-
         execlists->port_mask = 1;
         BUILD_BUG_ON_NOT_POWER_OF_2(execlists_num_ports(execlists));
         GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
@@ -492,6 +483,7 @@ static void intel_engine_init_execlist(struct intel_engine_cs *engine)
 void intel_engine_setup_common(struct intel_engine_cs *engine)
 {
         i915_timeline_init(engine->i915, &engine->timeline, engine->name);
+        lockdep_set_subclass(&engine->timeline.lock, TIMELINE_ENGINE);
 
         intel_engine_init_execlist(engine);
         intel_engine_init_hangcheck(engine);
@@ -1000,10 +992,12 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine)
         if (READ_ONCE(engine->execlists.active)) {
                 struct intel_engine_execlists *execlists = &engine->execlists;
 
+                local_bh_disable();
                 if (tasklet_trylock(&execlists->tasklet)) {
                         execlists->tasklet.func(execlists->tasklet.data);
                         tasklet_unlock(&execlists->tasklet);
                 }
+                local_bh_enable();
 
                 if (READ_ONCE(execlists->active))
                         return false;
@@ -1363,12 +1357,10 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
                 ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
                 read = GEN8_CSB_READ_PTR(ptr);
                 write = GEN8_CSB_WRITE_PTR(ptr);
-                drm_printf(m, "\tExeclist CSB read %d [%d cached], write %d [%d from hws], interrupt posted? %s, tasklet queued? %s (%s)\n",
+                drm_printf(m, "\tExeclist CSB read %d [%d cached], write %d [%d from hws], tasklet queued? %s (%s)\n",
                            read, execlists->csb_head,
                            write,
                            intel_read_status_page(engine, intel_hws_csb_write_index(engine->i915)),
-                           yesno(test_bit(ENGINE_IRQ_EXECLIST,
-                                          &engine->irq_posted)),
                            yesno(test_bit(TASKLET_STATE_SCHED,
                                           &engine->execlists.tasklet.state)),
                            enableddisabled(!atomic_read(&engine->execlists.tasklet.count)));
@@ -1580,11 +1572,9 @@ void intel_engine_dump(struct intel_engine_cs *engine,
         spin_unlock(&b->rb_lock);
         local_irq_restore(flags);
 
-        drm_printf(m, "IRQ? 0x%lx (breadcrumbs? %s) (execlists? %s)\n",
+        drm_printf(m, "IRQ? 0x%lx (breadcrumbs? %s)\n",
                    engine->irq_posted,
                    yesno(test_bit(ENGINE_IRQ_BREADCRUMB,
-                                  &engine->irq_posted)),
-                   yesno(test_bit(ENGINE_IRQ_EXECLIST,
                                   &engine->irq_posted)));
 
         drm_printf(m, "HWSP:\n");
@@ -1633,8 +1623,8 @@ int intel_enable_engine_stats(struct intel_engine_cs *engine)
         if (!intel_engine_supports_stats(engine))
                 return -ENODEV;
 
-        tasklet_disable(&execlists->tasklet);
-        write_seqlock_irqsave(&engine->stats.lock, flags);
+        spin_lock_irqsave(&engine->timeline.lock, flags);
+        write_seqlock(&engine->stats.lock);
 
         if (unlikely(engine->stats.enabled == ~0)) {
                 err = -EBUSY;
@@ -1658,8 +1648,8 @@ int intel_enable_engine_stats(struct intel_engine_cs *engine)
         }
 
 unlock:
-        write_sequnlock_irqrestore(&engine->stats.lock, flags);
-        tasklet_enable(&execlists->tasklet);
+        write_sequnlock(&engine->stats.lock);
+        spin_unlock_irqrestore(&engine->timeline.lock, flags);
 
         return err;
 }