Merge tag 'v4.2-rc7' into drm-next

Linux 4.2-rc7

Backmerge master for i915 fixes

15 files changed, 296 insertions, 97 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f3791e0d27d4..baefa635169a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1130,6 +1130,9 @@ struct amdgpu_gfx {
         uint32_t                        me_feature_version;
         uint32_t                        ce_feature_version;
         uint32_t                        pfp_feature_version;
+        uint32_t                        rlc_feature_version;
+        uint32_t                        mec_feature_version;
+        uint32_t                        mec2_feature_version;
         struct amdgpu_ring              gfx_ring[AMDGPU_MAX_GFX_RINGS];
         unsigned                        num_gfx_rings;
         struct amdgpu_ring              compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
@@ -1614,6 +1617,9 @@ struct amdgpu_uvd {
 #define AMDGPU_MAX_VCE_HANDLES  16
 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
 
+#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
+#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
+
 struct amdgpu_vce {
         struct amdgpu_bo        *vcpu_bo;
         uint64_t                gpu_addr;
@@ -1626,6 +1632,7 @@ struct amdgpu_vce {
         const struct firmware   *fw;    /* VCE firmware */
         struct amdgpu_ring      ring[AMDGPU_MAX_VCE_RINGS];
         struct amdgpu_irq_src   irq;
+        unsigned                harvest_config;
 };
 
 /*
@@ -1635,6 +1642,7 @@ struct amdgpu_sdma {
         /* SDMA firmware */
         const struct firmware   *fw;
         uint32_t                fw_version;
+        uint32_t                feature_version;
 
         struct amdgpu_ring      ring;
 };
@@ -1862,6 +1870,12 @@ typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
 
+struct amdgpu_ip_block_status {
+        bool valid;
+        bool sw;
+        bool hw;
+};
+
 struct amdgpu_device {
         struct device                   *dev;
         struct drm_device               *ddev;
@@ -2004,7 +2018,7 @@ struct amdgpu_device {
 
         const struct amdgpu_ip_block_version *ip_blocks;
         int                             num_ip_blocks;
-        bool                            *ip_block_enabled;
+        struct amdgpu_ip_block_status   *ip_block_status;
         struct mutex    mn_lock;
         DECLARE_HASHTABLE(mn_hash, 7);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index d79009b65867..99f158e1baff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1191,8 +1191,9 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
                 return -EINVAL;
         }
 
-        adev->ip_block_enabled = kcalloc(adev->num_ip_blocks, sizeof(bool), GFP_KERNEL);
-        if (adev->ip_block_enabled == NULL)
+        adev->ip_block_status = kcalloc(adev->num_ip_blocks,
+                                        sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
+        if (adev->ip_block_status == NULL)
                 return -ENOMEM;
 
         if (adev->ip_blocks == NULL) {
@@ -1203,18 +1204,18 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
         for (i = 0; i < adev->num_ip_blocks; i++) {
                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
                         DRM_ERROR("disabled ip block: %d\n", i);
-                        adev->ip_block_enabled[i] = false;
+                        adev->ip_block_status[i].valid = false;
                 } else {
                         if (adev->ip_blocks[i].funcs->early_init) {
                                 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
                                 if (r == -ENOENT)
-                                        adev->ip_block_enabled[i] = false;
+                                        adev->ip_block_status[i].valid = false;
                                 else if (r)
                                         return r;
                                 else
-                                        adev->ip_block_enabled[i] = true;
+                                        adev->ip_block_status[i].valid = true;
                         } else {
-                                adev->ip_block_enabled[i] = true;
+                                adev->ip_block_status[i].valid = true;
                         }
                 }
         }
@@ -1227,11 +1228,12 @@ static int amdgpu_init(struct amdgpu_device *adev)
         int i, r;
 
         for (i = 0; i < adev->num_ip_blocks; i++) {
-                if (!adev->ip_block_enabled[i])
+                if (!adev->ip_block_status[i].valid)
                         continue;
                 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
                 if (r)
                         return r;
+                adev->ip_block_status[i].sw = true;
                 /* need to do gmc hw init early so we can allocate gpu mem */
                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
                         r = amdgpu_vram_scratch_init(adev);
@@ -1243,11 +1245,12 @@ static int amdgpu_init(struct amdgpu_device *adev)
                         r = amdgpu_wb_init(adev);
                         if (r)
                                 return r;
+                        adev->ip_block_status[i].hw = true;
                 }
         }
 
         for (i = 0; i < adev->num_ip_blocks; i++) {
-                if (!adev->ip_block_enabled[i])
+                if (!adev->ip_block_status[i].sw)
                         continue;
                 /* gmc hw init is done early */
                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
@@ -1255,6 +1258,7 @@ static int amdgpu_init(struct amdgpu_device *adev)
                 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
                 if (r)
                         return r;
+                adev->ip_block_status[i].hw = true;
         }
 
         return 0;
@@ -1265,7 +1269,7 @@ static int amdgpu_late_init(struct amdgpu_device *adev)
         int i = 0, r;
 
         for (i = 0; i < adev->num_ip_blocks; i++) {
-                if (!adev->ip_block_enabled[i])
+                if (!adev->ip_block_status[i].valid)
                         continue;
                 /* enable clockgating to save power */
                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
@@ -1287,7 +1291,7 @@ static int amdgpu_fini(struct amdgpu_device *adev)
         int i, r;
 
         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
-                if (!adev->ip_block_enabled[i])
+                if (!adev->ip_block_status[i].hw)
                         continue;
                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
                         amdgpu_wb_fini(adev);
@@ -1300,14 +1304,16 @@ static int amdgpu_fini(struct amdgpu_device *adev)
                         return r;
                 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
                 /* XXX handle errors */
+                adev->ip_block_status[i].hw = false;
         }
 
         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
-                if (!adev->ip_block_enabled[i])
+                if (!adev->ip_block_status[i].sw)
                         continue;
                 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
                 /* XXX handle errors */
-                adev->ip_block_enabled[i] = false;
+                adev->ip_block_status[i].sw = false;
+                adev->ip_block_status[i].valid = false;
         }
 
         return 0;
@@ -1318,7 +1324,7 @@ static int amdgpu_suspend(struct amdgpu_device *adev)
         int i, r;
 
         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
-                if (!adev->ip_block_enabled[i])
+                if (!adev->ip_block_status[i].valid)
                         continue;
                 /* ungate blocks so that suspend can properly shut them down */
                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
@@ -1336,7 +1342,7 @@ static int amdgpu_resume(struct amdgpu_device *adev)
         int i, r;
 
         for (i = 0; i < adev->num_ip_blocks; i++) {
-                if (!adev->ip_block_enabled[i])
+                if (!adev->ip_block_status[i].valid)
                         continue;
                 r = adev->ip_blocks[i].funcs->resume(adev);
                 if (r)
@@ -1582,8 +1588,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
         amdgpu_fence_driver_fini(adev);
         amdgpu_fbdev_fini(adev);
         r = amdgpu_fini(adev);
-        kfree(adev->ip_block_enabled);
-        adev->ip_block_enabled = NULL;
+        kfree(adev->ip_block_status);
+        adev->ip_block_status = NULL;
         adev->accel_working = false;
         /* free i2c buses */
         amdgpu_i2c_fini(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index ae43b58c9733..4afc507820c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -449,7 +449,7 @@ out:
  * vital here, so they are not reported back to userspace.
  */
 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
-                                    struct amdgpu_bo_va *bo_va)
+                                    struct amdgpu_bo_va *bo_va, uint32_t operation)
 {
         struct ttm_validate_buffer tv, *entry;
         struct amdgpu_bo_list_entry *vm_bos;
@@ -485,7 +485,9 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
         if (r)
                 goto error_unlock;
 
-        r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem);
+
+        if (operation == AMDGPU_VA_OP_MAP)
+                r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem);
 
 error_unlock:
         mutex_unlock(&bo_va->vm->mutex);
@@ -580,7 +582,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
         }
 
         if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE))
-                amdgpu_gem_va_update_vm(adev, bo_va);
+                amdgpu_gem_va_update_vm(adev, bo_va, args->operation);
 
         drm_gem_object_unreference_unlocked(gobj);
         return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 52dff75aac6f..bc0fac618a3f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -180,16 +180,16 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
         if (vm) {
                 /* do context switch */
                 amdgpu_vm_flush(ring, vm, ib->sync.last_vm_update);
-        }
 
-        if (vm && ring->funcs->emit_gds_switch)
-                amdgpu_ring_emit_gds_switch(ring, ib->vm->ids[ring->idx].id,
-                                            ib->gds_base, ib->gds_size,
-                                            ib->gws_base, ib->gws_size,
-                                            ib->oa_base, ib->oa_size);
+                if (ring->funcs->emit_gds_switch)
+                        amdgpu_ring_emit_gds_switch(ring, ib->vm->ids[ring->idx].id,
+                                                    ib->gds_base, ib->gds_size,
+                                                    ib->gws_base, ib->gws_size,
+                                                    ib->oa_base, ib->oa_size);
 
-        if (ring->funcs->emit_hdp_flush)
-                amdgpu_ring_emit_hdp_flush(ring);
+                if (ring->funcs->emit_hdp_flush)
+                        amdgpu_ring_emit_hdp_flush(ring);
+        }
 
         old_ctx = ring->current_ctx;
         for (i = 0; i < num_ibs; ++i) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 8c40a9671b9f..93000af92283 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -242,7 +242,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
 
                 for (i = 0; i < adev->num_ip_blocks; i++) {
                         if (adev->ip_blocks[i].type == type &&
-                            adev->ip_block_enabled[i]) {
+                            adev->ip_block_status[i].valid) {
                                 ip.hw_ip_version_major = adev->ip_blocks[i].major;
                                 ip.hw_ip_version_minor = adev->ip_blocks[i].minor;
                                 ip.capabilities_flags = 0;
@@ -281,7 +281,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
 
                 for (i = 0; i < adev->num_ip_blocks; i++)
                         if (adev->ip_blocks[i].type == type &&
-                            adev->ip_block_enabled[i] &&
+                            adev->ip_block_status[i].valid &&
                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
                                 count++;
 
@@ -324,16 +324,17 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                         break;
                 case AMDGPU_INFO_FW_GFX_RLC:
                         fw_info.ver = adev->gfx.rlc_fw_version;
-                        fw_info.feature = 0;
+                        fw_info.feature = adev->gfx.rlc_feature_version;
                         break;
                 case AMDGPU_INFO_FW_GFX_MEC:
-                        if (info->query_fw.index == 0)
+                        if (info->query_fw.index == 0) {
                                 fw_info.ver = adev->gfx.mec_fw_version;
-                        else if (info->query_fw.index == 1)
+                                fw_info.feature = adev->gfx.mec_feature_version;
+                        } else if (info->query_fw.index == 1) {
                                 fw_info.ver = adev->gfx.mec2_fw_version;
-                        else
+                                fw_info.feature = adev->gfx.mec2_feature_version;
+                        } else
                                 return -EINVAL;
-                        fw_info.feature = 0;
                         break;
                 case AMDGPU_INFO_FW_SMC:
                         fw_info.ver = adev->pm.fw_version;
@@ -343,7 +344,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                         if (info->query_fw.index >= 2)
                                 return -EINVAL;
                         fw_info.ver = adev->sdma[info->query_fw.index].fw_version;
-                        fw_info.feature = 0;
+                        fw_info.feature = adev->sdma[info->query_fw.index].feature_version;
                         break;
                 default:
                         return -EINVAL;
@@ -423,7 +424,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                 return n ? -EFAULT : 0;
         }
         case AMDGPU_INFO_DEV_INFO: {
-                struct drm_amdgpu_info_device dev_info;
+                struct drm_amdgpu_info_device dev_info = {};
                 struct amdgpu_cu_info cu_info;
 
                 dev_info.device_id = dev->pdev->device;
@@ -466,6 +467,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                 memcpy(&dev_info.cu_bitmap[0], &cu_info.bitmap[0], sizeof(cu_info.bitmap));
                 dev_info.vram_type = adev->mc.vram_type;
                 dev_info.vram_bit_width = adev->mc.vram_width;
+                dev_info.vce_harvest_config = adev->vce.harvest_config;
 
                 return copy_to_user(out, &dev_info,
                                     min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 2f7a5efa21c2..f5c22556ec2c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -374,7 +374,7 @@ static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
         unsigned height_in_mb = ALIGN(height / 16, 2);
         unsigned fs_in_mb = width_in_mb * height_in_mb;
 
-        unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
+        unsigned image_size, tmp, min_dpb_size, num_dpb_buffer, min_ctx_size;
 
         image_size = width * height;
         image_size += image_size / 2;
@@ -466,6 +466,8 @@ static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
 
                 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
                 min_dpb_size = image_size * num_dpb_buffer;
+                min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
+                                           * 16 * num_dpb_buffer + 52 * 1024;
                 break;
 
         default:
@@ -486,6 +488,7 @@ static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
 
         buf_sizes[0x1] = dpb_size;
         buf_sizes[0x2] = image_size;
+        buf_sizes[0x4] = min_ctx_size;
         return 0;
 }
 
@@ -628,6 +631,13 @@ static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
                         return -EINVAL;
                 }
 
+        } else if (cmd == 0x206) {
+                if ((end - start) < ctx->buf_sizes[4]) {
+                        DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
+                                          (unsigned)(end - start),
+                                          ctx->buf_sizes[4]);
+                        return -EINVAL;
+                }
         } else if ((cmd != 0x100) && (cmd != 0x204)) {
                 DRM_ERROR("invalid UVD command %X!\n", cmd);
                 return -EINVAL;
@@ -755,9 +765,10 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
         struct amdgpu_uvd_cs_ctx ctx = {};
         unsigned buf_sizes[] = {
                 [0x00000000]    =       2048,
-                [0x00000001]    =       32 * 1024 * 1024,
-                [0x00000002]    =       2048 * 1152 * 3,
+                [0x00000001]    =       0xFFFFFFFF,
+                [0x00000002]    =       0xFFFFFFFF,
                 [0x00000003]    =       2048,
+                [0x00000004]    =       0xFFFFFFFF,
         };
         struct amdgpu_ib *ib = &parser->ibs[ib_idx];
         int r;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index ab83cc1ca4cc..15df46c93f0a 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -500,6 +500,7 @@ static int cik_sdma_load_microcode(struct amdgpu_device *adev)
                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
                 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
+                adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
                 fw_data = (const __le32 *)
                         (adev->sdma[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
index 1a2d419cbf16..ace870afc7d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
@@ -494,29 +494,67 @@ static void cz_dpm_fini(struct amdgpu_device *adev)
         amdgpu_free_extended_power_table(adev);
 }
 
+#define ixSMUSVI_NB_CURRENTVID 0xD8230044
+#define CURRENT_NB_VID_MASK 0xff000000
+#define CURRENT_NB_VID__SHIFT 24
+#define ixSMUSVI_GFX_CURRENTVID  0xD8230048
+#define CURRENT_GFX_VID_MASK 0xff000000
+#define CURRENT_GFX_VID__SHIFT 24
+
 static void
 cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
                                                struct seq_file *m)
 {
+        struct cz_power_info *pi = cz_get_pi(adev);
         struct amdgpu_clock_voltage_dependency_table *table =
                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
-        u32 current_index =
-                (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
-                TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
-                TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
-        u32 sclk, tmp;
-        u16 vddc;
-
-        if (current_index >= NUM_SCLK_LEVELS) {
-                seq_printf(m, "invalid dpm profile %d\n", current_index);
+        struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
+                &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
+        struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
+                &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
+        u32 sclk_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX),
+                                       TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
+        u32 uvd_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
+                                      TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
+        u32 vce_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
+                                      TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
+        u32 sclk, vclk, dclk, ecclk, tmp;
+        u16 vddnb, vddgfx;
+
+        if (sclk_index >= NUM_SCLK_LEVELS) {
+                seq_printf(m, "invalid sclk dpm profile %d\n", sclk_index);
         } else {
-                sclk = table->entries[current_index].clk;
-                tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &
-                        SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
-                        SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT;
-                vddc = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
-                seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
-                           current_index, sclk, vddc);
+                sclk = table->entries[sclk_index].clk;
+                seq_printf(m, "%u sclk: %u\n", sclk_index, sclk);
+        }
+
+        tmp = (RREG32_SMC(ixSMUSVI_NB_CURRENTVID) &
+               CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
+        vddnb = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
+        tmp = (RREG32_SMC(ixSMUSVI_GFX_CURRENTVID) &
+               CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
+        vddgfx = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
+        seq_printf(m, "vddnb: %u vddgfx: %u\n", vddnb, vddgfx);
+
+        seq_printf(m, "uvd    %sabled\n", pi->uvd_power_gated ? "dis" : "en");
+        if (!pi->uvd_power_gated) {
+                if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
+                        seq_printf(m, "invalid uvd dpm level %d\n", uvd_index);
+                } else {
+                        vclk = uvd_table->entries[uvd_index].vclk;
+                        dclk = uvd_table->entries[uvd_index].dclk;
+                        seq_printf(m, "%u uvd vclk: %u dclk: %u\n", uvd_index, vclk, dclk);
+                }
+        }
+
+        seq_printf(m, "vce    %sabled\n", pi->vce_power_gated ? "dis" : "en");
+        if (!pi->vce_power_gated) {
+                if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
+                        seq_printf(m, "invalid vce dpm level %d\n", vce_index);
+                } else {
+                        ecclk = vce_table->entries[vce_index].ecclk;
+                        seq_printf(m, "%u vce ecclk: %u\n", vce_index, ecclk);
+                }
         }
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 6e77964f1b64..e70a26f587a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -2632,6 +2632,7 @@ static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
         struct drm_device *dev = crtc->dev;
         struct amdgpu_device *adev = dev->dev_private;
         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
+        unsigned type;
 
         switch (mode) {
         case DRM_MODE_DPMS_ON:
@@ -2640,6 +2641,9 @@ static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
                 dce_v10_0_vga_enable(crtc, true);
                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
                 dce_v10_0_vga_enable(crtc, false);
+                /* Make sure VBLANK interrupt is still enabled */
+                type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
+                amdgpu_irq_update(adev, &adev->crtc_irq, type);
                 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
                 dce_v10_0_crtc_load_lut(crtc);
                 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 7f7abb0e0be5..dcb402ee048a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -2631,6 +2631,7 @@ static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
         struct drm_device *dev = crtc->dev;
         struct amdgpu_device *adev = dev->dev_private;
         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
+        unsigned type;
 
         switch (mode) {
         case DRM_MODE_DPMS_ON:
@@ -2639,6 +2640,9 @@ static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
                 dce_v11_0_vga_enable(crtc, true);
                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
                 dce_v11_0_vga_enable(crtc, false);
+                /* Make sure VBLANK interrupt is still enabled */
+                type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
+                amdgpu_irq_update(adev, &adev->crtc_irq, type);
                 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
                 dce_v11_0_crtc_load_lut(crtc);
                 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 2c188fb9fd22..0d8bf2cb1956 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2561,7 +2561,7 @@ static bool gfx_v7_0_ring_emit_semaphore(struct amdgpu_ring *ring,
  * sheduling on the ring.  This function schedules the IB
  * on the gfx ring for execution by the GPU.
  */
-static void gfx_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
+static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
                                   struct amdgpu_ib *ib)
 {
         bool need_ctx_switch = ring->current_ctx != ib->ctx;
@@ -2569,15 +2569,10 @@ static void gfx_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
         u32 next_rptr = ring->wptr + 5;
 
         /* drop the CE preamble IB for the same context */
-        if ((ring->type == AMDGPU_RING_TYPE_GFX) &&
-            (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
-            !need_ctx_switch)
+        if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
                 return;
 
-        if (ring->type == AMDGPU_RING_TYPE_COMPUTE)
-                control |= INDIRECT_BUFFER_VALID;
-
-        if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX)
+        if (need_ctx_switch)
                 next_rptr += 2;
 
         next_rptr += 4;
@@ -2588,7 +2583,7 @@ static void gfx_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
         amdgpu_ring_write(ring, next_rptr);
 
         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
-        if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) {
+        if (need_ctx_switch) {
                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
                 amdgpu_ring_write(ring, 0);
         }
@@ -2611,6 +2606,35 @@ static void gfx_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
         amdgpu_ring_write(ring, control);
 }
 
+static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
+                                  struct amdgpu_ib *ib)
+{
+        u32 header, control = 0;
+        u32 next_rptr = ring->wptr + 5;
+
+        control |= INDIRECT_BUFFER_VALID;
+        next_rptr += 4;
+        amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+        amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
+        amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
+        amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
+        amdgpu_ring_write(ring, next_rptr);
+
+        header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
+
+        control |= ib->length_dw |
+                           (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
+
+        amdgpu_ring_write(ring, header);
+        amdgpu_ring_write(ring,
+#ifdef __BIG_ENDIAN
+                                          (2 << 0) |
+#endif
+                                          (ib->gpu_addr & 0xFFFFFFFC));
+        amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
+        amdgpu_ring_write(ring, control);
+}
+
 /**
  * gfx_v7_0_ring_test_ib - basic ring IB test
  *
@@ -3056,6 +3080,8 @@ static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
         adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
+        adev->gfx.mec_feature_version = le32_to_cpu(
+                                        mec_hdr->ucode_feature_version);
 
         gfx_v7_0_cp_compute_enable(adev, false);
 
@@ -3078,6 +3104,8 @@ static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
                 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
                 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
                 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
+                adev->gfx.mec2_feature_version = le32_to_cpu(
+                                mec2_hdr->ucode_feature_version);
 
                 /* MEC2 */
                 fw_data = (const __le32 *)
@@ -4042,6 +4070,8 @@ static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
         hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
         amdgpu_ucode_print_rlc_hdr(&hdr->header);
         adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
+        adev->gfx.rlc_feature_version = le32_to_cpu(
+                                        hdr->ucode_feature_version);
 
         gfx_v7_0_rlc_stop(adev);
 
@@ -5098,7 +5128,7 @@ static void gfx_v7_0_print_status(void *handle)
                 dev_info(adev->dev, "  CP_HPD_EOP_CONTROL=0x%08X\n",
                          RREG32(mmCP_HPD_EOP_CONTROL));
 
-                for (queue = 0; queue < 8; i++) {
+                for (queue = 0; queue < 8; queue++) {
                         cik_srbm_select(adev, me, pipe, queue, 0);
                         dev_info(adev->dev, "  queue: %d\n", queue);
                         dev_info(adev->dev, "  CP_PQ_WPTR_POLL_CNTL=0x%08X\n",
@@ -5555,7 +5585,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
         .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
         .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
         .parse_cs = NULL,
-        .emit_ib = gfx_v7_0_ring_emit_ib,
+        .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
         .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
         .emit_semaphore = gfx_v7_0_ring_emit_semaphore,
         .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
@@ -5571,7 +5601,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
         .get_wptr = gfx_v7_0_ring_get_wptr_compute,
         .set_wptr = gfx_v7_0_ring_set_wptr_compute,
         .parse_cs = NULL,
-        .emit_ib = gfx_v7_0_ring_emit_ib,
+        .emit_ib = gfx_v7_0_ring_emit_ib_compute,
         .emit_fence = gfx_v7_0_ring_emit_fence_compute,
         .emit_semaphore = gfx_v7_0_ring_emit_semaphore,
         .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 1c7c992dea37..20e2cfd521d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -587,6 +587,7 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
         int err;
         struct amdgpu_firmware_info *info = NULL;
         const struct common_firmware_header *header = NULL;
+        const struct gfx_firmware_header_v1_0 *cp_hdr;
 
         DRM_DEBUG("\n");
 
@@ -611,6 +612,9 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
         if (err)
                 goto out;
+        cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
+        adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+        adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 
         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
@@ -619,6 +623,9 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
         err = amdgpu_ucode_validate(adev->gfx.me_fw);
         if (err)
                 goto out;
+        cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
+        adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+        adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 
         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
@@ -627,12 +634,18 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
         if (err)
                 goto out;
+        cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
+        adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+        adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 
         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
         if (err)
                 goto out;
         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
+        cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
+        adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+        adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 
         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
@@ -641,6 +654,9 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
         if (err)
                 goto out;
+        cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
+        adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+        adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 
         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
@@ -648,6 +664,12 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
                 if (err)
                         goto out;
+                cp_hdr = (const struct gfx_firmware_header_v1_0 *)
+                                                adev->gfx.mec2_fw->data;
+                adev->gfx.mec2_fw_version = le32_to_cpu(
+                                                cp_hdr->header.ucode_version);
+                adev->gfx.mec2_feature_version = le32_to_cpu(
+                                                cp_hdr->ucode_feature_version);
         } else {
                 err = 0;
                 adev->gfx.mec2_fw = NULL;
@@ -1983,6 +2005,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
                 adev->gfx.config.max_shader_engines = 1;
                 adev->gfx.config.max_tile_pipes = 2;
                 adev->gfx.config.max_sh_per_se = 1;
+                adev->gfx.config.max_backends_per_se = 2;
 
                 switch (adev->pdev->revision) {
                 case 0xc4:
@@ -1991,7 +2014,6 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
                 case 0xcc:
                         /* B10 */
                         adev->gfx.config.max_cu_per_sh = 8;
-                        adev->gfx.config.max_backends_per_se = 2;
                         break;
                 case 0xc5:
                 case 0x81:
@@ -2000,14 +2022,12 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
                 case 0xcd:
                         /* B8 */
                         adev->gfx.config.max_cu_per_sh = 6;
-                        adev->gfx.config.max_backends_per_se = 2;
                         break;
                 case 0xc6:
                 case 0xca:
                 case 0xce:
                         /* B6 */
                         adev->gfx.config.max_cu_per_sh = 6;
-                        adev->gfx.config.max_backends_per_se = 2;
                         break;
                 case 0xc7:
                 case 0x87:
@@ -2015,7 +2035,6 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
                 default:
                         /* B4 */
                         adev->gfx.config.max_cu_per_sh = 4;
-                        adev->gfx.config.max_backends_per_se = 1;
                         break;
                 }
 
@@ -2275,7 +2294,6 @@ static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
 
         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
         amdgpu_ucode_print_rlc_hdr(&hdr->header);
-        adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
 
         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
@@ -2361,12 +2379,6 @@ static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
-        adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
-        adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
-        adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
-        adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
-        adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
-        adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
 
         gfx_v8_0_cp_gfx_enable(adev, false);
 
@@ -2622,7 +2634,6 @@ static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
 
         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
-        adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
 
         fw_data = (const __le32 *)
                 (adev->gfx.mec_fw->data +
@@ -2641,7 +2652,6 @@ static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
 
                 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
                 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
-                adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
 
                 fw_data = (const __le32 *)
                         (adev->gfx.mec2_fw->data +
@@ -3125,7 +3135,7 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
                                 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
                                        AMDGPU_DOORBELL_KIQ << 2);
                                 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
-                                                0x7FFFF << 2);
+                                       AMDGPU_DOORBELL_MEC_RING7 << 2);
                         }
                         tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
@@ -3753,7 +3763,7 @@ static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
         amdgpu_ring_write(ring, 0x20); /* poll interval */
 }
 
-static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring,
+static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
                                   struct amdgpu_ib *ib)
 {
         bool need_ctx_switch = ring->current_ctx != ib->ctx;
@@ -3761,15 +3771,10 @@ static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring,
         u32 next_rptr = ring->wptr + 5;
 
         /* drop the CE preamble IB for the same context */
-        if ((ring->type == AMDGPU_RING_TYPE_GFX) &&
-            (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
-            !need_ctx_switch)
+        if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
                 return;
 
-        if (ring->type == AMDGPU_RING_TYPE_COMPUTE)
-                control |= INDIRECT_BUFFER_VALID;
-
-        if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX)
+        if (need_ctx_switch)
                 next_rptr += 2;
 
         next_rptr += 4;
@@ -3780,7 +3785,7 @@ static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring,
         amdgpu_ring_write(ring, next_rptr);
 
         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
-        if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) {
+        if (need_ctx_switch) {
                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
                 amdgpu_ring_write(ring, 0);
         }
@@ -3803,6 +3808,36 @@ static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring,
         amdgpu_ring_write(ring, control);
 }
 
+static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
+                                  struct amdgpu_ib *ib)
+{
+        u32 header, control = 0;
+        u32 next_rptr = ring->wptr + 5;
+
+        control |= INDIRECT_BUFFER_VALID;
+
+        next_rptr += 4;
+        amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+        amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
+        amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
+        amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
+        amdgpu_ring_write(ring, next_rptr);
+
+        header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
+
+        control |= ib->length_dw |
+                           (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
+
+        amdgpu_ring_write(ring, header);
+        amdgpu_ring_write(ring,
+#ifdef __BIG_ENDIAN
+                                          (2 << 0) |
+#endif
+                                          (ib->gpu_addr & 0xFFFFFFFC));
+        amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
+        amdgpu_ring_write(ring, control);
+}
+
 static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
                                          u64 seq, unsigned flags)
 {
@@ -4224,7 +4259,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
         .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
         .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
         .parse_cs = NULL,
-        .emit_ib = gfx_v8_0_ring_emit_ib,
+        .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
         .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
         .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
         .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
@@ -4240,7 +4275,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
         .get_wptr = gfx_v8_0_ring_get_wptr_compute,
         .set_wptr = gfx_v8_0_ring_set_wptr_compute,
         .parse_cs = NULL,
-        .emit_ib = gfx_v8_0_ring_emit_ib,
+        .emit_ib = gfx_v8_0_ring_emit_ib_compute,
         .emit_fence = gfx_v8_0_ring_emit_fence_compute,
         .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
         .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index d7895885fe0c..a988dfb1d394 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -121,6 +121,7 @@ static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
         int err, i;
         struct amdgpu_firmware_info *info = NULL;
         const struct common_firmware_header *header = NULL;
+        const struct sdma_firmware_header_v1_0 *hdr;
 
         DRM_DEBUG("\n");
 
@@ -142,6 +143,9 @@ static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
                 err = amdgpu_ucode_validate(adev->sdma[i].fw);
                 if (err)
                         goto out;
+                hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
+                adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
+                adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 
                 if (adev->firmware.smu_load) {
                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
@@ -541,8 +545,6 @@ static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
                         hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
                         amdgpu_ucode_print_sdma_hdr(&hdr->header);
                         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
-                        adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
-
                         fw_data = (const __le32 *)
                                 (adev->sdma[i].fw->data +
                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 7bb37b93993f..2b86569b18d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -159,6 +159,7 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
         int err, i;
         struct amdgpu_firmware_info *info = NULL;
         const struct common_firmware_header *header = NULL;
+        const struct sdma_firmware_header_v1_0 *hdr;
 
         DRM_DEBUG("\n");
 
@@ -183,6 +184,9 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
                 err = amdgpu_ucode_validate(adev->sdma[i].fw);
                 if (err)
                         goto out;
+                hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
+                adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
+                adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 
                 if (adev->firmware.smu_load) {
                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
@@ -630,8 +634,6 @@ static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
-                adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
-
                 fw_data = (const __le32 *)
                         (adev->sdma[i].fw->data +
                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index d62c4002e39c..d1064ca3670e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -35,6 +35,8 @@
 #include "oss/oss_2_0_d.h"
 #include "oss/oss_2_0_sh_mask.h"
 #include "gca/gfx_8_0_d.h"
+#include "smu/smu_7_1_2_d.h"
+#include "smu/smu_7_1_2_sh_mask.h"
 
 #define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT     0x04
 #define GRBM_GFX_INDEX__VCE_INSTANCE_MASK       0x10
@@ -112,6 +114,10 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
 
         mutex_lock(&adev->grbm_idx_mutex);
         for (idx = 0; idx < 2; ++idx) {
+
+                if (adev->vce.harvest_config & (1 << idx))
+                        continue;
+
                 if(idx == 0)
                         WREG32_P(mmGRBM_GFX_INDEX, 0,
                                 ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK);
@@ -190,10 +196,52 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
         return 0;
 }
 
+#define ixVCE_HARVEST_FUSE_MACRO__ADDRESS     0xC0014074
+#define VCE_HARVEST_FUSE_MACRO__SHIFT       27
+#define VCE_HARVEST_FUSE_MACRO__MASK        0x18000000
+
+static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
+{
+        u32 tmp;
+        unsigned ret;
+
+        if (adev->flags & AMDGPU_IS_APU)
+                tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) &
+                       VCE_HARVEST_FUSE_MACRO__MASK) >>
+                        VCE_HARVEST_FUSE_MACRO__SHIFT;
+        else
+                tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) &
+                       CC_HARVEST_FUSES__VCE_DISABLE_MASK) >>
+                        CC_HARVEST_FUSES__VCE_DISABLE__SHIFT;
+
+        switch (tmp) {
+        case 1:
+                ret = AMDGPU_VCE_HARVEST_VCE0;
+                break;
+        case 2:
+                ret = AMDGPU_VCE_HARVEST_VCE1;
+                break;
+        case 3:
+                ret = AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1;
+                break;
+        default:
+                ret = 0;
+        }
+
+        return ret;
+}
+
 static int vce_v3_0_early_init(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+        adev->vce.harvest_config = vce_v3_0_get_harvest_config(adev);
+
+        if ((adev->vce.harvest_config &
+             (AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1)) ==
+            (AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1))
+                return -ENOENT;
+
         vce_v3_0_set_ring_funcs(adev);
         vce_v3_0_set_irq_funcs(adev);