diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vce_v3_0.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index d62c4002e39c..d1064ca3670e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | |||
@@ -35,6 +35,8 @@ | |||
35 | #include "oss/oss_2_0_d.h" | 35 | #include "oss/oss_2_0_d.h" |
36 | #include "oss/oss_2_0_sh_mask.h" | 36 | #include "oss/oss_2_0_sh_mask.h" |
37 | #include "gca/gfx_8_0_d.h" | 37 | #include "gca/gfx_8_0_d.h" |
38 | #include "smu/smu_7_1_2_d.h" | ||
39 | #include "smu/smu_7_1_2_sh_mask.h" | ||
38 | 40 | ||
39 | #define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04 | 41 | #define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04 |
40 | #define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10 | 42 | #define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10 |
@@ -112,6 +114,10 @@ static int vce_v3_0_start(struct amdgpu_device *adev) | |||
112 | 114 | ||
113 | mutex_lock(&adev->grbm_idx_mutex); | 115 | mutex_lock(&adev->grbm_idx_mutex); |
114 | for (idx = 0; idx < 2; ++idx) { | 116 | for (idx = 0; idx < 2; ++idx) { |
117 | |||
118 | if (adev->vce.harvest_config & (1 << idx)) | ||
119 | continue; | ||
120 | |||
115 | if(idx == 0) | 121 | if(idx == 0) |
116 | WREG32_P(mmGRBM_GFX_INDEX, 0, | 122 | WREG32_P(mmGRBM_GFX_INDEX, 0, |
117 | ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK); | 123 | ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK); |
@@ -190,10 +196,52 @@ static int vce_v3_0_start(struct amdgpu_device *adev) | |||
190 | return 0; | 196 | return 0; |
191 | } | 197 | } |
192 | 198 | ||
199 | #define ixVCE_HARVEST_FUSE_MACRO__ADDRESS 0xC0014074 | ||
200 | #define VCE_HARVEST_FUSE_MACRO__SHIFT 27 | ||
201 | #define VCE_HARVEST_FUSE_MACRO__MASK 0x18000000 | ||
202 | |||
203 | static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev) | ||
204 | { | ||
205 | u32 tmp; | ||
206 | unsigned ret; | ||
207 | |||
208 | if (adev->flags & AMDGPU_IS_APU) | ||
209 | tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) & | ||
210 | VCE_HARVEST_FUSE_MACRO__MASK) >> | ||
211 | VCE_HARVEST_FUSE_MACRO__SHIFT; | ||
212 | else | ||
213 | tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) & | ||
214 | CC_HARVEST_FUSES__VCE_DISABLE_MASK) >> | ||
215 | CC_HARVEST_FUSES__VCE_DISABLE__SHIFT; | ||
216 | |||
217 | switch (tmp) { | ||
218 | case 1: | ||
219 | ret = AMDGPU_VCE_HARVEST_VCE0; | ||
220 | break; | ||
221 | case 2: | ||
222 | ret = AMDGPU_VCE_HARVEST_VCE1; | ||
223 | break; | ||
224 | case 3: | ||
225 | ret = AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1; | ||
226 | break; | ||
227 | default: | ||
228 | ret = 0; | ||
229 | } | ||
230 | |||
231 | return ret; | ||
232 | } | ||
233 | |||
193 | static int vce_v3_0_early_init(void *handle) | 234 | static int vce_v3_0_early_init(void *handle) |
194 | { | 235 | { |
195 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | 236 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
196 | 237 | ||
238 | adev->vce.harvest_config = vce_v3_0_get_harvest_config(adev); | ||
239 | |||
240 | if ((adev->vce.harvest_config & | ||
241 | (AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1)) == | ||
242 | (AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1)) | ||
243 | return -ENOENT; | ||
244 | |||
197 | vce_v3_0_set_ring_funcs(adev); | 245 | vce_v3_0_set_ring_funcs(adev); |
198 | vce_v3_0_set_irq_funcs(adev); | 246 | vce_v3_0_set_irq_funcs(adev); |
199 | 247 | ||