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authorChristian König <christian.koenig@amd.com>2017-12-18 11:08:25 -0500
committerAlex Deucher <alexander.deucher@amd.com>2017-12-27 11:34:02 -0500
commitc4f46f22c448ff571eb8fdbe4ab71a25805228d1 (patch)
tree50d8eafedcb7b1bbc3fa00561101d395d9ec003b /drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
parent620f774f4687d86c420152309eefb0ef0fcc7e51 (diff)
drm/amdgpu: rename vm_id to vmid
sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.c sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.h Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c36
1 files changed, 18 insertions, 18 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index deb3fba790a5..b99e15c43e45 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -833,13 +833,13 @@ static void vcn_v1_0_dec_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
833 */ 833 */
834static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 834static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
835 struct amdgpu_ib *ib, 835 struct amdgpu_ib *ib,
836 unsigned vm_id, bool ctx_switch) 836 unsigned vmid, bool ctx_switch)
837{ 837{
838 struct amdgpu_device *adev = ring->adev; 838 struct amdgpu_device *adev = ring->adev;
839 839
840 amdgpu_ring_write(ring, 840 amdgpu_ring_write(ring,
841 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); 841 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
842 amdgpu_ring_write(ring, vm_id); 842 amdgpu_ring_write(ring, vmid);
843 843
844 amdgpu_ring_write(ring, 844 amdgpu_ring_write(ring,
845 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 845 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
@@ -888,10 +888,10 @@ static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring,
888} 888}
889 889
890static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 890static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
891 unsigned vm_id, uint64_t pd_addr) 891 unsigned vmid, uint64_t pd_addr)
892{ 892{
893 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 893 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
894 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); 894 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
895 uint64_t flags = AMDGPU_PTE_VALID; 895 uint64_t flags = AMDGPU_PTE_VALID;
896 unsigned eng = ring->vm_inv_eng; 896 unsigned eng = ring->vm_inv_eng;
897 uint32_t data0, data1, mask; 897 uint32_t data0, data1, mask;
@@ -899,15 +899,15 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
899 amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags); 899 amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
900 pd_addr |= flags; 900 pd_addr |= flags;
901 901
902 data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2; 902 data0 = (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2;
903 data1 = upper_32_bits(pd_addr); 903 data1 = upper_32_bits(pd_addr);
904 vcn_v1_0_dec_vm_reg_write(ring, data0, data1); 904 vcn_v1_0_dec_vm_reg_write(ring, data0, data1);
905 905
906 data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2; 906 data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
907 data1 = lower_32_bits(pd_addr); 907 data1 = lower_32_bits(pd_addr);
908 vcn_v1_0_dec_vm_reg_write(ring, data0, data1); 908 vcn_v1_0_dec_vm_reg_write(ring, data0, data1);
909 909
910 data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2; 910 data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
911 data1 = lower_32_bits(pd_addr); 911 data1 = lower_32_bits(pd_addr);
912 mask = 0xffffffff; 912 mask = 0xffffffff;
913 vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask); 913 vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask);
@@ -919,8 +919,8 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
919 919
920 /* wait for flush */ 920 /* wait for flush */
921 data0 = (hub->vm_inv_eng0_ack + eng) << 2; 921 data0 = (hub->vm_inv_eng0_ack + eng) << 2;
922 data1 = 1 << vm_id; 922 data1 = 1 << vmid;
923 mask = 1 << vm_id; 923 mask = 1 << vmid;
924 vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask); 924 vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask);
925} 925}
926 926
@@ -1011,20 +1011,20 @@ static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1011 * Write enc ring commands to execute the indirect buffer 1011 * Write enc ring commands to execute the indirect buffer
1012 */ 1012 */
1013static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1013static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1014 struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch) 1014 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
1015{ 1015{
1016 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1016 amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1017 amdgpu_ring_write(ring, vm_id); 1017 amdgpu_ring_write(ring, vmid);
1018 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1018 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1019 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1019 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1020 amdgpu_ring_write(ring, ib->length_dw); 1020 amdgpu_ring_write(ring, ib->length_dw);
1021} 1021}
1022 1022
1023static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1023static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1024 unsigned int vm_id, uint64_t pd_addr) 1024 unsigned int vmid, uint64_t pd_addr)
1025{ 1025{
1026 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1026 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1027 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); 1027 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
1028 uint64_t flags = AMDGPU_PTE_VALID; 1028 uint64_t flags = AMDGPU_PTE_VALID;
1029 unsigned eng = ring->vm_inv_eng; 1029 unsigned eng = ring->vm_inv_eng;
1030 1030
@@ -1033,17 +1033,17 @@ static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1033 1033
1034 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1034 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1035 amdgpu_ring_write(ring, 1035 amdgpu_ring_write(ring,
1036 (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2); 1036 (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2);
1037 amdgpu_ring_write(ring, upper_32_bits(pd_addr)); 1037 amdgpu_ring_write(ring, upper_32_bits(pd_addr));
1038 1038
1039 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1039 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1040 amdgpu_ring_write(ring, 1040 amdgpu_ring_write(ring,
1041 (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2); 1041 (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
1042 amdgpu_ring_write(ring, lower_32_bits(pd_addr)); 1042 amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1043 1043
1044 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1044 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1045 amdgpu_ring_write(ring, 1045 amdgpu_ring_write(ring,
1046 (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2); 1046 (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
1047 amdgpu_ring_write(ring, 0xffffffff); 1047 amdgpu_ring_write(ring, 0xffffffff);
1048 amdgpu_ring_write(ring, lower_32_bits(pd_addr)); 1048 amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1049 1049
@@ -1055,8 +1055,8 @@ static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1055 /* wait for flush */ 1055 /* wait for flush */
1056 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1056 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1057 amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2); 1057 amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
1058 amdgpu_ring_write(ring, 1 << vm_id); 1058 amdgpu_ring_write(ring, 1 << vmid);
1059 amdgpu_ring_write(ring, 1 << vm_id); 1059 amdgpu_ring_write(ring, 1 << vmid);
1060} 1060}
1061 1061
1062static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev, 1062static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,