drm/amdgpu: move struct amdgpu_mc into amdgpu_gmc.h

And rename it to amdgpu_gmc as well.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Samuel Li <Samuel.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 9 insertions, 9 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index ce675a7f179a..9d57115a2d67 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -3064,7 +3064,7 @@ static bool si_dpm_vblank_too_short(void *handle)
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
         /* we never hit the non-gddr5 limit so disable it */
-        u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
+        u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
 
         if (vblank_time < switch_limit)
                 return true;
@@ -4350,7 +4350,7 @@ static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
         if (mclk <= pi->mclk_strobe_mode_threshold)
                 strobe_mode = true;
 
-        if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
+        if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
         else
                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
@@ -4937,7 +4937,7 @@ static int si_populate_smc_initial_state(struct amdgpu_device *adev,
         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
         table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
 
-        if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
+        if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
                 table->initialState.levels[0].strobeMode =
                         si_get_strobe_mode_settings(adev,
                                                     initial_state->performance_levels[0].mclk);
@@ -5208,7 +5208,7 @@ static int si_init_smc_table(struct amdgpu_device *adev)
         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
 
-        if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
+        if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
 
         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
@@ -5385,7 +5385,7 @@ static int si_populate_mclk_value(struct amdgpu_device *adev,
         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
 
-        if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
+        if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
                         YCLK_POST_DIV(mpll_param.post_div);
@@ -5397,7 +5397,7 @@ static int si_populate_mclk_value(struct amdgpu_device *adev,
                 u32 tmp;
                 u32 reference_clock = adev->clock.mpll.reference_freq;
 
-                if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
+                if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
                         freq_nom = memory_clock * 4;
                 else
                         freq_nom = memory_clock * 2;
@@ -5489,7 +5489,7 @@ static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
         }
 
-        if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
+        if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
                 if (pl->mclk > pi->mclk_edc_enable_threshold)
                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
 
@@ -5860,12 +5860,12 @@ static int si_set_mc_special_registers(struct amdgpu_device *adev,
                                 table->mc_reg_table_entry[k].mc_data[j] =
                                         (temp_reg & 0xffff0000) |
                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
-                                if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
+                                if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
                         }
                         j++;
 
-                        if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
+                        if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
                                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
                                         return -EINVAL;
                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;