aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/amdgpu
diff options
context:
space:
mode:
authorChristian König <christian.koenig@amd.com>2018-01-12 08:52:22 -0500
committerAlex Deucher <alexander.deucher@amd.com>2018-02-19 14:17:43 -0500
commit770d13b19fdf365a99e559f1d47f1380910a947d (patch)
treed9c9e2f506facd092fb3c85663d6d08fb1bf50a7 /drivers/gpu/drm/amd/amdgpu
parentda320625de81f508bbe658d57bfa015ff8894de2 (diff)
drm/amdgpu: move struct amdgpu_mc into amdgpu_gmc.h
And rename it to amdgpu_gmc as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Samuel Li <Samuel.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h56
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c16
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c16
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h84
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_object.c30
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_test.c12
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c46
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/ci_dpm.c12
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_sdma.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v10_0.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v11_0.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v6_0.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v8_0.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_virtual.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c24
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c80
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c106
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c134
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c80
-rw-r--r--drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c24
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si_dma.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si_dpm.c18
35 files changed, 431 insertions, 395 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 7a9b24e9067f..1b369a62bac3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -68,6 +68,7 @@
68#include "amdgpu_vce.h" 68#include "amdgpu_vce.h"
69#include "amdgpu_vcn.h" 69#include "amdgpu_vcn.h"
70#include "amdgpu_mn.h" 70#include "amdgpu_mn.h"
71#include "amdgpu_gmc.h"
71#include "amdgpu_dm.h" 72#include "amdgpu_dm.h"
72#include "amdgpu_virt.h" 73#include "amdgpu_virt.h"
73#include "amdgpu_gart.h" 74#include "amdgpu_gart.h"
@@ -496,55 +497,6 @@ int amdgpu_fence_slab_init(void);
496void amdgpu_fence_slab_fini(void); 497void amdgpu_fence_slab_fini(void);
497 498
498/* 499/*
499 * VMHUB structures, functions & helpers
500 */
501struct amdgpu_vmhub {
502 uint32_t ctx0_ptb_addr_lo32;
503 uint32_t ctx0_ptb_addr_hi32;
504 uint32_t vm_inv_eng0_req;
505 uint32_t vm_inv_eng0_ack;
506 uint32_t vm_context0_cntl;
507 uint32_t vm_l2_pro_fault_status;
508 uint32_t vm_l2_pro_fault_cntl;
509};
510
511/*
512 * GPU MC structures, functions & helpers
513 */
514struct amdgpu_mc {
515 resource_size_t aper_size;
516 resource_size_t aper_base;
517 /* for some chips with <= 32MB we need to lie
518 * about vram size near mc fb location */
519 u64 mc_vram_size;
520 u64 visible_vram_size;
521 u64 gart_size;
522 u64 gart_start;
523 u64 gart_end;
524 u64 vram_start;
525 u64 vram_end;
526 unsigned vram_width;
527 u64 real_vram_size;
528 int vram_mtrr;
529 u64 mc_mask;
530 const struct firmware *fw; /* MC firmware */
531 uint32_t fw_version;
532 struct amdgpu_irq_src vm_fault;
533 uint32_t vram_type;
534 uint32_t srbm_soft_reset;
535 bool prt_warning;
536 uint64_t stolen_size;
537 /* apertures */
538 u64 shared_aperture_start;
539 u64 shared_aperture_end;
540 u64 private_aperture_start;
541 u64 private_aperture_end;
542 /* protects concurrent invalidation */
543 spinlock_t invalidate_lock;
544 bool translate_further;
545};
546
547/*
548 * GPU doorbell structures, functions & helpers 500 * GPU doorbell structures, functions & helpers
549 */ 501 */
550typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 502typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
@@ -1579,7 +1531,7 @@ struct amdgpu_device {
1579 struct amdgpu_clock clock; 1531 struct amdgpu_clock clock;
1580 1532
1581 /* MC */ 1533 /* MC */
1582 struct amdgpu_mc mc; 1534 struct amdgpu_gmc gmc;
1583 struct amdgpu_gart gart; 1535 struct amdgpu_gart gart;
1584 struct amdgpu_dummy_page dummy_page; 1536 struct amdgpu_dummy_page dummy_page;
1585 struct amdgpu_vm_manager vm_manager; 1537 struct amdgpu_vm_manager vm_manager;
@@ -1908,9 +1860,9 @@ void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1908void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 1860void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
1909bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 1861bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
1910void amdgpu_device_vram_location(struct amdgpu_device *adev, 1862void amdgpu_device_vram_location(struct amdgpu_device *adev,
1911 struct amdgpu_mc *mc, u64 base); 1863 struct amdgpu_gmc *mc, u64 base);
1912void amdgpu_device_gart_location(struct amdgpu_device *adev, 1864void amdgpu_device_gart_location(struct amdgpu_device *adev,
1913 struct amdgpu_mc *mc); 1865 struct amdgpu_gmc *mc);
1914int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1866int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1915void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 1867void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
1916int amdgpu_ttm_init(struct amdgpu_device *adev); 1868int amdgpu_ttm_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 1d605e1c1d66..285916c93c3d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -281,21 +281,21 @@ void get_local_mem_info(struct kgd_dev *kgd,
281 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 281 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
282 uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask : 282 uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask :
283 ~((1ULL << 32) - 1); 283 ~((1ULL << 32) - 1);
284 resource_size_t aper_limit = adev->mc.aper_base + adev->mc.aper_size; 284 resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size;
285 285
286 memset(mem_info, 0, sizeof(*mem_info)); 286 memset(mem_info, 0, sizeof(*mem_info));
287 if (!(adev->mc.aper_base & address_mask || aper_limit & address_mask)) { 287 if (!(adev->gmc.aper_base & address_mask || aper_limit & address_mask)) {
288 mem_info->local_mem_size_public = adev->mc.visible_vram_size; 288 mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
289 mem_info->local_mem_size_private = adev->mc.real_vram_size - 289 mem_info->local_mem_size_private = adev->gmc.real_vram_size -
290 adev->mc.visible_vram_size; 290 adev->gmc.visible_vram_size;
291 } else { 291 } else {
292 mem_info->local_mem_size_public = 0; 292 mem_info->local_mem_size_public = 0;
293 mem_info->local_mem_size_private = adev->mc.real_vram_size; 293 mem_info->local_mem_size_private = adev->gmc.real_vram_size;
294 } 294 }
295 mem_info->vram_width = adev->mc.vram_width; 295 mem_info->vram_width = adev->gmc.vram_width;
296 296
297 pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n", 297 pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n",
298 &adev->mc.aper_base, &aper_limit, 298 &adev->gmc.aper_base, &aper_limit,
299 mem_info->local_mem_size_public, 299 mem_info->local_mem_size_public,
300 mem_info->local_mem_size_private); 300 mem_info->local_mem_size_private);
301 301
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index e80fc38141b5..fb12a7c6eeac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -257,7 +257,7 @@ static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
257 return; 257 return;
258 } 258 }
259 259
260 total_vram = adev->mc.real_vram_size - adev->vram_pin_size; 260 total_vram = adev->gmc.real_vram_size - adev->vram_pin_size;
261 used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 261 used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
262 free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram; 262 free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
263 263
@@ -302,8 +302,8 @@ static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
302 *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us); 302 *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
303 303
304 /* Do the same for visible VRAM if half of it is free */ 304 /* Do the same for visible VRAM if half of it is free */
305 if (adev->mc.visible_vram_size < adev->mc.real_vram_size) { 305 if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size) {
306 u64 total_vis_vram = adev->mc.visible_vram_size; 306 u64 total_vis_vram = adev->gmc.visible_vram_size;
307 u64 used_vis_vram = 307 u64 used_vis_vram =
308 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 308 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
309 309
@@ -359,7 +359,7 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
359 * to move it. Don't move anything if the threshold is zero. 359 * to move it. Don't move anything if the threshold is zero.
360 */ 360 */
361 if (p->bytes_moved < p->bytes_moved_threshold) { 361 if (p->bytes_moved < p->bytes_moved_threshold) {
362 if (adev->mc.visible_vram_size < adev->mc.real_vram_size && 362 if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
363 (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) { 363 (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
364 /* And don't move a CPU_ACCESS_REQUIRED BO to limited 364 /* And don't move a CPU_ACCESS_REQUIRED BO to limited
365 * visible VRAM if we've depleted our allowance to do 365 * visible VRAM if we've depleted our allowance to do
@@ -381,9 +381,9 @@ retry:
381 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 381 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
382 382
383 p->bytes_moved += ctx.bytes_moved; 383 p->bytes_moved += ctx.bytes_moved;
384 if (adev->mc.visible_vram_size < adev->mc.real_vram_size && 384 if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
385 bo->tbo.mem.mem_type == TTM_PL_VRAM && 385 bo->tbo.mem.mem_type == TTM_PL_VRAM &&
386 bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT) 386 bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
387 p->bytes_moved_vis += ctx.bytes_moved; 387 p->bytes_moved_vis += ctx.bytes_moved;
388 388
389 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { 389 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
@@ -437,9 +437,9 @@ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
437 /* Good we can try to move this BO somewhere else */ 437 /* Good we can try to move this BO somewhere else */
438 amdgpu_ttm_placement_from_domain(bo, other); 438 amdgpu_ttm_placement_from_domain(bo, other);
439 update_bytes_moved_vis = 439 update_bytes_moved_vis =
440 adev->mc.visible_vram_size < adev->mc.real_vram_size && 440 adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
441 bo->tbo.mem.mem_type == TTM_PL_VRAM && 441 bo->tbo.mem.mem_type == TTM_PL_VRAM &&
442 bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT; 442 bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT;
443 initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); 443 initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
444 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 444 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
445 bytes_moved = atomic64_read(&adev->num_bytes_moved) - 445 bytes_moved = atomic64_read(&adev->num_bytes_moved) -
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 00a50cc5ec9a..a2204c770776 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -544,7 +544,7 @@ void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
544 * as parameter. 544 * as parameter.
545 */ 545 */
546void amdgpu_device_vram_location(struct amdgpu_device *adev, 546void amdgpu_device_vram_location(struct amdgpu_device *adev,
547 struct amdgpu_mc *mc, u64 base) 547 struct amdgpu_gmc *mc, u64 base)
548{ 548{
549 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; 549 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
550 550
@@ -570,11 +570,11 @@ void amdgpu_device_vram_location(struct amdgpu_device *adev,
570 * FIXME: when reducing GTT size align new size on power of 2. 570 * FIXME: when reducing GTT size align new size on power of 2.
571 */ 571 */
572void amdgpu_device_gart_location(struct amdgpu_device *adev, 572void amdgpu_device_gart_location(struct amdgpu_device *adev,
573 struct amdgpu_mc *mc) 573 struct amdgpu_gmc *mc)
574{ 574{
575 u64 size_af, size_bf; 575 u64 size_af, size_bf;
576 576
577 size_af = adev->mc.mc_mask - mc->vram_end; 577 size_af = adev->gmc.mc_mask - mc->vram_end;
578 size_bf = mc->vram_start; 578 size_bf = mc->vram_start;
579 if (size_bf > size_af) { 579 if (size_bf > size_af) {
580 if (mc->gart_size > size_bf) { 580 if (mc->gart_size > size_bf) {
@@ -608,7 +608,7 @@ void amdgpu_device_gart_location(struct amdgpu_device *adev,
608 */ 608 */
609int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) 609int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
610{ 610{
611 u64 space_needed = roundup_pow_of_two(adev->mc.real_vram_size); 611 u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
612 u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1; 612 u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
613 struct pci_bus *root; 613 struct pci_bus *root;
614 struct resource *res; 614 struct resource *res;
@@ -1768,7 +1768,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
1768 adev->flags = flags; 1768 adev->flags = flags;
1769 adev->asic_type = flags & AMD_ASIC_MASK; 1769 adev->asic_type = flags & AMD_ASIC_MASK;
1770 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; 1770 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1771 adev->mc.gart_size = 512 * 1024 * 1024; 1771 adev->gmc.gart_size = 512 * 1024 * 1024;
1772 adev->accel_working = false; 1772 adev->accel_working = false;
1773 adev->num_rings = 0; 1773 adev->num_rings = 0;
1774 adev->mman.buffer_funcs = NULL; 1774 adev->mman.buffer_funcs = NULL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 17a3ef297fd6..a7423dd692b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -244,8 +244,8 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
244 244
245 info->fbops = &amdgpufb_ops; 245 info->fbops = &amdgpufb_ops;
246 246
247 tmp = amdgpu_bo_gpu_offset(abo) - adev->mc.vram_start; 247 tmp = amdgpu_bo_gpu_offset(abo) - adev->gmc.vram_start;
248 info->fix.smem_start = adev->mc.aper_base + tmp; 248 info->fix.smem_start = adev->gmc.aper_base + tmp;
249 info->fix.smem_len = amdgpu_bo_size(abo); 249 info->fix.smem_len = amdgpu_bo_size(abo);
250 info->screen_base = amdgpu_bo_kptr(abo); 250 info->screen_base = amdgpu_bo_kptr(abo);
251 info->screen_size = amdgpu_bo_size(abo); 251 info->screen_size = amdgpu_bo_size(abo);
@@ -254,7 +254,7 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
254 254
255 /* setup aperture base/size for vesafb takeover */ 255 /* setup aperture base/size for vesafb takeover */
256 info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base; 256 info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base;
257 info->apertures->ranges[0].size = adev->mc.aper_size; 257 info->apertures->ranges[0].size = adev->gmc.aper_size;
258 258
259 /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ 259 /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
260 260
@@ -264,7 +264,7 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
264 } 264 }
265 265
266 DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); 266 DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
267 DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->mc.aper_base); 267 DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base);
268 DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo)); 268 DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo));
269 DRM_INFO("fb depth is %d\n", fb->format->depth); 269 DRM_INFO("fb depth is %d\n", fb->format->depth);
270 DRM_INFO(" pitch is %d\n", fb->pitches[0]); 270 DRM_INFO(" pitch is %d\n", fb->pitches[0]);
@@ -321,7 +321,7 @@ int amdgpu_fbdev_init(struct amdgpu_device *adev)
321 return 0; 321 return 0;
322 322
323 /* select 8 bpp console on low vram cards */ 323 /* select 8 bpp console on low vram cards */
324 if (adev->mc.real_vram_size <= (32*1024*1024)) 324 if (adev->gmc.real_vram_size <= (32*1024*1024))
325 bpp_sel = 8; 325 bpp_sel = 8;
326 326
327 rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL); 327 rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index d0617f1c252f..b730dee4cb0e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -359,8 +359,8 @@ int amdgpu_gart_init(struct amdgpu_device *adev)
359 if (r) 359 if (r)
360 return r; 360 return r;
361 /* Compute table size */ 361 /* Compute table size */
362 adev->gart.num_cpu_pages = adev->mc.gart_size / PAGE_SIZE; 362 adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE;
363 adev->gart.num_gpu_pages = adev->mc.gart_size / AMDGPU_GPU_PAGE_SIZE; 363 adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE;
364 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", 364 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
365 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages); 365 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);
366 366
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
new file mode 100644
index 000000000000..e867be599b8d
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -0,0 +1,84 @@
1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26#ifndef __AMDGPU_GMC_H__
27#define __AMDGPU_GMC_H__
28
29#include <linux/types.h>
30
31#include "amdgpu_irq.h"
32
33struct firmware;
34
35/*
36 * VMHUB structures, functions & helpers
37 */
38struct amdgpu_vmhub {
39 uint32_t ctx0_ptb_addr_lo32;
40 uint32_t ctx0_ptb_addr_hi32;
41 uint32_t vm_inv_eng0_req;
42 uint32_t vm_inv_eng0_ack;
43 uint32_t vm_context0_cntl;
44 uint32_t vm_l2_pro_fault_status;
45 uint32_t vm_l2_pro_fault_cntl;
46};
47
48/*
49 * GPU MC structures, functions & helpers
50 */
51struct amdgpu_gmc {
52 resource_size_t aper_size;
53 resource_size_t aper_base;
54 /* for some chips with <= 32MB we need to lie
55 * about vram size near mc fb location */
56 u64 mc_vram_size;
57 u64 visible_vram_size;
58 u64 gart_size;
59 u64 gart_start;
60 u64 gart_end;
61 u64 vram_start;
62 u64 vram_end;
63 unsigned vram_width;
64 u64 real_vram_size;
65 int vram_mtrr;
66 u64 mc_mask;
67 const struct firmware *fw; /* MC firmware */
68 uint32_t fw_version;
69 struct amdgpu_irq_src vm_fault;
70 uint32_t vram_type;
71 uint32_t srbm_soft_reset;
72 bool prt_warning;
73 uint64_t stolen_size;
74 /* apertures */
75 u64 shared_aperture_start;
76 u64 shared_aperture_end;
77 u64 private_aperture_start;
78 u64 private_aperture_end;
79 /* protects concurrent invalidation */
80 spinlock_t invalidate_lock;
81 bool translate_further;
82};
83
84#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index e14ab34d8262..7abc1f3251ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -56,7 +56,7 @@ static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager *man,
56 return -ENOMEM; 56 return -ENOMEM;
57 57
58 start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS; 58 start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS;
59 size = (adev->mc.gart_size >> PAGE_SHIFT) - start; 59 size = (adev->gmc.gart_size >> PAGE_SHIFT) - start;
60 drm_mm_init(&mgr->mm, start, size); 60 drm_mm_init(&mgr->mm, start, size);
61 spin_lock_init(&mgr->lock); 61 spin_lock_init(&mgr->lock);
62 atomic64_set(&mgr->available, p_size); 62 atomic64_set(&mgr->available, p_size);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index bd6e9a40f421..2b077ccec181 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -191,7 +191,7 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
191 fw_info->feature = 0; 191 fw_info->feature = 0;
192 break; 192 break;
193 case AMDGPU_INFO_FW_GMC: 193 case AMDGPU_INFO_FW_GMC:
194 fw_info->ver = adev->mc.fw_version; 194 fw_info->ver = adev->gmc.fw_version;
195 fw_info->feature = 0; 195 fw_info->feature = 0;
196 break; 196 break;
197 case AMDGPU_INFO_FW_GFX_ME: 197 case AMDGPU_INFO_FW_GFX_ME:
@@ -470,9 +470,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
470 case AMDGPU_INFO_VRAM_GTT: { 470 case AMDGPU_INFO_VRAM_GTT: {
471 struct drm_amdgpu_info_vram_gtt vram_gtt; 471 struct drm_amdgpu_info_vram_gtt vram_gtt;
472 472
473 vram_gtt.vram_size = adev->mc.real_vram_size; 473 vram_gtt.vram_size = adev->gmc.real_vram_size;
474 vram_gtt.vram_size -= adev->vram_pin_size; 474 vram_gtt.vram_size -= adev->vram_pin_size;
475 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size; 475 vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size;
476 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size); 476 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
477 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size; 477 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
478 vram_gtt.gtt_size *= PAGE_SIZE; 478 vram_gtt.gtt_size *= PAGE_SIZE;
@@ -484,17 +484,17 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
484 struct drm_amdgpu_memory_info mem; 484 struct drm_amdgpu_memory_info mem;
485 485
486 memset(&mem, 0, sizeof(mem)); 486 memset(&mem, 0, sizeof(mem));
487 mem.vram.total_heap_size = adev->mc.real_vram_size; 487 mem.vram.total_heap_size = adev->gmc.real_vram_size;
488 mem.vram.usable_heap_size = 488 mem.vram.usable_heap_size =
489 adev->mc.real_vram_size - adev->vram_pin_size; 489 adev->gmc.real_vram_size - adev->vram_pin_size;
490 mem.vram.heap_usage = 490 mem.vram.heap_usage =
491 amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 491 amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
492 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 492 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
493 493
494 mem.cpu_accessible_vram.total_heap_size = 494 mem.cpu_accessible_vram.total_heap_size =
495 adev->mc.visible_vram_size; 495 adev->gmc.visible_vram_size;
496 mem.cpu_accessible_vram.usable_heap_size = 496 mem.cpu_accessible_vram.usable_heap_size =
497 adev->mc.visible_vram_size - 497 adev->gmc.visible_vram_size -
498 (adev->vram_pin_size - adev->invisible_pin_size); 498 (adev->vram_pin_size - adev->invisible_pin_size);
499 mem.cpu_accessible_vram.heap_usage = 499 mem.cpu_accessible_vram.heap_usage =
500 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 500 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
@@ -599,8 +599,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
599 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 599 sizeof(adev->gfx.cu_info.ao_cu_bitmap));
600 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 600 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
601 sizeof(adev->gfx.cu_info.bitmap)); 601 sizeof(adev->gfx.cu_info.bitmap));
602 dev_info.vram_type = adev->mc.vram_type; 602 dev_info.vram_type = adev->gmc.vram_type;
603 dev_info.vram_bit_width = adev->mc.vram_width; 603 dev_info.vram_bit_width = adev->gmc.vram_width;
604 dev_info.vce_harvest_config = adev->vce.harvest_config; 604 dev_info.vce_harvest_config = adev->vce.harvest_config;
605 dev_info.gc_double_offchip_lds_buf = 605 dev_info.gc_double_offchip_lds_buf =
606 adev->gfx.config.double_offchip_lds_buf; 606 adev->gfx.config.double_offchip_lds_buf;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 5c4c3e0d527b..f0a685340cd4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -83,7 +83,7 @@ void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
83 u32 c = 0; 83 u32 c = 0;
84 84
85 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 85 if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
86 unsigned visible_pfn = adev->mc.visible_vram_size >> PAGE_SHIFT; 86 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
87 87
88 places[c].fpfn = 0; 88 places[c].fpfn = 0;
89 places[c].lpfn = 0; 89 places[c].lpfn = 0;
@@ -103,7 +103,7 @@ void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
103 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 103 if (domain & AMDGPU_GEM_DOMAIN_GTT) {
104 places[c].fpfn = 0; 104 places[c].fpfn = 0;
105 if (flags & AMDGPU_GEM_CREATE_SHADOW) 105 if (flags & AMDGPU_GEM_CREATE_SHADOW)
106 places[c].lpfn = adev->mc.gart_size >> PAGE_SHIFT; 106 places[c].lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
107 else 107 else
108 places[c].lpfn = 0; 108 places[c].lpfn = 0;
109 places[c].flags = TTM_PL_FLAG_TT; 109 places[c].flags = TTM_PL_FLAG_TT;
@@ -428,9 +428,9 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
428 if (unlikely(r != 0)) 428 if (unlikely(r != 0))
429 return r; 429 return r;
430 430
431 if (adev->mc.visible_vram_size < adev->mc.real_vram_size && 431 if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
432 bo->tbo.mem.mem_type == TTM_PL_VRAM && 432 bo->tbo.mem.mem_type == TTM_PL_VRAM &&
433 bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT) 433 bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
434 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 434 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
435 ctx.bytes_moved); 435 ctx.bytes_moved);
436 else 436 else
@@ -832,25 +832,25 @@ static const char *amdgpu_vram_names[] = {
832int amdgpu_bo_init(struct amdgpu_device *adev) 832int amdgpu_bo_init(struct amdgpu_device *adev)
833{ 833{
834 /* reserve PAT memory space to WC for VRAM */ 834 /* reserve PAT memory space to WC for VRAM */
835 arch_io_reserve_memtype_wc(adev->mc.aper_base, 835 arch_io_reserve_memtype_wc(adev->gmc.aper_base,
836 adev->mc.aper_size); 836 adev->gmc.aper_size);
837 837
838 /* Add an MTRR for the VRAM */ 838 /* Add an MTRR for the VRAM */
839 adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base, 839 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
840 adev->mc.aper_size); 840 adev->gmc.aper_size);
841 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 841 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
842 adev->mc.mc_vram_size >> 20, 842 adev->gmc.mc_vram_size >> 20,
843 (unsigned long long)adev->mc.aper_size >> 20); 843 (unsigned long long)adev->gmc.aper_size >> 20);
844 DRM_INFO("RAM width %dbits %s\n", 844 DRM_INFO("RAM width %dbits %s\n",
845 adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]); 845 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
846 return amdgpu_ttm_init(adev); 846 return amdgpu_ttm_init(adev);
847} 847}
848 848
849void amdgpu_bo_fini(struct amdgpu_device *adev) 849void amdgpu_bo_fini(struct amdgpu_device *adev)
850{ 850{
851 amdgpu_ttm_fini(adev); 851 amdgpu_ttm_fini(adev);
852 arch_phys_wc_del(adev->mc.vram_mtrr); 852 arch_phys_wc_del(adev->gmc.vram_mtrr);
853 arch_io_free_memtype_wc(adev->mc.aper_base, adev->mc.aper_size); 853 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
854} 854}
855 855
856int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 856int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
@@ -980,7 +980,7 @@ int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
980 980
981 size = bo->mem.num_pages << PAGE_SHIFT; 981 size = bo->mem.num_pages << PAGE_SHIFT;
982 offset = bo->mem.start << PAGE_SHIFT; 982 offset = bo->mem.start << PAGE_SHIFT;
983 if ((offset + size) <= adev->mc.visible_vram_size) 983 if ((offset + size) <= adev->gmc.visible_vram_size)
984 return 0; 984 return 0;
985 985
986 /* Can't move a pinned BO to visible VRAM */ 986 /* Can't move a pinned BO to visible VRAM */
@@ -1003,7 +1003,7 @@ int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
1003 offset = bo->mem.start << PAGE_SHIFT; 1003 offset = bo->mem.start << PAGE_SHIFT;
1004 /* this should never happen */ 1004 /* this should never happen */
1005 if (bo->mem.mem_type == TTM_PL_VRAM && 1005 if (bo->mem.mem_type == TTM_PL_VRAM &&
1006 (offset + size) > adev->mc.visible_vram_size) 1006 (offset + size) > adev->gmc.visible_vram_size)
1007 return -EINVAL; 1007 return -EINVAL;
1008 1008
1009 return 0; 1009 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
index ed8c3739015b..30d84df20437 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
@@ -42,7 +42,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
42 /* Number of tests = 42 /* Number of tests =
43 * (Total GTT - IB pool - writeback page - ring buffers) / test size 43 * (Total GTT - IB pool - writeback page - ring buffers) / test size
44 */ 44 */
45 n = adev->mc.gart_size - AMDGPU_IB_POOL_SIZE*64*1024; 45 n = adev->gmc.gart_size - AMDGPU_IB_POOL_SIZE*64*1024;
46 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) 46 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
47 if (adev->rings[i]) 47 if (adev->rings[i])
48 n -= adev->rings[i]->ring_size; 48 n -= adev->rings[i]->ring_size;
@@ -142,10 +142,10 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
142 "0x%16llx/0x%16llx)\n", 142 "0x%16llx/0x%16llx)\n",
143 i, *vram_start, gart_start, 143 i, *vram_start, gart_start,
144 (unsigned long long) 144 (unsigned long long)
145 (gart_addr - adev->mc.gart_start + 145 (gart_addr - adev->gmc.gart_start +
146 (void*)gart_start - gtt_map), 146 (void*)gart_start - gtt_map),
147 (unsigned long long) 147 (unsigned long long)
148 (vram_addr - adev->mc.vram_start + 148 (vram_addr - adev->gmc.vram_start +
149 (void*)gart_start - gtt_map)); 149 (void*)gart_start - gtt_map));
150 amdgpu_bo_kunmap(vram_obj); 150 amdgpu_bo_kunmap(vram_obj);
151 goto out_lclean_unpin; 151 goto out_lclean_unpin;
@@ -187,10 +187,10 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
187 "0x%16llx/0x%16llx)\n", 187 "0x%16llx/0x%16llx)\n",
188 i, *gart_start, vram_start, 188 i, *gart_start, vram_start,
189 (unsigned long long) 189 (unsigned long long)
190 (vram_addr - adev->mc.vram_start + 190 (vram_addr - adev->gmc.vram_start +
191 (void*)vram_start - vram_map), 191 (void*)vram_start - vram_map),
192 (unsigned long long) 192 (unsigned long long)
193 (gart_addr - adev->mc.gart_start + 193 (gart_addr - adev->gmc.gart_start +
194 (void*)vram_start - vram_map)); 194 (void*)vram_start - vram_map));
195 amdgpu_bo_kunmap(gtt_obj[i]); 195 amdgpu_bo_kunmap(gtt_obj[i]);
196 goto out_lclean_unpin; 196 goto out_lclean_unpin;
@@ -200,7 +200,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
200 amdgpu_bo_kunmap(gtt_obj[i]); 200 amdgpu_bo_kunmap(gtt_obj[i]);
201 201
202 DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n", 202 DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n",
203 gart_addr - adev->mc.gart_start); 203 gart_addr - adev->gmc.gart_start);
204 continue; 204 continue;
205 205
206out_lclean_unpin: 206out_lclean_unpin:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index d897c4c61a01..828d13990354 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -161,7 +161,7 @@ static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
161 break; 161 break;
162 case TTM_PL_TT: 162 case TTM_PL_TT:
163 man->func = &amdgpu_gtt_mgr_func; 163 man->func = &amdgpu_gtt_mgr_func;
164 man->gpu_offset = adev->mc.gart_start; 164 man->gpu_offset = adev->gmc.gart_start;
165 man->available_caching = TTM_PL_MASK_CACHING; 165 man->available_caching = TTM_PL_MASK_CACHING;
166 man->default_caching = TTM_PL_FLAG_CACHED; 166 man->default_caching = TTM_PL_FLAG_CACHED;
167 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; 167 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
@@ -169,7 +169,7 @@ static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
169 case TTM_PL_VRAM: 169 case TTM_PL_VRAM:
170 /* "On-card" video ram */ 170 /* "On-card" video ram */
171 man->func = &amdgpu_vram_mgr_func; 171 man->func = &amdgpu_vram_mgr_func;
172 man->gpu_offset = adev->mc.vram_start; 172 man->gpu_offset = adev->gmc.vram_start;
173 man->flags = TTM_MEMTYPE_FLAG_FIXED | 173 man->flags = TTM_MEMTYPE_FLAG_FIXED |
174 TTM_MEMTYPE_FLAG_MAPPABLE; 174 TTM_MEMTYPE_FLAG_MAPPABLE;
175 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; 175 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
@@ -217,9 +217,9 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
217 adev->mman.buffer_funcs_ring && 217 adev->mman.buffer_funcs_ring &&
218 adev->mman.buffer_funcs_ring->ready == false) { 218 adev->mman.buffer_funcs_ring->ready == false) {
219 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 219 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
220 } else if (adev->mc.visible_vram_size < adev->mc.real_vram_size && 220 } else if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
221 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) { 221 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
222 unsigned fpfn = adev->mc.visible_vram_size >> PAGE_SHIFT; 222 unsigned fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
223 struct drm_mm_node *node = bo->mem.mm_node; 223 struct drm_mm_node *node = bo->mem.mm_node;
224 unsigned long pages_left; 224 unsigned long pages_left;
225 225
@@ -638,9 +638,9 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_
638 case TTM_PL_VRAM: 638 case TTM_PL_VRAM:
639 mem->bus.offset = mem->start << PAGE_SHIFT; 639 mem->bus.offset = mem->start << PAGE_SHIFT;
640 /* check if it's visible */ 640 /* check if it's visible */
641 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size) 641 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
642 return -EINVAL; 642 return -EINVAL;
643 mem->bus.base = adev->mc.aper_base; 643 mem->bus.base = adev->gmc.aper_base;
644 mem->bus.is_iomem = true; 644 mem->bus.is_iomem = true;
645 break; 645 break;
646 default: 646 default:
@@ -891,7 +891,7 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
891 placement.num_busy_placement = 1; 891 placement.num_busy_placement = 1;
892 placement.busy_placement = &placements; 892 placement.busy_placement = &placements;
893 placements.fpfn = 0; 893 placements.fpfn = 0;
894 placements.lpfn = adev->mc.gart_size >> PAGE_SHIFT; 894 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
895 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) | 895 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
896 TTM_PL_FLAG_TT; 896 TTM_PL_FLAG_TT;
897 897
@@ -1212,7 +1212,7 @@ static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1212 nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset); 1212 nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
1213 pos = (nodes->start << PAGE_SHIFT) + offset; 1213 pos = (nodes->start << PAGE_SHIFT) + offset;
1214 1214
1215 while (len && pos < adev->mc.mc_vram_size) { 1215 while (len && pos < adev->gmc.mc_vram_size) {
1216 uint64_t aligned_pos = pos & ~(uint64_t)3; 1216 uint64_t aligned_pos = pos & ~(uint64_t)3;
1217 uint32_t bytes = 4 - (pos & 3); 1217 uint32_t bytes = 4 - (pos & 3);
1218 uint32_t shift = (pos & 3) * 8; 1218 uint32_t shift = (pos & 3) * 8;
@@ -1298,7 +1298,7 @@ static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1298 struct ttm_operation_ctx ctx = { false, false }; 1298 struct ttm_operation_ctx ctx = { false, false };
1299 int r = 0; 1299 int r = 0;
1300 int i; 1300 int i;
1301 u64 vram_size = adev->mc.visible_vram_size; 1301 u64 vram_size = adev->gmc.visible_vram_size;
1302 u64 offset = adev->fw_vram_usage.start_offset; 1302 u64 offset = adev->fw_vram_usage.start_offset;
1303 u64 size = adev->fw_vram_usage.size; 1303 u64 size = adev->fw_vram_usage.size;
1304 struct amdgpu_bo *bo; 1304 struct amdgpu_bo *bo;
@@ -1388,7 +1388,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
1388 } 1388 }
1389 adev->mman.initialized = true; 1389 adev->mman.initialized = true;
1390 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM, 1390 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1391 adev->mc.real_vram_size >> PAGE_SHIFT); 1391 adev->gmc.real_vram_size >> PAGE_SHIFT);
1392 if (r) { 1392 if (r) {
1393 DRM_ERROR("Failed initializing VRAM heap.\n"); 1393 DRM_ERROR("Failed initializing VRAM heap.\n");
1394 return r; 1394 return r;
@@ -1397,11 +1397,11 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
1397 /* Reduce size of CPU-visible VRAM if requested */ 1397 /* Reduce size of CPU-visible VRAM if requested */
1398 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024; 1398 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1399 if (amdgpu_vis_vram_limit > 0 && 1399 if (amdgpu_vis_vram_limit > 0 &&
1400 vis_vram_limit <= adev->mc.visible_vram_size) 1400 vis_vram_limit <= adev->gmc.visible_vram_size)
1401 adev->mc.visible_vram_size = vis_vram_limit; 1401 adev->gmc.visible_vram_size = vis_vram_limit;
1402 1402
1403 /* Change the size here instead of the init above so only lpfn is affected */ 1403 /* Change the size here instead of the init above so only lpfn is affected */
1404 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 1404 amdgpu_ttm_set_active_vram_size(adev, adev->gmc.visible_vram_size);
1405 1405
1406 /* 1406 /*
1407 *The reserved vram for firmware must be pinned to the specified 1407 *The reserved vram for firmware must be pinned to the specified
@@ -1412,21 +1412,21 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
1412 return r; 1412 return r;
1413 } 1413 }
1414 1414
1415 r = amdgpu_bo_create_kernel(adev, adev->mc.stolen_size, PAGE_SIZE, 1415 r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1416 AMDGPU_GEM_DOMAIN_VRAM, 1416 AMDGPU_GEM_DOMAIN_VRAM,
1417 &adev->stolen_vga_memory, 1417 &adev->stolen_vga_memory,
1418 NULL, NULL); 1418 NULL, NULL);
1419 if (r) 1419 if (r)
1420 return r; 1420 return r;
1421 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1421 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1422 (unsigned) (adev->mc.real_vram_size / (1024 * 1024))); 1422 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1423 1423
1424 if (amdgpu_gtt_size == -1) { 1424 if (amdgpu_gtt_size == -1) {
1425 struct sysinfo si; 1425 struct sysinfo si;
1426 1426
1427 si_meminfo(&si); 1427 si_meminfo(&si);
1428 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), 1428 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1429 adev->mc.mc_vram_size), 1429 adev->gmc.mc_vram_size),
1430 ((uint64_t)si.totalram * si.mem_unit * 3/4)); 1430 ((uint64_t)si.totalram * si.mem_unit * 3/4));
1431 } 1431 }
1432 else 1432 else
@@ -1559,7 +1559,7 @@ static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1559 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 1559 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1560 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); 1560 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1561 1561
1562 *addr = adev->mc.gart_start; 1562 *addr = adev->gmc.gart_start;
1563 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 1563 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1564 AMDGPU_GPU_PAGE_SIZE; 1564 AMDGPU_GPU_PAGE_SIZE;
1565 1565
@@ -1811,14 +1811,14 @@ static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1811 if (size & 0x3 || *pos & 0x3) 1811 if (size & 0x3 || *pos & 0x3)
1812 return -EINVAL; 1812 return -EINVAL;
1813 1813
1814 if (*pos >= adev->mc.mc_vram_size) 1814 if (*pos >= adev->gmc.mc_vram_size)
1815 return -ENXIO; 1815 return -ENXIO;
1816 1816
1817 while (size) { 1817 while (size) {
1818 unsigned long flags; 1818 unsigned long flags;
1819 uint32_t value; 1819 uint32_t value;
1820 1820
1821 if (*pos >= adev->mc.mc_vram_size) 1821 if (*pos >= adev->gmc.mc_vram_size)
1822 return result; 1822 return result;
1823 1823
1824 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 1824 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
@@ -1850,14 +1850,14 @@ static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
1850 if (size & 0x3 || *pos & 0x3) 1850 if (size & 0x3 || *pos & 0x3)
1851 return -EINVAL; 1851 return -EINVAL;
1852 1852
1853 if (*pos >= adev->mc.mc_vram_size) 1853 if (*pos >= adev->gmc.mc_vram_size)
1854 return -ENXIO; 1854 return -ENXIO;
1855 1855
1856 while (size) { 1856 while (size) {
1857 unsigned long flags; 1857 unsigned long flags;
1858 uint32_t value; 1858 uint32_t value;
1859 1859
1860 if (*pos >= adev->mc.mc_vram_size) 1860 if (*pos >= adev->gmc.mc_vram_size)
1861 return result; 1861 return result;
1862 1862
1863 r = get_user(value, (uint32_t *)buf); 1863 r = get_user(value, (uint32_t *)buf);
@@ -2001,9 +2001,9 @@ static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2001 if (IS_ERR(ent)) 2001 if (IS_ERR(ent))
2002 return PTR_ERR(ent); 2002 return PTR_ERR(ent);
2003 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM) 2003 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2004 i_size_write(ent->d_inode, adev->mc.mc_vram_size); 2004 i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2005 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT) 2005 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2006 i_size_write(ent->d_inode, adev->mc.gart_size); 2006 i_size_write(ent->d_inode, adev->gmc.gart_size);
2007 adev->mman.debugfs_entries[count] = ent; 2007 adev->mman.debugfs_entries[count] = ent;
2008 } 2008 }
2009 2009
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 114571f29c7a..988ccb248b54 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -465,7 +465,7 @@ bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
465 465
466static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev) 466static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev)
467{ 467{
468 return (adev->mc.real_vram_size == adev->mc.visible_vram_size); 468 return (adev->gmc.real_vram_size == adev->gmc.visible_vram_size);
469} 469}
470 470
471/** 471/**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 4acca92f6a52..9aca653bec07 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -89,11 +89,11 @@ static u64 amdgpu_vram_mgr_vis_size(struct amdgpu_device *adev,
89 uint64_t start = node->start << PAGE_SHIFT; 89 uint64_t start = node->start << PAGE_SHIFT;
90 uint64_t end = (node->size + node->start) << PAGE_SHIFT; 90 uint64_t end = (node->size + node->start) << PAGE_SHIFT;
91 91
92 if (start >= adev->mc.visible_vram_size) 92 if (start >= adev->gmc.visible_vram_size)
93 return 0; 93 return 0;
94 94
95 return (end > adev->mc.visible_vram_size ? 95 return (end > adev->gmc.visible_vram_size ?
96 adev->mc.visible_vram_size : end) - start; 96 adev->gmc.visible_vram_size : end) - start;
97} 97}
98 98
99/** 99/**
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index a0943aa8d1d3..ab4523234f36 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -905,7 +905,7 @@ static bool ci_dpm_vblank_too_short(void *handle)
905{ 905{
906 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 906 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
907 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev); 907 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
908 u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300; 908 u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300;
909 909
910 /* disable mclk switching if the refresh is >120Hz, even if the 910 /* disable mclk switching if the refresh is >120Hz, even if the
911 * blanking period would allow it 911 * blanking period would allow it
@@ -2954,7 +2954,7 @@ static int ci_calculate_mclk_params(struct amdgpu_device *adev,
2954 mpll_ad_func_cntl &= ~MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK; 2954 mpll_ad_func_cntl &= ~MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK;
2955 mpll_ad_func_cntl |= (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT); 2955 mpll_ad_func_cntl |= (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
2956 2956
2957 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 2957 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
2958 mpll_dq_func_cntl &= ~(MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK | 2958 mpll_dq_func_cntl &= ~(MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK |
2959 MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK); 2959 MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK);
2960 mpll_dq_func_cntl |= (mpll_param.yclk_sel << MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT) | 2960 mpll_dq_func_cntl |= (mpll_param.yclk_sel << MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT) |
@@ -3077,7 +3077,7 @@ static int ci_populate_single_memory_level(struct amdgpu_device *adev,
3077 (memory_clock <= pi->mclk_strobe_mode_threshold)) 3077 (memory_clock <= pi->mclk_strobe_mode_threshold))
3078 memory_level->StrobeEnable = 1; 3078 memory_level->StrobeEnable = 1;
3079 3079
3080 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 3080 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
3081 memory_level->StrobeRatio = 3081 memory_level->StrobeRatio =
3082 ci_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable); 3082 ci_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
3083 if (pi->mclk_edc_enable_threshold && 3083 if (pi->mclk_edc_enable_threshold &&
@@ -3752,7 +3752,7 @@ static int ci_init_smc_table(struct amdgpu_device *adev)
3752 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 3752 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3753 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 3753 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3754 3754
3755 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 3755 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
3756 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 3756 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3757 3757
3758 if (ulv->supported) { 3758 if (ulv->supported) {
@@ -4549,12 +4549,12 @@ static int ci_set_mc_special_registers(struct amdgpu_device *adev,
4549 for (k = 0; k < table->num_entries; k++) { 4549 for (k = 0; k < table->num_entries; k++) {
4550 table->mc_reg_table_entry[k].mc_data[j] = 4550 table->mc_reg_table_entry[k].mc_data[j] =
4551 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 4551 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4552 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) 4552 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
4553 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 4553 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
4554 } 4554 }
4555 j++; 4555 j++;
4556 4556
4557 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) { 4557 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
4558 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4558 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4559 return -EINVAL; 4559 return -EINVAL;
4560 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; 4560 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 6e8278e689b1..1836ae1b7505 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -317,7 +317,7 @@ static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
317 317
318 if ((adev->mman.buffer_funcs_ring == sdma0) || 318 if ((adev->mman.buffer_funcs_ring == sdma0) ||
319 (adev->mman.buffer_funcs_ring == sdma1)) 319 (adev->mman.buffer_funcs_ring == sdma1))
320 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 320 amdgpu_ttm_set_active_vram_size(adev, adev->gmc.visible_vram_size);
321 321
322 for (i = 0; i < adev->sdma.num_instances; i++) { 322 for (i = 0; i < adev->sdma.num_instances; i++) {
323 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 323 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
@@ -517,7 +517,7 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
517 } 517 }
518 518
519 if (adev->mman.buffer_funcs_ring == ring) 519 if (adev->mman.buffer_funcs_ring == ring)
520 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); 520 amdgpu_ttm_set_active_vram_size(adev, adev->gmc.real_vram_size);
521 } 521 }
522 522
523 return 0; 523 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index f34bc68aadfb..5590bf15a05d 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -2824,7 +2824,7 @@ static int dce_v10_0_sw_init(void *handle)
2824 adev->ddev->mode_config.preferred_depth = 24; 2824 adev->ddev->mode_config.preferred_depth = 24;
2825 adev->ddev->mode_config.prefer_shadow = 1; 2825 adev->ddev->mode_config.prefer_shadow = 1;
2826 2826
2827 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 2827 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2828 2828
2829 r = amdgpu_modeset_create_props(adev); 2829 r = amdgpu_modeset_create_props(adev);
2830 if (r) 2830 if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 26378bd6aba4..8ee4fc47ea63 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -2939,7 +2939,7 @@ static int dce_v11_0_sw_init(void *handle)
2939 adev->ddev->mode_config.preferred_depth = 24; 2939 adev->ddev->mode_config.preferred_depth = 24;
2940 adev->ddev->mode_config.prefer_shadow = 1; 2940 adev->ddev->mode_config.prefer_shadow = 1;
2941 2941
2942 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 2942 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2943 2943
2944 r = amdgpu_modeset_create_props(adev); 2944 r = amdgpu_modeset_create_props(adev);
2945 if (r) 2945 if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index bd2c4f727df6..c943ad19eed5 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -2693,7 +2693,7 @@ static int dce_v6_0_sw_init(void *handle)
2693 adev->ddev->mode_config.max_height = 16384; 2693 adev->ddev->mode_config.max_height = 16384;
2694 adev->ddev->mode_config.preferred_depth = 24; 2694 adev->ddev->mode_config.preferred_depth = 24;
2695 adev->ddev->mode_config.prefer_shadow = 1; 2695 adev->ddev->mode_config.prefer_shadow = 1;
2696 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 2696 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2697 2697
2698 r = amdgpu_modeset_create_props(adev); 2698 r = amdgpu_modeset_create_props(adev);
2699 if (r) 2699 if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index c008dc030687..c02308c7e3da 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -2724,7 +2724,7 @@ static int dce_v8_0_sw_init(void *handle)
2724 adev->ddev->mode_config.preferred_depth = 24; 2724 adev->ddev->mode_config.preferred_depth = 24;
2725 adev->ddev->mode_config.prefer_shadow = 1; 2725 adev->ddev->mode_config.prefer_shadow = 1;
2726 2726
2727 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 2727 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2728 2728
2729 r = amdgpu_modeset_create_props(adev); 2729 r = amdgpu_modeset_create_props(adev);
2730 if (r) 2730 if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index 120dd3b26fc2..695b600b5c21 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -406,7 +406,7 @@ static int dce_virtual_sw_init(void *handle)
406 adev->ddev->mode_config.preferred_depth = 24; 406 adev->ddev->mode_config.preferred_depth = 24;
407 adev->ddev->mode_config.prefer_shadow = 1; 407 adev->ddev->mode_config.prefer_shadow = 1;
408 408
409 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 409 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
410 410
411 r = amdgpu_modeset_create_props(adev); 411 r = amdgpu_modeset_create_props(adev);
412 if (r) 412 if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index a066c5eda135..133245cd31ae 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -1946,7 +1946,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
1946 if (i == 0) 1946 if (i == 0)
1947 sh_mem_base = 0; 1947 sh_mem_base = 0;
1948 else 1948 else
1949 sh_mem_base = adev->mc.shared_aperture_start >> 48; 1949 sh_mem_base = adev->gmc.shared_aperture_start >> 48;
1950 cik_srbm_select(adev, 0, 0, 0, i); 1950 cik_srbm_select(adev, 0, 0, 0, i);
1951 /* CP and shaders */ 1951 /* CP and shaders */
1952 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg); 1952 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 4e694ae9f308..a4820edb1fdf 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3796,7 +3796,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
3796 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, 3796 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
3797 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 3797 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
3798 WREG32(mmSH_MEM_CONFIG, tmp); 3798 WREG32(mmSH_MEM_CONFIG, tmp);
3799 tmp = adev->mc.shared_aperture_start >> 48; 3799 tmp = adev->gmc.shared_aperture_start >> 48;
3800 WREG32(mmSH_MEM_BASES, tmp); 3800 WREG32(mmSH_MEM_BASES, tmp);
3801 } 3801 }
3802 3802
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ee5464b43e9e..59928b7e741d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1539,7 +1539,7 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1539 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1539 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1540 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1540 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1541 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); 1541 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1542 tmp = adev->mc.shared_aperture_start >> 48; 1542 tmp = adev->gmc.shared_aperture_start >> 48;
1543 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 1543 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1544 } 1544 }
1545 } 1545 }
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 56f5fe4e2fee..94a07bcbbdda 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -40,7 +40,7 @@ static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
40 uint64_t value; 40 uint64_t value;
41 41
42 BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); 42 BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
43 value = adev->gart.table_addr - adev->mc.vram_start 43 value = adev->gart.table_addr - adev->gmc.vram_start
44 + adev->vm_manager.vram_base_offset; 44 + adev->vm_manager.vram_base_offset;
45 value &= 0x0000FFFFFFFFF000ULL; 45 value &= 0x0000FFFFFFFFF000ULL;
46 value |= 0x1; /*valid bit*/ 46 value |= 0x1; /*valid bit*/
@@ -57,14 +57,14 @@ static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
57 gfxhub_v1_0_init_gart_pt_regs(adev); 57 gfxhub_v1_0_init_gart_pt_regs(adev);
58 58
59 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 59 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
60 (u32)(adev->mc.gart_start >> 12)); 60 (u32)(adev->gmc.gart_start >> 12));
61 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 61 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
62 (u32)(adev->mc.gart_start >> 44)); 62 (u32)(adev->gmc.gart_start >> 44));
63 63
64 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 64 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
65 (u32)(adev->mc.gart_end >> 12)); 65 (u32)(adev->gmc.gart_end >> 12));
66 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 66 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
67 (u32)(adev->mc.gart_end >> 44)); 67 (u32)(adev->gmc.gart_end >> 44));
68} 68}
69 69
70static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 70static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
@@ -78,12 +78,12 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
78 78
79 /* Program the system aperture low logical page number. */ 79 /* Program the system aperture low logical page number. */
80 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 80 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
81 adev->mc.vram_start >> 18); 81 adev->gmc.vram_start >> 18);
82 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 82 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
83 adev->mc.vram_end >> 18); 83 adev->gmc.vram_end >> 18);
84 84
85 /* Set default page address. */ 85 /* Set default page address. */
86 value = adev->vram_scratch.gpu_addr - adev->mc.vram_start 86 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
87 + adev->vm_manager.vram_base_offset; 87 + adev->vm_manager.vram_base_offset;
88 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 88 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
89 (u32)(value >> 12)); 89 (u32)(value >> 12));
@@ -143,7 +143,7 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
143 WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp); 143 WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);
144 144
145 tmp = mmVM_L2_CNTL3_DEFAULT; 145 tmp = mmVM_L2_CNTL3_DEFAULT;
146 if (adev->mc.translate_further) { 146 if (adev->gmc.translate_further) {
147 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); 147 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
148 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 148 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
149 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 149 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
@@ -195,7 +195,7 @@ static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
195 195
196 num_level = adev->vm_manager.num_level; 196 num_level = adev->vm_manager.num_level;
197 block_size = adev->vm_manager.block_size; 197 block_size = adev->vm_manager.block_size;
198 if (adev->mc.translate_further) 198 if (adev->gmc.translate_further)
199 num_level -= 1; 199 num_level -= 1;
200 else 200 else
201 block_size -= 9; 201 block_size -= 9;
@@ -257,9 +257,9 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
257 * SRIOV driver need to program them 257 * SRIOV driver need to program them
258 */ 258 */
259 WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 259 WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE,
260 adev->mc.vram_start >> 24); 260 adev->gmc.vram_start >> 24);
261 WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 261 WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP,
262 adev->mc.vram_end >> 24); 262 adev->gmc.vram_end >> 24);
263 } 263 }
264 264
265 /* GART Enable. */ 265 /* GART Enable. */
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index aa06e7232d29..98411e3479f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -137,19 +137,19 @@ static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
137 snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin"); 137 snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin");
138 else 138 else
139 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); 139 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
140 err = request_firmware(&adev->mc.fw, fw_name, adev->dev); 140 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
141 if (err) 141 if (err)
142 goto out; 142 goto out;
143 143
144 err = amdgpu_ucode_validate(adev->mc.fw); 144 err = amdgpu_ucode_validate(adev->gmc.fw);
145 145
146out: 146out:
147 if (err) { 147 if (err) {
148 dev_err(adev->dev, 148 dev_err(adev->dev,
149 "si_mc: Failed to load firmware \"%s\"\n", 149 "si_mc: Failed to load firmware \"%s\"\n",
150 fw_name); 150 fw_name);
151 release_firmware(adev->mc.fw); 151 release_firmware(adev->gmc.fw);
152 adev->mc.fw = NULL; 152 adev->gmc.fw = NULL;
153 } 153 }
154 return err; 154 return err;
155} 155}
@@ -162,20 +162,20 @@ static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
162 int i, regs_size, ucode_size; 162 int i, regs_size, ucode_size;
163 const struct mc_firmware_header_v1_0 *hdr; 163 const struct mc_firmware_header_v1_0 *hdr;
164 164
165 if (!adev->mc.fw) 165 if (!adev->gmc.fw)
166 return -EINVAL; 166 return -EINVAL;
167 167
168 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; 168 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
169 169
170 amdgpu_ucode_print_mc_hdr(&hdr->header); 170 amdgpu_ucode_print_mc_hdr(&hdr->header);
171 171
172 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); 172 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
173 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 173 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
174 new_io_mc_regs = (const __le32 *) 174 new_io_mc_regs = (const __le32 *)
175 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 175 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
176 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 176 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
177 new_fw_data = (const __le32 *) 177 new_fw_data = (const __le32 *)
178 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 178 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
179 179
180 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; 180 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
181 181
@@ -218,12 +218,12 @@ static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
218} 218}
219 219
220static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev, 220static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
221 struct amdgpu_mc *mc) 221 struct amdgpu_gmc *mc)
222{ 222{
223 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 223 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
224 base <<= 24; 224 base <<= 24;
225 225
226 amdgpu_device_vram_location(adev, &adev->mc, base); 226 amdgpu_device_vram_location(adev, &adev->gmc, base);
227 amdgpu_device_gart_location(adev, mc); 227 amdgpu_device_gart_location(adev, mc);
228} 228}
229 229
@@ -260,9 +260,9 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
260 } 260 }
261 /* Update configuration */ 261 /* Update configuration */
262 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 262 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
263 adev->mc.vram_start >> 12); 263 adev->gmc.vram_start >> 12);
264 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 264 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
265 adev->mc.vram_end >> 12); 265 adev->gmc.vram_end >> 12);
266 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 266 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
267 adev->vram_scratch.gpu_addr >> 12); 267 adev->vram_scratch.gpu_addr >> 12);
268 WREG32(mmMC_VM_AGP_BASE, 0); 268 WREG32(mmMC_VM_AGP_BASE, 0);
@@ -320,39 +320,39 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
320 numchan = 16; 320 numchan = 16;
321 break; 321 break;
322 } 322 }
323 adev->mc.vram_width = numchan * chansize; 323 adev->gmc.vram_width = numchan * chansize;
324 /* size in MB on si */ 324 /* size in MB on si */
325 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 325 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
326 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 326 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
327 327
328 if (!(adev->flags & AMD_IS_APU)) { 328 if (!(adev->flags & AMD_IS_APU)) {
329 r = amdgpu_device_resize_fb_bar(adev); 329 r = amdgpu_device_resize_fb_bar(adev);
330 if (r) 330 if (r)
331 return r; 331 return r;
332 } 332 }
333 adev->mc.aper_base = pci_resource_start(adev->pdev, 0); 333 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
334 adev->mc.aper_size = pci_resource_len(adev->pdev, 0); 334 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
335 adev->mc.visible_vram_size = adev->mc.aper_size; 335 adev->gmc.visible_vram_size = adev->gmc.aper_size;
336 336
337 /* set the gart size */ 337 /* set the gart size */
338 if (amdgpu_gart_size == -1) { 338 if (amdgpu_gart_size == -1) {
339 switch (adev->asic_type) { 339 switch (adev->asic_type) {
340 case CHIP_HAINAN: /* no MM engines */ 340 case CHIP_HAINAN: /* no MM engines */
341 default: 341 default:
342 adev->mc.gart_size = 256ULL << 20; 342 adev->gmc.gart_size = 256ULL << 20;
343 break; 343 break;
344 case CHIP_VERDE: /* UVD, VCE do not support GPUVM */ 344 case CHIP_VERDE: /* UVD, VCE do not support GPUVM */
345 case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */ 345 case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */
346 case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */ 346 case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
347 case CHIP_OLAND: /* UVD, VCE do not support GPUVM */ 347 case CHIP_OLAND: /* UVD, VCE do not support GPUVM */
348 adev->mc.gart_size = 1024ULL << 20; 348 adev->gmc.gart_size = 1024ULL << 20;
349 break; 349 break;
350 } 350 }
351 } else { 351 } else {
352 adev->mc.gart_size = (u64)amdgpu_gart_size << 20; 352 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
353 } 353 }
354 354
355 gmc_v6_0_vram_gtt_location(adev, &adev->mc); 355 gmc_v6_0_vram_gtt_location(adev, &adev->gmc);
356 356
357 return 0; 357 return 0;
358} 358}
@@ -431,9 +431,9 @@ static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
431{ 431{
432 u32 tmp; 432 u32 tmp;
433 433
434 if (enable && !adev->mc.prt_warning) { 434 if (enable && !adev->gmc.prt_warning) {
435 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 435 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
436 adev->mc.prt_warning = true; 436 adev->gmc.prt_warning = true;
437 } 437 }
438 438
439 tmp = RREG32(mmVM_PRT_CNTL); 439 tmp = RREG32(mmVM_PRT_CNTL);
@@ -513,8 +513,8 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
513 (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) | 513 (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
514 (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); 514 (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
515 /* setup context0 */ 515 /* setup context0 */
516 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12); 516 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
517 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12); 517 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
518 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); 518 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
519 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 519 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
520 (u32)(adev->dummy_page.addr >> 12)); 520 (u32)(adev->dummy_page.addr >> 12));
@@ -561,7 +561,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
561 561
562 gmc_v6_0_gart_flush_gpu_tlb(adev, 0); 562 gmc_v6_0_gart_flush_gpu_tlb(adev, 0);
563 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", 563 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
564 (unsigned)(adev->mc.gart_size >> 20), 564 (unsigned)(adev->gmc.gart_size >> 20),
565 (unsigned long long)adev->gart.table_addr); 565 (unsigned long long)adev->gart.table_addr);
566 adev->gart.ready = true; 566 adev->gart.ready = true;
567 return 0; 567 return 0;
@@ -804,7 +804,7 @@ static int gmc_v6_0_late_init(void *handle)
804 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 804 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
805 805
806 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 806 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
807 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 807 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
808 else 808 else
809 return 0; 809 return 0;
810} 810}
@@ -816,26 +816,26 @@ static int gmc_v6_0_sw_init(void *handle)
816 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 816 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
817 817
818 if (adev->flags & AMD_IS_APU) { 818 if (adev->flags & AMD_IS_APU) {
819 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 819 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
820 } else { 820 } else {
821 u32 tmp = RREG32(mmMC_SEQ_MISC0); 821 u32 tmp = RREG32(mmMC_SEQ_MISC0);
822 tmp &= MC_SEQ_MISC0__MT__MASK; 822 tmp &= MC_SEQ_MISC0__MT__MASK;
823 adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp); 823 adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp);
824 } 824 }
825 825
826 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault); 826 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
827 if (r) 827 if (r)
828 return r; 828 return r;
829 829
830 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault); 830 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
831 if (r) 831 if (r)
832 return r; 832 return r;
833 833
834 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 834 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
835 835
836 adev->mc.mc_mask = 0xffffffffffULL; 836 adev->gmc.mc_mask = 0xffffffffffULL;
837 837
838 adev->mc.stolen_size = 256 * 1024; 838 adev->gmc.stolen_size = 256 * 1024;
839 839
840 adev->need_dma32 = false; 840 adev->need_dma32 = false;
841 dma_bits = adev->need_dma32 ? 32 : 40; 841 dma_bits = adev->need_dma32 ? 32 : 40;
@@ -900,8 +900,8 @@ static int gmc_v6_0_sw_fini(void *handle)
900 amdgpu_vm_manager_fini(adev); 900 amdgpu_vm_manager_fini(adev);
901 gmc_v6_0_gart_fini(adev); 901 gmc_v6_0_gart_fini(adev);
902 amdgpu_bo_fini(adev); 902 amdgpu_bo_fini(adev);
903 release_firmware(adev->mc.fw); 903 release_firmware(adev->gmc.fw);
904 adev->mc.fw = NULL; 904 adev->gmc.fw = NULL;
905 905
906 return 0; 906 return 0;
907} 907}
@@ -932,7 +932,7 @@ static int gmc_v6_0_hw_fini(void *handle)
932{ 932{
933 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 933 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
934 934
935 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); 935 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
936 gmc_v6_0_gart_disable(adev); 936 gmc_v6_0_gart_disable(adev);
937 937
938 return 0; 938 return 0;
@@ -1148,8 +1148,8 @@ static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev)
1148 1148
1149static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1149static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1150{ 1150{
1151 adev->mc.vm_fault.num_types = 1; 1151 adev->gmc.vm_fault.num_types = 1;
1152 adev->mc.vm_fault.funcs = &gmc_v6_0_irq_funcs; 1152 adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1153} 1153}
1154 1154
1155const struct amdgpu_ip_block_version gmc_v6_0_ip_block = 1155const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index f214672dc493..71986cddcbcc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -152,16 +152,16 @@ static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
152 else 152 else
153 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); 153 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
154 154
155 err = request_firmware(&adev->mc.fw, fw_name, adev->dev); 155 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
156 if (err) 156 if (err)
157 goto out; 157 goto out;
158 err = amdgpu_ucode_validate(adev->mc.fw); 158 err = amdgpu_ucode_validate(adev->gmc.fw);
159 159
160out: 160out:
161 if (err) { 161 if (err) {
162 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name); 162 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name);
163 release_firmware(adev->mc.fw); 163 release_firmware(adev->gmc.fw);
164 adev->mc.fw = NULL; 164 adev->gmc.fw = NULL;
165 } 165 }
166 return err; 166 return err;
167} 167}
@@ -182,19 +182,19 @@ static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
182 u32 running; 182 u32 running;
183 int i, ucode_size, regs_size; 183 int i, ucode_size, regs_size;
184 184
185 if (!adev->mc.fw) 185 if (!adev->gmc.fw)
186 return -EINVAL; 186 return -EINVAL;
187 187
188 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; 188 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
189 amdgpu_ucode_print_mc_hdr(&hdr->header); 189 amdgpu_ucode_print_mc_hdr(&hdr->header);
190 190
191 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); 191 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
192 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 192 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
193 io_mc_regs = (const __le32 *) 193 io_mc_regs = (const __le32 *)
194 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 194 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
195 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 195 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
196 fw_data = (const __le32 *) 196 fw_data = (const __le32 *)
197 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 197 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
198 198
199 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 199 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
200 200
@@ -236,12 +236,12 @@ static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
236} 236}
237 237
238static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, 238static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
239 struct amdgpu_mc *mc) 239 struct amdgpu_gmc *mc)
240{ 240{
241 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 241 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
242 base <<= 24; 242 base <<= 24;
243 243
244 amdgpu_device_vram_location(adev, &adev->mc, base); 244 amdgpu_device_vram_location(adev, &adev->gmc, base);
245 amdgpu_device_gart_location(adev, mc); 245 amdgpu_device_gart_location(adev, mc);
246} 246}
247 247
@@ -284,9 +284,9 @@ static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
284 } 284 }
285 /* Update configuration */ 285 /* Update configuration */
286 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 286 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
287 adev->mc.vram_start >> 12); 287 adev->gmc.vram_start >> 12);
288 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 288 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
289 adev->mc.vram_end >> 12); 289 adev->gmc.vram_end >> 12);
290 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 290 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
291 adev->vram_scratch.gpu_addr >> 12); 291 adev->vram_scratch.gpu_addr >> 12);
292 WREG32(mmMC_VM_AGP_BASE, 0); 292 WREG32(mmMC_VM_AGP_BASE, 0);
@@ -319,8 +319,8 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
319{ 319{
320 int r; 320 int r;
321 321
322 adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev); 322 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
323 if (!adev->mc.vram_width) { 323 if (!adev->gmc.vram_width) {
324 u32 tmp; 324 u32 tmp;
325 int chansize, numchan; 325 int chansize, numchan;
326 326
@@ -362,38 +362,38 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
362 numchan = 16; 362 numchan = 16;
363 break; 363 break;
364 } 364 }
365 adev->mc.vram_width = numchan * chansize; 365 adev->gmc.vram_width = numchan * chansize;
366 } 366 }
367 /* size in MB on si */ 367 /* size in MB on si */
368 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 368 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
369 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 369 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
370 370
371 if (!(adev->flags & AMD_IS_APU)) { 371 if (!(adev->flags & AMD_IS_APU)) {
372 r = amdgpu_device_resize_fb_bar(adev); 372 r = amdgpu_device_resize_fb_bar(adev);
373 if (r) 373 if (r)
374 return r; 374 return r;
375 } 375 }
376 adev->mc.aper_base = pci_resource_start(adev->pdev, 0); 376 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
377 adev->mc.aper_size = pci_resource_len(adev->pdev, 0); 377 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
378 378
379#ifdef CONFIG_X86_64 379#ifdef CONFIG_X86_64
380 if (adev->flags & AMD_IS_APU) { 380 if (adev->flags & AMD_IS_APU) {
381 adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 381 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
382 adev->mc.aper_size = adev->mc.real_vram_size; 382 adev->gmc.aper_size = adev->gmc.real_vram_size;
383 } 383 }
384#endif 384#endif
385 385
386 /* In case the PCI BAR is larger than the actual amount of vram */ 386 /* In case the PCI BAR is larger than the actual amount of vram */
387 adev->mc.visible_vram_size = adev->mc.aper_size; 387 adev->gmc.visible_vram_size = adev->gmc.aper_size;
388 if (adev->mc.visible_vram_size > adev->mc.real_vram_size) 388 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
389 adev->mc.visible_vram_size = adev->mc.real_vram_size; 389 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
390 390
391 /* set the gart size */ 391 /* set the gart size */
392 if (amdgpu_gart_size == -1) { 392 if (amdgpu_gart_size == -1) {
393 switch (adev->asic_type) { 393 switch (adev->asic_type) {
394 case CHIP_TOPAZ: /* no MM engines */ 394 case CHIP_TOPAZ: /* no MM engines */
395 default: 395 default:
396 adev->mc.gart_size = 256ULL << 20; 396 adev->gmc.gart_size = 256ULL << 20;
397 break; 397 break;
398#ifdef CONFIG_DRM_AMDGPU_CIK 398#ifdef CONFIG_DRM_AMDGPU_CIK
399 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */ 399 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
@@ -401,15 +401,15 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
401 case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */ 401 case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */
402 case CHIP_KABINI: /* UVD, VCE do not support GPUVM */ 402 case CHIP_KABINI: /* UVD, VCE do not support GPUVM */
403 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */ 403 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */
404 adev->mc.gart_size = 1024ULL << 20; 404 adev->gmc.gart_size = 1024ULL << 20;
405 break; 405 break;
406#endif 406#endif
407 } 407 }
408 } else { 408 } else {
409 adev->mc.gart_size = (u64)amdgpu_gart_size << 20; 409 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
410 } 410 }
411 411
412 gmc_v7_0_vram_gtt_location(adev, &adev->mc); 412 gmc_v7_0_vram_gtt_location(adev, &adev->gmc);
413 413
414 return 0; 414 return 0;
415} 415}
@@ -521,9 +521,9 @@ static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
521{ 521{
522 uint32_t tmp; 522 uint32_t tmp;
523 523
524 if (enable && !adev->mc.prt_warning) { 524 if (enable && !adev->gmc.prt_warning) {
525 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 525 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
526 adev->mc.prt_warning = true; 526 adev->gmc.prt_warning = true;
527 } 527 }
528 528
529 tmp = RREG32(mmVM_PRT_CNTL); 529 tmp = RREG32(mmVM_PRT_CNTL);
@@ -619,8 +619,8 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
619 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 619 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
620 WREG32(mmVM_L2_CNTL3, tmp); 620 WREG32(mmVM_L2_CNTL3, tmp);
621 /* setup context0 */ 621 /* setup context0 */
622 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12); 622 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
623 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12); 623 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
624 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); 624 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
625 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 625 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
626 (u32)(adev->dummy_page.addr >> 12)); 626 (u32)(adev->dummy_page.addr >> 12));
@@ -674,7 +674,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
674 674
675 gmc_v7_0_gart_flush_gpu_tlb(adev, 0); 675 gmc_v7_0_gart_flush_gpu_tlb(adev, 0);
676 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 676 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
677 (unsigned)(adev->mc.gart_size >> 20), 677 (unsigned)(adev->gmc.gart_size >> 20),
678 (unsigned long long)adev->gart.table_addr); 678 (unsigned long long)adev->gart.table_addr);
679 adev->gart.ready = true; 679 adev->gart.ready = true;
680 return 0; 680 return 0;
@@ -922,13 +922,13 @@ static int gmc_v7_0_early_init(void *handle)
922 gmc_v7_0_set_gart_funcs(adev); 922 gmc_v7_0_set_gart_funcs(adev);
923 gmc_v7_0_set_irq_funcs(adev); 923 gmc_v7_0_set_irq_funcs(adev);
924 924
925 adev->mc.shared_aperture_start = 0x2000000000000000ULL; 925 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
926 adev->mc.shared_aperture_end = 926 adev->gmc.shared_aperture_end =
927 adev->mc.shared_aperture_start + (4ULL << 30) - 1; 927 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
928 adev->mc.private_aperture_start = 928 adev->gmc.private_aperture_start =
929 adev->mc.shared_aperture_end + 1; 929 adev->gmc.shared_aperture_end + 1;
930 adev->mc.private_aperture_end = 930 adev->gmc.private_aperture_end =
931 adev->mc.private_aperture_start + (4ULL << 30) - 1; 931 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
932 932
933 return 0; 933 return 0;
934} 934}
@@ -938,7 +938,7 @@ static int gmc_v7_0_late_init(void *handle)
938 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 938 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
939 939
940 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 940 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
941 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 941 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
942 else 942 else
943 return 0; 943 return 0;
944} 944}
@@ -950,18 +950,18 @@ static int gmc_v7_0_sw_init(void *handle)
950 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 950 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
951 951
952 if (adev->flags & AMD_IS_APU) { 952 if (adev->flags & AMD_IS_APU) {
953 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 953 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
954 } else { 954 } else {
955 u32 tmp = RREG32(mmMC_SEQ_MISC0); 955 u32 tmp = RREG32(mmMC_SEQ_MISC0);
956 tmp &= MC_SEQ_MISC0__MT__MASK; 956 tmp &= MC_SEQ_MISC0__MT__MASK;
957 adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp); 957 adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp);
958 } 958 }
959 959
960 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault); 960 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
961 if (r) 961 if (r)
962 return r; 962 return r;
963 963
964 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault); 964 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
965 if (r) 965 if (r)
966 return r; 966 return r;
967 967
@@ -975,9 +975,9 @@ static int gmc_v7_0_sw_init(void *handle)
975 * This is the max address of the GPU's 975 * This is the max address of the GPU's
976 * internal address space. 976 * internal address space.
977 */ 977 */
978 adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 978 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
979 979
980 adev->mc.stolen_size = 256 * 1024; 980 adev->gmc.stolen_size = 256 * 1024;
981 981
982 /* set DMA mask + need_dma32 flags. 982 /* set DMA mask + need_dma32 flags.
983 * PCIE - can handle 40-bits. 983 * PCIE - can handle 40-bits.
@@ -1048,8 +1048,8 @@ static int gmc_v7_0_sw_fini(void *handle)
1048 amdgpu_vm_manager_fini(adev); 1048 amdgpu_vm_manager_fini(adev);
1049 gmc_v7_0_gart_fini(adev); 1049 gmc_v7_0_gart_fini(adev);
1050 amdgpu_bo_fini(adev); 1050 amdgpu_bo_fini(adev);
1051 release_firmware(adev->mc.fw); 1051 release_firmware(adev->gmc.fw);
1052 adev->mc.fw = NULL; 1052 adev->gmc.fw = NULL;
1053 1053
1054 return 0; 1054 return 0;
1055} 1055}
@@ -1082,7 +1082,7 @@ static int gmc_v7_0_hw_fini(void *handle)
1082{ 1082{
1083 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1083 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1084 1084
1085 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); 1085 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1086 gmc_v7_0_gart_disable(adev); 1086 gmc_v7_0_gart_disable(adev);
1087 1087
1088 return 0; 1088 return 0;
@@ -1327,8 +1327,8 @@ static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev)
1327 1327
1328static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1328static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1329{ 1329{
1330 adev->mc.vm_fault.num_types = 1; 1330 adev->gmc.vm_fault.num_types = 1;
1331 adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs; 1331 adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1332} 1332}
1333 1333
1334const struct amdgpu_ip_block_version gmc_v7_0_ip_block = 1334const struct amdgpu_ip_block_version gmc_v7_0_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 8dd3dc59cb9f..7a021c6fb0bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -236,16 +236,16 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
236 } 236 }
237 237
238 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 238 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
239 err = request_firmware(&adev->mc.fw, fw_name, adev->dev); 239 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
240 if (err) 240 if (err)
241 goto out; 241 goto out;
242 err = amdgpu_ucode_validate(adev->mc.fw); 242 err = amdgpu_ucode_validate(adev->gmc.fw);
243 243
244out: 244out:
245 if (err) { 245 if (err) {
246 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name); 246 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
247 release_firmware(adev->mc.fw); 247 release_firmware(adev->gmc.fw);
248 adev->mc.fw = NULL; 248 adev->gmc.fw = NULL;
249 } 249 }
250 return err; 250 return err;
251} 251}
@@ -274,19 +274,19 @@ static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
274 if (amdgpu_sriov_bios(adev)) 274 if (amdgpu_sriov_bios(adev))
275 return 0; 275 return 0;
276 276
277 if (!adev->mc.fw) 277 if (!adev->gmc.fw)
278 return -EINVAL; 278 return -EINVAL;
279 279
280 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; 280 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
281 amdgpu_ucode_print_mc_hdr(&hdr->header); 281 amdgpu_ucode_print_mc_hdr(&hdr->header);
282 282
283 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); 283 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
284 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 284 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
285 io_mc_regs = (const __le32 *) 285 io_mc_regs = (const __le32 *)
286 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 286 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
287 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 287 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
288 fw_data = (const __le32 *) 288 fw_data = (const __le32 *)
289 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 289 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
290 290
291 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 291 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
292 292
@@ -350,19 +350,19 @@ static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
350 if (vbios_version == 0) 350 if (vbios_version == 0)
351 return 0; 351 return 0;
352 352
353 if (!adev->mc.fw) 353 if (!adev->gmc.fw)
354 return -EINVAL; 354 return -EINVAL;
355 355
356 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; 356 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
357 amdgpu_ucode_print_mc_hdr(&hdr->header); 357 amdgpu_ucode_print_mc_hdr(&hdr->header);
358 358
359 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); 359 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
360 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 360 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
361 io_mc_regs = (const __le32 *) 361 io_mc_regs = (const __le32 *)
362 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 362 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
363 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 363 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
364 fw_data = (const __le32 *) 364 fw_data = (const __le32 *)
365 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 365 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
366 366
367 data = RREG32(mmMC_SEQ_MISC0); 367 data = RREG32(mmMC_SEQ_MISC0);
368 data &= ~(0x40); 368 data &= ~(0x40);
@@ -398,7 +398,7 @@ static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
398} 398}
399 399
400static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, 400static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
401 struct amdgpu_mc *mc) 401 struct amdgpu_gmc *mc)
402{ 402{
403 u64 base = 0; 403 u64 base = 0;
404 404
@@ -406,7 +406,7 @@ static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
406 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 406 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
407 base <<= 24; 407 base <<= 24;
408 408
409 amdgpu_device_vram_location(adev, &adev->mc, base); 409 amdgpu_device_vram_location(adev, &adev->gmc, base);
410 amdgpu_device_gart_location(adev, mc); 410 amdgpu_device_gart_location(adev, mc);
411} 411}
412 412
@@ -449,18 +449,18 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
449 } 449 }
450 /* Update configuration */ 450 /* Update configuration */
451 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 451 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
452 adev->mc.vram_start >> 12); 452 adev->gmc.vram_start >> 12);
453 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 453 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
454 adev->mc.vram_end >> 12); 454 adev->gmc.vram_end >> 12);
455 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 455 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
456 adev->vram_scratch.gpu_addr >> 12); 456 adev->vram_scratch.gpu_addr >> 12);
457 457
458 if (amdgpu_sriov_vf(adev)) { 458 if (amdgpu_sriov_vf(adev)) {
459 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16; 459 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;
460 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF); 460 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF);
461 WREG32(mmMC_VM_FB_LOCATION, tmp); 461 WREG32(mmMC_VM_FB_LOCATION, tmp);
462 /* XXX double check these! */ 462 /* XXX double check these! */
463 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8)); 463 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
464 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 464 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
465 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); 465 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
466 } 466 }
@@ -495,8 +495,8 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
495{ 495{
496 int r; 496 int r;
497 497
498 adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev); 498 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
499 if (!adev->mc.vram_width) { 499 if (!adev->gmc.vram_width) {
500 u32 tmp; 500 u32 tmp;
501 int chansize, numchan; 501 int chansize, numchan;
502 502
@@ -538,31 +538,31 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
538 numchan = 16; 538 numchan = 16;
539 break; 539 break;
540 } 540 }
541 adev->mc.vram_width = numchan * chansize; 541 adev->gmc.vram_width = numchan * chansize;
542 } 542 }
543 /* size in MB on si */ 543 /* size in MB on si */
544 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 544 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
545 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 545 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
546 546
547 if (!(adev->flags & AMD_IS_APU)) { 547 if (!(adev->flags & AMD_IS_APU)) {
548 r = amdgpu_device_resize_fb_bar(adev); 548 r = amdgpu_device_resize_fb_bar(adev);
549 if (r) 549 if (r)
550 return r; 550 return r;
551 } 551 }
552 adev->mc.aper_base = pci_resource_start(adev->pdev, 0); 552 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
553 adev->mc.aper_size = pci_resource_len(adev->pdev, 0); 553 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
554 554
555#ifdef CONFIG_X86_64 555#ifdef CONFIG_X86_64
556 if (adev->flags & AMD_IS_APU) { 556 if (adev->flags & AMD_IS_APU) {
557 adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 557 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
558 adev->mc.aper_size = adev->mc.real_vram_size; 558 adev->gmc.aper_size = adev->gmc.real_vram_size;
559 } 559 }
560#endif 560#endif
561 561
562 /* In case the PCI BAR is larger than the actual amount of vram */ 562 /* In case the PCI BAR is larger than the actual amount of vram */
563 adev->mc.visible_vram_size = adev->mc.aper_size; 563 adev->gmc.visible_vram_size = adev->gmc.aper_size;
564 if (adev->mc.visible_vram_size > adev->mc.real_vram_size) 564 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
565 adev->mc.visible_vram_size = adev->mc.real_vram_size; 565 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
566 566
567 /* set the gart size */ 567 /* set the gart size */
568 if (amdgpu_gart_size == -1) { 568 if (amdgpu_gart_size == -1) {
@@ -571,20 +571,20 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
571 case CHIP_POLARIS10: /* all engines support GPUVM */ 571 case CHIP_POLARIS10: /* all engines support GPUVM */
572 case CHIP_POLARIS12: /* all engines support GPUVM */ 572 case CHIP_POLARIS12: /* all engines support GPUVM */
573 default: 573 default:
574 adev->mc.gart_size = 256ULL << 20; 574 adev->gmc.gart_size = 256ULL << 20;
575 break; 575 break;
576 case CHIP_TONGA: /* UVD, VCE do not support GPUVM */ 576 case CHIP_TONGA: /* UVD, VCE do not support GPUVM */
577 case CHIP_FIJI: /* UVD, VCE do not support GPUVM */ 577 case CHIP_FIJI: /* UVD, VCE do not support GPUVM */
578 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */ 578 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
579 case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */ 579 case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */
580 adev->mc.gart_size = 1024ULL << 20; 580 adev->gmc.gart_size = 1024ULL << 20;
581 break; 581 break;
582 } 582 }
583 } else { 583 } else {
584 adev->mc.gart_size = (u64)amdgpu_gart_size << 20; 584 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
585 } 585 }
586 586
587 gmc_v8_0_vram_gtt_location(adev, &adev->mc); 587 gmc_v8_0_vram_gtt_location(adev, &adev->gmc);
588 588
589 return 0; 589 return 0;
590} 590}
@@ -720,9 +720,9 @@ static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
720{ 720{
721 u32 tmp; 721 u32 tmp;
722 722
723 if (enable && !adev->mc.prt_warning) { 723 if (enable && !adev->gmc.prt_warning) {
724 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 724 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
725 adev->mc.prt_warning = true; 725 adev->gmc.prt_warning = true;
726 } 726 }
727 727
728 tmp = RREG32(mmVM_PRT_CNTL); 728 tmp = RREG32(mmVM_PRT_CNTL);
@@ -834,8 +834,8 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
834 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); 834 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
835 WREG32(mmVM_L2_CNTL4, tmp); 835 WREG32(mmVM_L2_CNTL4, tmp);
836 /* setup context0 */ 836 /* setup context0 */
837 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12); 837 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
838 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12); 838 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
839 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); 839 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
840 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 840 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
841 (u32)(adev->dummy_page.addr >> 12)); 841 (u32)(adev->dummy_page.addr >> 12));
@@ -890,7 +890,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
890 890
891 gmc_v8_0_gart_flush_gpu_tlb(adev, 0); 891 gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
892 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 892 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
893 (unsigned)(adev->mc.gart_size >> 20), 893 (unsigned)(adev->gmc.gart_size >> 20),
894 (unsigned long long)adev->gart.table_addr); 894 (unsigned long long)adev->gart.table_addr);
895 adev->gart.ready = true; 895 adev->gart.ready = true;
896 return 0; 896 return 0;
@@ -1012,13 +1012,13 @@ static int gmc_v8_0_early_init(void *handle)
1012 gmc_v8_0_set_gart_funcs(adev); 1012 gmc_v8_0_set_gart_funcs(adev);
1013 gmc_v8_0_set_irq_funcs(adev); 1013 gmc_v8_0_set_irq_funcs(adev);
1014 1014
1015 adev->mc.shared_aperture_start = 0x2000000000000000ULL; 1015 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1016 adev->mc.shared_aperture_end = 1016 adev->gmc.shared_aperture_end =
1017 adev->mc.shared_aperture_start + (4ULL << 30) - 1; 1017 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1018 adev->mc.private_aperture_start = 1018 adev->gmc.private_aperture_start =
1019 adev->mc.shared_aperture_end + 1; 1019 adev->gmc.shared_aperture_end + 1;
1020 adev->mc.private_aperture_end = 1020 adev->gmc.private_aperture_end =
1021 adev->mc.private_aperture_start + (4ULL << 30) - 1; 1021 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1022 1022
1023 return 0; 1023 return 0;
1024} 1024}
@@ -1028,7 +1028,7 @@ static int gmc_v8_0_late_init(void *handle)
1028 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1028 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1029 1029
1030 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 1030 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
1031 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 1031 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1032 else 1032 else
1033 return 0; 1033 return 0;
1034} 1034}
@@ -1042,7 +1042,7 @@ static int gmc_v8_0_sw_init(void *handle)
1042 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1042 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1043 1043
1044 if (adev->flags & AMD_IS_APU) { 1044 if (adev->flags & AMD_IS_APU) {
1045 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 1045 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
1046 } else { 1046 } else {
1047 u32 tmp; 1047 u32 tmp;
1048 1048
@@ -1051,14 +1051,14 @@ static int gmc_v8_0_sw_init(void *handle)
1051 else 1051 else
1052 tmp = RREG32(mmMC_SEQ_MISC0); 1052 tmp = RREG32(mmMC_SEQ_MISC0);
1053 tmp &= MC_SEQ_MISC0__MT__MASK; 1053 tmp &= MC_SEQ_MISC0__MT__MASK;
1054 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp); 1054 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
1055 } 1055 }
1056 1056
1057 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault); 1057 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
1058 if (r) 1058 if (r)
1059 return r; 1059 return r;
1060 1060
1061 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault); 1061 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
1062 if (r) 1062 if (r)
1063 return r; 1063 return r;
1064 1064
@@ -1072,9 +1072,9 @@ static int gmc_v8_0_sw_init(void *handle)
1072 * This is the max address of the GPU's 1072 * This is the max address of the GPU's
1073 * internal address space. 1073 * internal address space.
1074 */ 1074 */
1075 adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1075 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1076 1076
1077 adev->mc.stolen_size = 256 * 1024; 1077 adev->gmc.stolen_size = 256 * 1024;
1078 1078
1079 /* set DMA mask + need_dma32 flags. 1079 /* set DMA mask + need_dma32 flags.
1080 * PCIE - can handle 40-bits. 1080 * PCIE - can handle 40-bits.
@@ -1146,8 +1146,8 @@ static int gmc_v8_0_sw_fini(void *handle)
1146 amdgpu_vm_manager_fini(adev); 1146 amdgpu_vm_manager_fini(adev);
1147 gmc_v8_0_gart_fini(adev); 1147 gmc_v8_0_gart_fini(adev);
1148 amdgpu_bo_fini(adev); 1148 amdgpu_bo_fini(adev);
1149 release_firmware(adev->mc.fw); 1149 release_firmware(adev->gmc.fw);
1150 adev->mc.fw = NULL; 1150 adev->gmc.fw = NULL;
1151 1151
1152 return 0; 1152 return 0;
1153} 1153}
@@ -1188,7 +1188,7 @@ static int gmc_v8_0_hw_fini(void *handle)
1188{ 1188{
1189 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1189 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1190 1190
1191 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); 1191 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1192 gmc_v8_0_gart_disable(adev); 1192 gmc_v8_0_gart_disable(adev);
1193 1193
1194 return 0; 1194 return 0;
@@ -1268,10 +1268,10 @@ static bool gmc_v8_0_check_soft_reset(void *handle)
1268 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1268 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1269 } 1269 }
1270 if (srbm_soft_reset) { 1270 if (srbm_soft_reset) {
1271 adev->mc.srbm_soft_reset = srbm_soft_reset; 1271 adev->gmc.srbm_soft_reset = srbm_soft_reset;
1272 return true; 1272 return true;
1273 } else { 1273 } else {
1274 adev->mc.srbm_soft_reset = 0; 1274 adev->gmc.srbm_soft_reset = 0;
1275 return false; 1275 return false;
1276 } 1276 }
1277} 1277}
@@ -1280,7 +1280,7 @@ static int gmc_v8_0_pre_soft_reset(void *handle)
1280{ 1280{
1281 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1281 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1282 1282
1283 if (!adev->mc.srbm_soft_reset) 1283 if (!adev->gmc.srbm_soft_reset)
1284 return 0; 1284 return 0;
1285 1285
1286 gmc_v8_0_mc_stop(adev); 1286 gmc_v8_0_mc_stop(adev);
@@ -1296,9 +1296,9 @@ static int gmc_v8_0_soft_reset(void *handle)
1296 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1296 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1297 u32 srbm_soft_reset; 1297 u32 srbm_soft_reset;
1298 1298
1299 if (!adev->mc.srbm_soft_reset) 1299 if (!adev->gmc.srbm_soft_reset)
1300 return 0; 1300 return 0;
1301 srbm_soft_reset = adev->mc.srbm_soft_reset; 1301 srbm_soft_reset = adev->gmc.srbm_soft_reset;
1302 1302
1303 if (srbm_soft_reset) { 1303 if (srbm_soft_reset) {
1304 u32 tmp; 1304 u32 tmp;
@@ -1326,7 +1326,7 @@ static int gmc_v8_0_post_soft_reset(void *handle)
1326{ 1326{
1327 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1327 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1328 1328
1329 if (!adev->mc.srbm_soft_reset) 1329 if (!adev->gmc.srbm_soft_reset)
1330 return 0; 1330 return 0;
1331 1331
1332 gmc_v8_0_mc_resume(adev); 1332 gmc_v8_0_mc_resume(adev);
@@ -1661,8 +1661,8 @@ static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
1661 1661
1662static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) 1662static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1663{ 1663{
1664 adev->mc.vm_fault.num_types = 1; 1664 adev->gmc.vm_fault.num_types = 1;
1665 adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs; 1665 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1666} 1666}
1667 1667
1668const struct amdgpu_ip_block_version gmc_v8_0_ip_block = 1668const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 1d67df045d2e..e3d0098f0524 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -285,8 +285,8 @@ static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
285 285
286static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 286static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
287{ 287{
288 adev->mc.vm_fault.num_types = 1; 288 adev->gmc.vm_fault.num_types = 1;
289 adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 289 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
290} 290}
291 291
292static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid) 292static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid)
@@ -330,7 +330,7 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
330 const unsigned eng = 17; 330 const unsigned eng = 17;
331 unsigned i, j; 331 unsigned i, j;
332 332
333 spin_lock(&adev->mc.invalidate_lock); 333 spin_lock(&adev->gmc.invalidate_lock);
334 334
335 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { 335 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
336 struct amdgpu_vmhub *hub = &adev->vmhub[i]; 336 struct amdgpu_vmhub *hub = &adev->vmhub[i];
@@ -363,7 +363,7 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
363 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 363 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
364 } 364 }
365 365
366 spin_unlock(&adev->mc.invalidate_lock); 366 spin_unlock(&adev->gmc.invalidate_lock);
367} 367}
368 368
369/** 369/**
@@ -472,10 +472,10 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
472{ 472{
473 if (!(*flags & AMDGPU_PDE_PTE)) 473 if (!(*flags & AMDGPU_PDE_PTE))
474 *addr = adev->vm_manager.vram_base_offset + *addr - 474 *addr = adev->vm_manager.vram_base_offset + *addr -
475 adev->mc.vram_start; 475 adev->gmc.vram_start;
476 BUG_ON(*addr & 0xFFFF00000000003FULL); 476 BUG_ON(*addr & 0xFFFF00000000003FULL);
477 477
478 if (!adev->mc.translate_further) 478 if (!adev->gmc.translate_further)
479 return; 479 return;
480 480
481 if (level == AMDGPU_VM_PDB1) { 481 if (level == AMDGPU_VM_PDB1) {
@@ -512,13 +512,13 @@ static int gmc_v9_0_early_init(void *handle)
512 gmc_v9_0_set_gart_funcs(adev); 512 gmc_v9_0_set_gart_funcs(adev);
513 gmc_v9_0_set_irq_funcs(adev); 513 gmc_v9_0_set_irq_funcs(adev);
514 514
515 adev->mc.shared_aperture_start = 0x2000000000000000ULL; 515 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
516 adev->mc.shared_aperture_end = 516 adev->gmc.shared_aperture_end =
517 adev->mc.shared_aperture_start + (4ULL << 30) - 1; 517 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
518 adev->mc.private_aperture_start = 518 adev->gmc.private_aperture_start =
519 adev->mc.shared_aperture_end + 1; 519 adev->gmc.shared_aperture_end + 1;
520 adev->mc.private_aperture_end = 520 adev->gmc.private_aperture_end =
521 adev->mc.private_aperture_start + (4ULL << 30) - 1; 521 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
522 522
523 return 0; 523 return 0;
524} 524}
@@ -644,16 +644,16 @@ static int gmc_v9_0_late_init(void *handle)
644 } 644 }
645 } 645 }
646 646
647 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 647 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
648} 648}
649 649
650static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 650static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
651 struct amdgpu_mc *mc) 651 struct amdgpu_gmc *mc)
652{ 652{
653 u64 base = 0; 653 u64 base = 0;
654 if (!amdgpu_sriov_vf(adev)) 654 if (!amdgpu_sriov_vf(adev))
655 base = mmhub_v1_0_get_fb_location(adev); 655 base = mmhub_v1_0_get_fb_location(adev);
656 amdgpu_device_vram_location(adev, &adev->mc, base); 656 amdgpu_device_vram_location(adev, &adev->gmc, base);
657 amdgpu_device_gart_location(adev, mc); 657 amdgpu_device_gart_location(adev, mc);
658 /* base offset of vram pages */ 658 /* base offset of vram pages */
659 if (adev->flags & AMD_IS_APU) 659 if (adev->flags & AMD_IS_APU)
@@ -677,8 +677,8 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
677 int chansize, numchan; 677 int chansize, numchan;
678 int r; 678 int r;
679 679
680 adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); 680 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
681 if (!adev->mc.vram_width) { 681 if (!adev->gmc.vram_width) {
682 /* hbm memory channel size */ 682 /* hbm memory channel size */
683 chansize = 128; 683 chansize = 128;
684 684
@@ -715,43 +715,43 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
715 numchan = 2; 715 numchan = 2;
716 break; 716 break;
717 } 717 }
718 adev->mc.vram_width = numchan * chansize; 718 adev->gmc.vram_width = numchan * chansize;
719 } 719 }
720 720
721 /* size in MB on si */ 721 /* size in MB on si */
722 adev->mc.mc_vram_size = 722 adev->gmc.mc_vram_size =
723 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL; 723 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
724 adev->mc.real_vram_size = adev->mc.mc_vram_size; 724 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
725 725
726 if (!(adev->flags & AMD_IS_APU)) { 726 if (!(adev->flags & AMD_IS_APU)) {
727 r = amdgpu_device_resize_fb_bar(adev); 727 r = amdgpu_device_resize_fb_bar(adev);
728 if (r) 728 if (r)
729 return r; 729 return r;
730 } 730 }
731 adev->mc.aper_base = pci_resource_start(adev->pdev, 0); 731 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
732 adev->mc.aper_size = pci_resource_len(adev->pdev, 0); 732 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
733 733
734 /* In case the PCI BAR is larger than the actual amount of vram */ 734 /* In case the PCI BAR is larger than the actual amount of vram */
735 adev->mc.visible_vram_size = adev->mc.aper_size; 735 adev->gmc.visible_vram_size = adev->gmc.aper_size;
736 if (adev->mc.visible_vram_size > adev->mc.real_vram_size) 736 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
737 adev->mc.visible_vram_size = adev->mc.real_vram_size; 737 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
738 738
739 /* set the gart size */ 739 /* set the gart size */
740 if (amdgpu_gart_size == -1) { 740 if (amdgpu_gart_size == -1) {
741 switch (adev->asic_type) { 741 switch (adev->asic_type) {
742 case CHIP_VEGA10: /* all engines support GPUVM */ 742 case CHIP_VEGA10: /* all engines support GPUVM */
743 default: 743 default:
744 adev->mc.gart_size = 256ULL << 20; 744 adev->gmc.gart_size = 256ULL << 20;
745 break; 745 break;
746 case CHIP_RAVEN: /* DCE SG support */ 746 case CHIP_RAVEN: /* DCE SG support */
747 adev->mc.gart_size = 1024ULL << 20; 747 adev->gmc.gart_size = 1024ULL << 20;
748 break; 748 break;
749 } 749 }
750 } else { 750 } else {
751 adev->mc.gart_size = (u64)amdgpu_gart_size << 20; 751 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
752 } 752 }
753 753
754 gmc_v9_0_vram_gtt_location(adev, &adev->mc); 754 gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
755 755
756 return 0; 756 return 0;
757} 757}
@@ -783,23 +783,23 @@ static int gmc_v9_0_sw_init(void *handle)
783 gfxhub_v1_0_init(adev); 783 gfxhub_v1_0_init(adev);
784 mmhub_v1_0_init(adev); 784 mmhub_v1_0_init(adev);
785 785
786 spin_lock_init(&adev->mc.invalidate_lock); 786 spin_lock_init(&adev->gmc.invalidate_lock);
787 787
788 switch (adev->asic_type) { 788 switch (adev->asic_type) {
789 case CHIP_RAVEN: 789 case CHIP_RAVEN:
790 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 790 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
791 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 791 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
792 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 792 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
793 } else { 793 } else {
794 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 794 /* vm_size is 128TB + 512GB for legacy 3-level page support */
795 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 795 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
796 adev->mc.translate_further = 796 adev->gmc.translate_further =
797 adev->vm_manager.num_level > 1; 797 adev->vm_manager.num_level > 1;
798 } 798 }
799 break; 799 break;
800 case CHIP_VEGA10: 800 case CHIP_VEGA10:
801 /* XXX Don't know how to get VRAM type yet. */ 801 /* XXX Don't know how to get VRAM type yet. */
802 adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM; 802 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM;
803 /* 803 /*
804 * To fulfill 4-level page support, 804 * To fulfill 4-level page support,
805 * vm size is 256TB (48bit), maximum size of Vega10, 805 * vm size is 256TB (48bit), maximum size of Vega10,
@@ -813,9 +813,9 @@ static int gmc_v9_0_sw_init(void *handle)
813 813
814 /* This interrupt is VMC page fault.*/ 814 /* This interrupt is VMC page fault.*/
815 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0, 815 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
816 &adev->mc.vm_fault); 816 &adev->gmc.vm_fault);
817 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UTCL2, 0, 817 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UTCL2, 0,
818 &adev->mc.vm_fault); 818 &adev->gmc.vm_fault);
819 819
820 if (r) 820 if (r)
821 return r; 821 return r;
@@ -824,13 +824,13 @@ static int gmc_v9_0_sw_init(void *handle)
824 * This is the max address of the GPU's 824 * This is the max address of the GPU's
825 * internal address space. 825 * internal address space.
826 */ 826 */
827 adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 827 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
828 828
829 /* 829 /*
830 * It needs to reserve 8M stolen memory for vega10 830 * It needs to reserve 8M stolen memory for vega10
831 * TODO: Figure out how to avoid that... 831 * TODO: Figure out how to avoid that...
832 */ 832 */
833 adev->mc.stolen_size = 8 * 1024 * 1024; 833 adev->gmc.stolen_size = 8 * 1024 * 1024;
834 834
835 /* set DMA mask + need_dma32 flags. 835 /* set DMA mask + need_dma32 flags.
836 * PCIE - can handle 44-bits. 836 * PCIE - can handle 44-bits.
@@ -984,7 +984,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
984 gmc_v9_0_gart_flush_gpu_tlb(adev, 0); 984 gmc_v9_0_gart_flush_gpu_tlb(adev, 0);
985 985
986 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 986 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
987 (unsigned)(adev->mc.gart_size >> 20), 987 (unsigned)(adev->gmc.gart_size >> 20),
988 (unsigned long long)adev->gart.table_addr); 988 (unsigned long long)adev->gart.table_addr);
989 adev->gart.ready = true; 989 adev->gart.ready = true;
990 return 0; 990 return 0;
@@ -1035,7 +1035,7 @@ static int gmc_v9_0_hw_fini(void *handle)
1035 return 0; 1035 return 0;
1036 } 1036 }
1037 1037
1038 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); 1038 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1039 gmc_v9_0_gart_disable(adev); 1039 gmc_v9_0_gart_disable(adev);
1040 1040
1041 return 0; 1041 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index bdf94c61f246..82f8bc83cc0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -50,7 +50,7 @@ static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
50 uint64_t value; 50 uint64_t value;
51 51
52 BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); 52 BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
53 value = adev->gart.table_addr - adev->mc.vram_start + 53 value = adev->gart.table_addr - adev->gmc.vram_start +
54 adev->vm_manager.vram_base_offset; 54 adev->vm_manager.vram_base_offset;
55 value &= 0x0000FFFFFFFFF000ULL; 55 value &= 0x0000FFFFFFFFF000ULL;
56 value |= 0x1; /* valid bit */ 56 value |= 0x1; /* valid bit */
@@ -67,14 +67,14 @@ static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
67 mmhub_v1_0_init_gart_pt_regs(adev); 67 mmhub_v1_0_init_gart_pt_regs(adev);
68 68
69 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 69 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
70 (u32)(adev->mc.gart_start >> 12)); 70 (u32)(adev->gmc.gart_start >> 12));
71 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 71 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
72 (u32)(adev->mc.gart_start >> 44)); 72 (u32)(adev->gmc.gart_start >> 44));
73 73
74 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 74 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
75 (u32)(adev->mc.gart_end >> 12)); 75 (u32)(adev->gmc.gart_end >> 12));
76 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 76 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
77 (u32)(adev->mc.gart_end >> 44)); 77 (u32)(adev->gmc.gart_end >> 44));
78} 78}
79 79
80static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 80static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
@@ -89,12 +89,12 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
89 89
90 /* Program the system aperture low logical page number. */ 90 /* Program the system aperture low logical page number. */
91 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 91 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
92 adev->mc.vram_start >> 18); 92 adev->gmc.vram_start >> 18);
93 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 93 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
94 adev->mc.vram_end >> 18); 94 adev->gmc.vram_end >> 18);
95 95
96 /* Set default page address. */ 96 /* Set default page address. */
97 value = adev->vram_scratch.gpu_addr - adev->mc.vram_start + 97 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
98 adev->vm_manager.vram_base_offset; 98 adev->vm_manager.vram_base_offset;
99 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 99 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
100 (u32)(value >> 12)); 100 (u32)(value >> 12));
@@ -155,7 +155,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
155 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 155 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
156 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp); 156 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
157 157
158 if (adev->mc.translate_further) { 158 if (adev->gmc.translate_further) {
159 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); 159 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
160 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 160 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
161 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 161 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
@@ -207,7 +207,7 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
207 207
208 num_level = adev->vm_manager.num_level; 208 num_level = adev->vm_manager.num_level;
209 block_size = adev->vm_manager.block_size; 209 block_size = adev->vm_manager.block_size;
210 if (adev->mc.translate_further) 210 if (adev->gmc.translate_further)
211 num_level -= 1; 211 num_level -= 1;
212 else 212 else
213 block_size -= 9; 213 block_size -= 9;
@@ -499,9 +499,9 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
499 * SRIOV driver need to program them 499 * SRIOV driver need to program them
500 */ 500 */
501 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE, 501 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE,
502 adev->mc.vram_start >> 24); 502 adev->gmc.vram_start >> 24);
503 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP, 503 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP,
504 adev->mc.vram_end >> 24); 504 adev->gmc.vram_end >> 24);
505 } 505 }
506 506
507 /* GART Enable. */ 507 /* GART Enable. */
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index d4787ad4d346..e9c74641ac01 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -346,7 +346,7 @@ static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
346 346
347 if ((adev->mman.buffer_funcs_ring == sdma0) || 347 if ((adev->mman.buffer_funcs_ring == sdma0) ||
348 (adev->mman.buffer_funcs_ring == sdma1)) 348 (adev->mman.buffer_funcs_ring == sdma1))
349 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 349 amdgpu_ttm_set_active_vram_size(adev, adev->gmc.visible_vram_size);
350 350
351 for (i = 0; i < adev->sdma.num_instances; i++) { 351 for (i = 0; i < adev->sdma.num_instances; i++) {
352 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 352 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
@@ -491,7 +491,7 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
491 } 491 }
492 492
493 if (adev->mman.buffer_funcs_ring == ring) 493 if (adev->mman.buffer_funcs_ring == ring)
494 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); 494 amdgpu_ttm_set_active_vram_size(adev, adev->gmc.real_vram_size);
495 } 495 }
496 496
497 return 0; 497 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 521978c40537..b56f8dd93a4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -518,7 +518,7 @@ static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
518 518
519 if ((adev->mman.buffer_funcs_ring == sdma0) || 519 if ((adev->mman.buffer_funcs_ring == sdma0) ||
520 (adev->mman.buffer_funcs_ring == sdma1)) 520 (adev->mman.buffer_funcs_ring == sdma1))
521 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 521 amdgpu_ttm_set_active_vram_size(adev, adev->gmc.visible_vram_size);
522 522
523 for (i = 0; i < adev->sdma.num_instances; i++) { 523 for (i = 0; i < adev->sdma.num_instances; i++) {
524 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 524 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
@@ -758,7 +758,7 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
758 } 758 }
759 759
760 if (adev->mman.buffer_funcs_ring == ring) 760 if (adev->mman.buffer_funcs_ring == ring)
761 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); 761 amdgpu_ttm_set_active_vram_size(adev, adev->gmc.real_vram_size);
762 } 762 }
763 763
764 return 0; 764 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index e92fb372bc99..8a0b1b9cbca8 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -440,7 +440,7 @@ static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
440 440
441 if ((adev->mman.buffer_funcs_ring == sdma0) || 441 if ((adev->mman.buffer_funcs_ring == sdma0) ||
442 (adev->mman.buffer_funcs_ring == sdma1)) 442 (adev->mman.buffer_funcs_ring == sdma1))
443 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 443 amdgpu_ttm_set_active_vram_size(adev, adev->gmc.visible_vram_size);
444 444
445 for (i = 0; i < adev->sdma.num_instances; i++) { 445 for (i = 0; i < adev->sdma.num_instances; i++) {
446 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 446 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
@@ -682,7 +682,7 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
682 } 682 }
683 683
684 if (adev->mman.buffer_funcs_ring == ring) 684 if (adev->mman.buffer_funcs_ring == ring)
685 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); 685 amdgpu_ttm_set_active_vram_size(adev, adev->gmc.real_vram_size);
686 686
687 } 687 }
688 688
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 9a29c1399091..54e7a12eb50e 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -134,7 +134,7 @@ static void si_dma_stop(struct amdgpu_device *adev)
134 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); 134 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl);
135 135
136 if (adev->mman.buffer_funcs_ring == ring) 136 if (adev->mman.buffer_funcs_ring == ring)
137 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 137 amdgpu_ttm_set_active_vram_size(adev, adev->gmc.visible_vram_size);
138 ring->ready = false; 138 ring->ready = false;
139 } 139 }
140} 140}
@@ -197,7 +197,7 @@ static int si_dma_start(struct amdgpu_device *adev)
197 } 197 }
198 198
199 if (adev->mman.buffer_funcs_ring == ring) 199 if (adev->mman.buffer_funcs_ring == ring)
200 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); 200 amdgpu_ttm_set_active_vram_size(adev, adev->gmc.real_vram_size);
201 } 201 }
202 202
203 return 0; 203 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index ce675a7f179a..9d57115a2d67 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -3064,7 +3064,7 @@ static bool si_dpm_vblank_too_short(void *handle)
3064 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3064 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3065 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev); 3065 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
3066 /* we never hit the non-gddr5 limit so disable it */ 3066 /* we never hit the non-gddr5 limit so disable it */
3067 u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0; 3067 u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
3068 3068
3069 if (vblank_time < switch_limit) 3069 if (vblank_time < switch_limit)
3070 return true; 3070 return true;
@@ -4350,7 +4350,7 @@ static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4350 if (mclk <= pi->mclk_strobe_mode_threshold) 4350 if (mclk <= pi->mclk_strobe_mode_threshold)
4351 strobe_mode = true; 4351 strobe_mode = true;
4352 4352
4353 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 4353 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4354 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 4354 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4355 else 4355 else
4356 result = si_get_ddr3_mclk_frequency_ratio(mclk); 4356 result = si_get_ddr3_mclk_frequency_ratio(mclk);
@@ -4937,7 +4937,7 @@ static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4937 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4937 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4938 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4938 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4939 4939
4940 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 4940 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4941 table->initialState.levels[0].strobeMode = 4941 table->initialState.levels[0].strobeMode =
4942 si_get_strobe_mode_settings(adev, 4942 si_get_strobe_mode_settings(adev,
4943 initial_state->performance_levels[0].mclk); 4943 initial_state->performance_levels[0].mclk);
@@ -5208,7 +5208,7 @@ static int si_init_smc_table(struct amdgpu_device *adev)
5208 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 5208 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5209 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 5209 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5210 5210
5211 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 5211 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5212 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 5212 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5213 5213
5214 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 5214 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
@@ -5385,7 +5385,7 @@ static int si_populate_mclk_value(struct amdgpu_device *adev,
5385 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 5385 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5386 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 5386 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5387 5387
5388 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 5388 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5389 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 5389 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5390 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 5390 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5391 YCLK_POST_DIV(mpll_param.post_div); 5391 YCLK_POST_DIV(mpll_param.post_div);
@@ -5397,7 +5397,7 @@ static int si_populate_mclk_value(struct amdgpu_device *adev,
5397 u32 tmp; 5397 u32 tmp;
5398 u32 reference_clock = adev->clock.mpll.reference_freq; 5398 u32 reference_clock = adev->clock.mpll.reference_freq;
5399 5399
5400 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 5400 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5401 freq_nom = memory_clock * 4; 5401 freq_nom = memory_clock * 4;
5402 else 5402 else
5403 freq_nom = memory_clock * 2; 5403 freq_nom = memory_clock * 2;
@@ -5489,7 +5489,7 @@ static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5489 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 5489 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5490 } 5490 }
5491 5491
5492 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 5492 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5493 if (pl->mclk > pi->mclk_edc_enable_threshold) 5493 if (pl->mclk > pi->mclk_edc_enable_threshold)
5494 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 5494 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5495 5495
@@ -5860,12 +5860,12 @@ static int si_set_mc_special_registers(struct amdgpu_device *adev,
5860 table->mc_reg_table_entry[k].mc_data[j] = 5860 table->mc_reg_table_entry[k].mc_data[j] =
5861 (temp_reg & 0xffff0000) | 5861 (temp_reg & 0xffff0000) |
5862 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5862 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5863 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) 5863 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5864 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5864 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5865 } 5865 }
5866 j++; 5866 j++;
5867 5867
5868 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) { 5868 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5869 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5869 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5870 return -EINVAL; 5870 return -EINVAL;
5871 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD; 5871 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 03:18:44 -0400