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authorAlex Deucher <alexander.deucher@amd.com>2016-10-13 17:41:13 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-10-25 14:38:45 -0400
commita12551072126758ecb0743147054f22bf233bb7d (patch)
treef3850a0b1945b6620fd591cafdb8ecb998b01302 /drivers/gpu/drm/amd/amdgpu/si.c
parentcf35c7ca3d50286a3ac7672aa7d26a8d2e930706 (diff)
drm/amdgpu: rework IP block registration (v2)
This makes it easier to replace specific IP blocks on asics for handling virtual_dce, DAL, etc. and for building IP lists for hw or tables. This also stored the status information in the same structure. v2: split out spelling fix into a separate patch add a function to add IPs to the list Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/si.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si.c288
1 files changed, 40 insertions, 248 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 1d40c26de324..d2d79206bcf9 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1812,7 +1812,7 @@ static int si_common_set_powergating_state(void *handle,
1812 return 0; 1812 return 0;
1813} 1813}
1814 1814
1815const struct amd_ip_funcs si_common_ip_funcs = { 1815static const struct amd_ip_funcs si_common_ip_funcs = {
1816 .name = "si_common", 1816 .name = "si_common",
1817 .early_init = si_common_early_init, 1817 .early_init = si_common_early_init,
1818 .late_init = NULL, 1818 .late_init = NULL,
@@ -1829,240 +1829,13 @@ const struct amd_ip_funcs si_common_ip_funcs = {
1829 .set_powergating_state = si_common_set_powergating_state, 1829 .set_powergating_state = si_common_set_powergating_state,
1830}; 1830};
1831 1831
1832static const struct amdgpu_ip_block_version verde_ip_blocks[] = 1832static const struct amdgpu_ip_block_version si_common_ip_block =
1833{ 1833{
1834 { 1834 .type = AMD_IP_BLOCK_TYPE_COMMON,
1835 .type = AMD_IP_BLOCK_TYPE_COMMON, 1835 .major = 1,
1836 .major = 1, 1836 .minor = 0,
1837 .minor = 0, 1837 .rev = 0,
1838 .rev = 0, 1838 .funcs = &si_common_ip_funcs,
1839 .funcs = &si_common_ip_funcs,
1840 },
1841 {
1842 .type = AMD_IP_BLOCK_TYPE_GMC,
1843 .major = 6,
1844 .minor = 0,
1845 .rev = 0,
1846 .funcs = &gmc_v6_0_ip_funcs,
1847 },
1848 {
1849 .type = AMD_IP_BLOCK_TYPE_IH,
1850 .major = 1,
1851 .minor = 0,
1852 .rev = 0,
1853 .funcs = &si_ih_ip_funcs,
1854 },
1855 {
1856 .type = AMD_IP_BLOCK_TYPE_SMC,
1857 .major = 6,
1858 .minor = 0,
1859 .rev = 0,
1860 .funcs = &amdgpu_pp_ip_funcs,
1861 },
1862 {
1863 .type = AMD_IP_BLOCK_TYPE_DCE,
1864 .major = 6,
1865 .minor = 0,
1866 .rev = 0,
1867 .funcs = &dce_v6_0_ip_funcs,
1868 },
1869 {
1870 .type = AMD_IP_BLOCK_TYPE_GFX,
1871 .major = 6,
1872 .minor = 0,
1873 .rev = 0,
1874 .funcs = &gfx_v6_0_ip_funcs,
1875 },
1876 {
1877 .type = AMD_IP_BLOCK_TYPE_SDMA,
1878 .major = 1,
1879 .minor = 0,
1880 .rev = 0,
1881 .funcs = &si_dma_ip_funcs,
1882 },
1883/* {
1884 .type = AMD_IP_BLOCK_TYPE_UVD,
1885 .major = 3,
1886 .minor = 1,
1887 .rev = 0,
1888 .funcs = &si_null_ip_funcs,
1889 },
1890 {
1891 .type = AMD_IP_BLOCK_TYPE_VCE,
1892 .major = 1,
1893 .minor = 0,
1894 .rev = 0,
1895 .funcs = &si_null_ip_funcs,
1896 },
1897 */
1898};
1899
1900
1901static const struct amdgpu_ip_block_version verde_ip_blocks_vd[] =
1902{
1903 {
1904 .type = AMD_IP_BLOCK_TYPE_COMMON,
1905 .major = 1,
1906 .minor = 0,
1907 .rev = 0,
1908 .funcs = &si_common_ip_funcs,
1909 },
1910 {
1911 .type = AMD_IP_BLOCK_TYPE_GMC,
1912 .major = 6,
1913 .minor = 0,
1914 .rev = 0,
1915 .funcs = &gmc_v6_0_ip_funcs,
1916 },
1917 {
1918 .type = AMD_IP_BLOCK_TYPE_IH,
1919 .major = 1,
1920 .minor = 0,
1921 .rev = 0,
1922 .funcs = &si_ih_ip_funcs,
1923 },
1924 {
1925 .type = AMD_IP_BLOCK_TYPE_SMC,
1926 .major = 6,
1927 .minor = 0,
1928 .rev = 0,
1929 .funcs = &amdgpu_pp_ip_funcs,
1930 },
1931 {
1932 .type = AMD_IP_BLOCK_TYPE_DCE,
1933 .major = 6,
1934 .minor = 0,
1935 .rev = 0,
1936 .funcs = &dce_virtual_ip_funcs,
1937 },
1938 {
1939 .type = AMD_IP_BLOCK_TYPE_GFX,
1940 .major = 6,
1941 .minor = 0,
1942 .rev = 0,
1943 .funcs = &gfx_v6_0_ip_funcs,
1944 },
1945 {
1946 .type = AMD_IP_BLOCK_TYPE_SDMA,
1947 .major = 1,
1948 .minor = 0,
1949 .rev = 0,
1950 .funcs = &si_dma_ip_funcs,
1951 },
1952/* {
1953 .type = AMD_IP_BLOCK_TYPE_UVD,
1954 .major = 3,
1955 .minor = 1,
1956 .rev = 0,
1957 .funcs = &si_null_ip_funcs,
1958 },
1959 {
1960 .type = AMD_IP_BLOCK_TYPE_VCE,
1961 .major = 1,
1962 .minor = 0,
1963 .rev = 0,
1964 .funcs = &si_null_ip_funcs,
1965 },
1966 */
1967};
1968
1969static const struct amdgpu_ip_block_version hainan_ip_blocks[] =
1970{
1971 {
1972 .type = AMD_IP_BLOCK_TYPE_COMMON,
1973 .major = 1,
1974 .minor = 0,
1975 .rev = 0,
1976 .funcs = &si_common_ip_funcs,
1977 },
1978 {
1979 .type = AMD_IP_BLOCK_TYPE_GMC,
1980 .major = 6,
1981 .minor = 0,
1982 .rev = 0,
1983 .funcs = &gmc_v6_0_ip_funcs,
1984 },
1985 {
1986 .type = AMD_IP_BLOCK_TYPE_IH,
1987 .major = 1,
1988 .minor = 0,
1989 .rev = 0,
1990 .funcs = &si_ih_ip_funcs,
1991 },
1992 {
1993 .type = AMD_IP_BLOCK_TYPE_SMC,
1994 .major = 6,
1995 .minor = 0,
1996 .rev = 0,
1997 .funcs = &amdgpu_pp_ip_funcs,
1998 },
1999 {
2000 .type = AMD_IP_BLOCK_TYPE_GFX,
2001 .major = 6,
2002 .minor = 0,
2003 .rev = 0,
2004 .funcs = &gfx_v6_0_ip_funcs,
2005 },
2006 {
2007 .type = AMD_IP_BLOCK_TYPE_SDMA,
2008 .major = 1,
2009 .minor = 0,
2010 .rev = 0,
2011 .funcs = &si_dma_ip_funcs,
2012 },
2013};
2014
2015static const struct amdgpu_ip_block_version hainan_ip_blocks_vd[] =
2016{
2017 {
2018 .type = AMD_IP_BLOCK_TYPE_COMMON,
2019 .major = 1,
2020 .minor = 0,
2021 .rev = 0,
2022 .funcs = &si_common_ip_funcs,
2023 },
2024 {
2025 .type = AMD_IP_BLOCK_TYPE_GMC,
2026 .major = 6,
2027 .minor = 0,
2028 .rev = 0,
2029 .funcs = &gmc_v6_0_ip_funcs,
2030 },
2031 {
2032 .type = AMD_IP_BLOCK_TYPE_IH,
2033 .major = 1,
2034 .minor = 0,
2035 .rev = 0,
2036 .funcs = &si_ih_ip_funcs,
2037 },
2038 {
2039 .type = AMD_IP_BLOCK_TYPE_SMC,
2040 .major = 6,
2041 .minor = 0,
2042 .rev = 0,
2043 .funcs = &amdgpu_pp_ip_funcs,
2044 },
2045 {
2046 .type = AMD_IP_BLOCK_TYPE_DCE,
2047 .major = 1,
2048 .minor = 0,
2049 .rev = 0,
2050 .funcs = &dce_virtual_ip_funcs,
2051 },
2052 {
2053 .type = AMD_IP_BLOCK_TYPE_GFX,
2054 .major = 6,
2055 .minor = 0,
2056 .rev = 0,
2057 .funcs = &gfx_v6_0_ip_funcs,
2058 },
2059 {
2060 .type = AMD_IP_BLOCK_TYPE_SDMA,
2061 .major = 1,
2062 .minor = 0,
2063 .rev = 0,
2064 .funcs = &si_dma_ip_funcs,
2065 },
2066}; 1839};
2067 1840
2068int si_set_ip_blocks(struct amdgpu_device *adev) 1841int si_set_ip_blocks(struct amdgpu_device *adev)
@@ -2071,23 +1844,42 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
2071 case CHIP_VERDE: 1844 case CHIP_VERDE:
2072 case CHIP_TAHITI: 1845 case CHIP_TAHITI:
2073 case CHIP_PITCAIRN: 1846 case CHIP_PITCAIRN:
1847 amdgpu_ip_block_add(adev, &si_common_ip_block);
1848 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1849 amdgpu_ip_block_add(adev, &si_ih_ip_block);
1850 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1851 if (adev->enable_virtual_display)
1852 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1853 else
1854 amdgpu_ip_block_add(adev, &dce_v6_0_ip_block);
1855 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1856 amdgpu_ip_block_add(adev, &si_dma_ip_block);
1857 /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
1858 /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
1859 break;
2074 case CHIP_OLAND: 1860 case CHIP_OLAND:
2075 if (adev->enable_virtual_display) { 1861 amdgpu_ip_block_add(adev, &si_common_ip_block);
2076 adev->ip_blocks = verde_ip_blocks_vd; 1862 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
2077 adev->num_ip_blocks = ARRAY_SIZE(verde_ip_blocks_vd); 1863 amdgpu_ip_block_add(adev, &si_ih_ip_block);
2078 } else { 1864 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
2079 adev->ip_blocks = verde_ip_blocks; 1865 if (adev->enable_virtual_display)
2080 adev->num_ip_blocks = ARRAY_SIZE(verde_ip_blocks); 1866 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
2081 } 1867 else
1868 amdgpu_ip_block_add(adev, &dce_v6_4_ip_block);
1869 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1870 amdgpu_ip_block_add(adev, &si_dma_ip_block);
1871 /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
1872 /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
2082 break; 1873 break;
2083 case CHIP_HAINAN: 1874 case CHIP_HAINAN:
2084 if (adev->enable_virtual_display) { 1875 amdgpu_ip_block_add(adev, &si_common_ip_block);
2085 adev->ip_blocks = hainan_ip_blocks_vd; 1876 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
2086 adev->num_ip_blocks = ARRAY_SIZE(hainan_ip_blocks_vd); 1877 amdgpu_ip_block_add(adev, &si_ih_ip_block);
2087 } else { 1878 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
2088 adev->ip_blocks = hainan_ip_blocks; 1879 if (adev->enable_virtual_display)
2089 adev->num_ip_blocks = ARRAY_SIZE(hainan_ip_blocks); 1880 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
2090 } 1881 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1882 amdgpu_ip_block_add(adev, &si_dma_ip_block);
2091 break; 1883 break;
2092 default: 1884 default:
2093 BUG(); 1885 BUG();
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-27 12:14:50 -0400