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authorAlex Deucher <alexander.deucher@amd.com>2016-10-13 17:41:13 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-10-25 14:38:45 -0400
commita12551072126758ecb0743147054f22bf233bb7d (patch)
treef3850a0b1945b6620fd591cafdb8ecb998b01302 /drivers/gpu
parentcf35c7ca3d50286a3ac7672aa7d26a8d2e930706 (diff)
drm/amdgpu: rework IP block registration (v2)
This makes it easier to replace specific IP blocks on asics for handling virtual_dce, DAL, etc. and for building IP lists for hw or tables. This also stored the status information in the same structure. v2: split out spelling fix into a separate patch add a function to add IPs to the list Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h42
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c17
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c12
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c260
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c12
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c11
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/ci_dpm.c9
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik.c817
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_ih.c11
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_ih.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_sdma.c11
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_sdma.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_dpm.c9
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_ih.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_ih.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v10_0.c20
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v10_0.h4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v11_0.c20
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v11_0.h3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v6_0.c20
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v6_0.h3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v8_0.c47
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v8_0.h6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_virtual.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_virtual.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c11
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v6_0.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c38
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c20
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v6_0.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c20
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c29
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/iceland_ih.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/iceland_ih.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/kv_dpm.c9
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c11
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c20
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si.c288
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si_dma.c11
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si_dma.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si_dpm.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si_ih.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si_ih.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/tonga_ih.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/tonga_ih.h4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c11
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c11
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c29
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v2_0.c11
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v2_0.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v3_0.c29
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v3_0.h4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c837
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.h2
69 files changed, 924 insertions, 1935 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index e6f86b83652b..1800ea139c98 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -195,21 +195,38 @@ int amdgpu_wait_for_idle(struct amdgpu_device *adev,
195bool amdgpu_is_idle(struct amdgpu_device *adev, 195bool amdgpu_is_idle(struct amdgpu_device *adev,
196 enum amd_ip_block_type block_type); 196 enum amd_ip_block_type block_type);
197 197
198#define AMDGPU_MAX_IP_NUM 16
199
200struct amdgpu_ip_block_status {
201 bool valid;
202 bool sw;
203 bool hw;
204 bool late_initialized;
205 bool hang;
206};
207
198struct amdgpu_ip_block_version { 208struct amdgpu_ip_block_version {
199 enum amd_ip_block_type type; 209 const enum amd_ip_block_type type;
200 u32 major; 210 const u32 major;
201 u32 minor; 211 const u32 minor;
202 u32 rev; 212 const u32 rev;
203 const struct amd_ip_funcs *funcs; 213 const struct amd_ip_funcs *funcs;
204}; 214};
205 215
216struct amdgpu_ip_block {
217 struct amdgpu_ip_block_status status;
218 const struct amdgpu_ip_block_version *version;
219};
220
206int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 221int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
207 enum amd_ip_block_type type, 222 enum amd_ip_block_type type,
208 u32 major, u32 minor); 223 u32 major, u32 minor);
209 224
210const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 225struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
211 struct amdgpu_device *adev, 226 enum amd_ip_block_type type);
212 enum amd_ip_block_type type); 227
228int amdgpu_ip_block_add(struct amdgpu_device *adev,
229 const struct amdgpu_ip_block_version *ip_block_version);
213 230
214/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 231/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
215struct amdgpu_buffer_funcs { 232struct amdgpu_buffer_funcs {
@@ -1271,14 +1288,6 @@ typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1271typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1288typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1272typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1289typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1273 1290
1274struct amdgpu_ip_block_status {
1275 bool valid;
1276 bool sw;
1277 bool hw;
1278 bool late_initialized;
1279 bool hang;
1280};
1281
1282struct amdgpu_device { 1291struct amdgpu_device {
1283 struct device *dev; 1292 struct device *dev;
1284 struct drm_device *ddev; 1293 struct drm_device *ddev;
@@ -1434,9 +1443,8 @@ struct amdgpu_device {
1434 /* GDS */ 1443 /* GDS */
1435 struct amdgpu_gds gds; 1444 struct amdgpu_gds gds;
1436 1445
1437 const struct amdgpu_ip_block_version *ip_blocks; 1446 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
1438 int num_ip_blocks; 1447 int num_ip_blocks;
1439 struct amdgpu_ip_block_status *ip_block_status;
1440 struct mutex mn_lock; 1448 struct mutex mn_lock;
1441 DECLARE_HASHTABLE(mn_hash, 7); 1449 DECLARE_HASHTABLE(mn_hash, 7);
1442 1450
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 892d60fb225b..2f9f96cc9f65 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -265,14 +265,14 @@ static int acp_hw_init(void *handle)
265 265
266 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 266 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
267 267
268 const struct amdgpu_ip_block_version *ip_version = 268 const struct amdgpu_ip_block *ip_block =
269 amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP); 269 amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP);
270 270
271 if (!ip_version) 271 if (!ip_block)
272 return -EINVAL; 272 return -EINVAL;
273 273
274 r = amd_acp_hw_init(adev->acp.cgs_device, 274 r = amd_acp_hw_init(adev->acp.cgs_device,
275 ip_version->major, ip_version->minor); 275 ip_block->version->major, ip_block->version->minor);
276 /* -ENODEV means board uses AZ rather than ACP */ 276 /* -ENODEV means board uses AZ rather than ACP */
277 if (r == -ENODEV) 277 if (r == -ENODEV)
278 return 0; 278 return 0;
@@ -456,7 +456,7 @@ static int acp_set_powergating_state(void *handle,
456 return 0; 456 return 0;
457} 457}
458 458
459const struct amd_ip_funcs acp_ip_funcs = { 459static const struct amd_ip_funcs acp_ip_funcs = {
460 .name = "acp_ip", 460 .name = "acp_ip",
461 .early_init = acp_early_init, 461 .early_init = acp_early_init,
462 .late_init = NULL, 462 .late_init = NULL,
@@ -472,3 +472,12 @@ const struct amd_ip_funcs acp_ip_funcs = {
472 .set_clockgating_state = acp_set_clockgating_state, 472 .set_clockgating_state = acp_set_clockgating_state,
473 .set_powergating_state = acp_set_powergating_state, 473 .set_powergating_state = acp_set_powergating_state,
474}; 474};
475
476const struct amdgpu_ip_block_version acp_ip_block =
477{
478 .type = AMD_IP_BLOCK_TYPE_ACP,
479 .major = 2,
480 .minor = 2,
481 .rev = 0,
482 .funcs = &acp_ip_funcs,
483};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h
index 8a396313c86f..a288ce25c176 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h
@@ -37,6 +37,6 @@ struct amdgpu_acp {
37 struct acp_pm_domain *acp_genpd; 37 struct acp_pm_domain *acp_genpd;
38}; 38};
39 39
40extern const struct amd_ip_funcs acp_ip_funcs; 40extern const struct amdgpu_ip_block_version acp_ip_block;
41 41
42#endif /* __AMDGPU_ACP_H__ */ 42#endif /* __AMDGPU_ACP_H__ */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 34049d67a0d8..017556ca22e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -626,11 +626,11 @@ static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device,
626 int i, r = -1; 626 int i, r = -1;
627 627
628 for (i = 0; i < adev->num_ip_blocks; i++) { 628 for (i = 0; i < adev->num_ip_blocks; i++) {
629 if (!adev->ip_block_status[i].valid) 629 if (!adev->ip_blocks[i].status.valid)
630 continue; 630 continue;
631 631
632 if (adev->ip_blocks[i].type == block_type) { 632 if (adev->ip_blocks[i].version->type == block_type) {
633 r = adev->ip_blocks[i].funcs->set_clockgating_state( 633 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
634 (void *)adev, 634 (void *)adev,
635 state); 635 state);
636 break; 636 break;
@@ -647,11 +647,11 @@ static int amdgpu_cgs_set_powergating_state(struct cgs_device *cgs_device,
647 int i, r = -1; 647 int i, r = -1;
648 648
649 for (i = 0; i < adev->num_ip_blocks; i++) { 649 for (i = 0; i < adev->num_ip_blocks; i++) {
650 if (!adev->ip_block_status[i].valid) 650 if (!adev->ip_blocks[i].status.valid)
651 continue; 651 continue;
652 652
653 if (adev->ip_blocks[i].type == block_type) { 653 if (adev->ip_blocks[i].version->type == block_type) {
654 r = adev->ip_blocks[i].funcs->set_powergating_state( 654 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
655 (void *)adev, 655 (void *)adev,
656 state); 656 state);
657 break; 657 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index afeb7ab16d09..27a729c70c29 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1133,11 +1133,11 @@ int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1133 int i, r = 0; 1133 int i, r = 0;
1134 1134
1135 for (i = 0; i < adev->num_ip_blocks; i++) { 1135 for (i = 0; i < adev->num_ip_blocks; i++) {
1136 if (!adev->ip_block_status[i].valid) 1136 if (!adev->ip_blocks[i].status.valid)
1137 continue; 1137 continue;
1138 if (adev->ip_blocks[i].type == block_type) { 1138 if (adev->ip_blocks[i].version->type == block_type) {
1139 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, 1139 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1140 state); 1140 state);
1141 if (r) 1141 if (r)
1142 return r; 1142 return r;
1143 break; 1143 break;
@@ -1153,11 +1153,11 @@ int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1153 int i, r = 0; 1153 int i, r = 0;
1154 1154
1155 for (i = 0; i < adev->num_ip_blocks; i++) { 1155 for (i = 0; i < adev->num_ip_blocks; i++) {
1156 if (!adev->ip_block_status[i].valid) 1156 if (!adev->ip_blocks[i].status.valid)
1157 continue; 1157 continue;
1158 if (adev->ip_blocks[i].type == block_type) { 1158 if (adev->ip_blocks[i].version->type == block_type) {
1159 r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev, 1159 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
1160 state); 1160 state);
1161 if (r) 1161 if (r)
1162 return r; 1162 return r;
1163 break; 1163 break;
@@ -1172,10 +1172,10 @@ int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1172 int i, r; 1172 int i, r;
1173 1173
1174 for (i = 0; i < adev->num_ip_blocks; i++) { 1174 for (i = 0; i < adev->num_ip_blocks; i++) {
1175 if (!adev->ip_block_status[i].valid) 1175 if (!adev->ip_blocks[i].status.valid)
1176 continue; 1176 continue;
1177 if (adev->ip_blocks[i].type == block_type) { 1177 if (adev->ip_blocks[i].version->type == block_type) {
1178 r = adev->ip_blocks[i].funcs->wait_for_idle((void *)adev); 1178 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1179 if (r) 1179 if (r)
1180 return r; 1180 return r;
1181 break; 1181 break;
@@ -1191,23 +1191,22 @@ bool amdgpu_is_idle(struct amdgpu_device *adev,
1191 int i; 1191 int i;
1192 1192
1193 for (i = 0; i < adev->num_ip_blocks; i++) { 1193 for (i = 0; i < adev->num_ip_blocks; i++) {
1194 if (!adev->ip_block_status[i].valid) 1194 if (!adev->ip_blocks[i].status.valid)
1195 continue; 1195 continue;
1196 if (adev->ip_blocks[i].type == block_type) 1196 if (adev->ip_blocks[i].version->type == block_type)
1197 return adev->ip_blocks[i].funcs->is_idle((void *)adev); 1197 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1198 } 1198 }
1199 return true; 1199 return true;
1200 1200
1201} 1201}
1202 1202
1203const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 1203struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
1204 struct amdgpu_device *adev, 1204 enum amd_ip_block_type type)
1205 enum amd_ip_block_type type)
1206{ 1205{
1207 int i; 1206 int i;
1208 1207
1209 for (i = 0; i < adev->num_ip_blocks; i++) 1208 for (i = 0; i < adev->num_ip_blocks; i++)
1210 if (adev->ip_blocks[i].type == type) 1209 if (adev->ip_blocks[i].version->type == type)
1211 return &adev->ip_blocks[i]; 1210 return &adev->ip_blocks[i];
1212 1211
1213 return NULL; 1212 return NULL;
@@ -1228,17 +1227,36 @@ int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1228 enum amd_ip_block_type type, 1227 enum amd_ip_block_type type,
1229 u32 major, u32 minor) 1228 u32 major, u32 minor)
1230{ 1229{
1231 const struct amdgpu_ip_block_version *ip_block; 1230 struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type);
1232 ip_block = amdgpu_get_ip_block(adev, type);
1233 1231
1234 if (ip_block && ((ip_block->major > major) || 1232 if (ip_block && ((ip_block->version->major > major) ||
1235 ((ip_block->major == major) && 1233 ((ip_block->version->major == major) &&
1236 (ip_block->minor >= minor)))) 1234 (ip_block->version->minor >= minor))))
1237 return 0; 1235 return 0;
1238 1236
1239 return 1; 1237 return 1;
1240} 1238}
1241 1239
1240/**
1241 * amdgpu_ip_block_add
1242 *
1243 * @adev: amdgpu_device pointer
1244 * @ip_block_version: pointer to the IP to add
1245 *
1246 * Adds the IP block driver information to the collection of IPs
1247 * on the asic.
1248 */
1249int amdgpu_ip_block_add(struct amdgpu_device *adev,
1250 const struct amdgpu_ip_block_version *ip_block_version)
1251{
1252 if (!ip_block_version)
1253 return -EINVAL;
1254
1255 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1256
1257 return 0;
1258}
1259
1242static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) 1260static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1243{ 1261{
1244 adev->enable_virtual_display = false; 1262 adev->enable_virtual_display = false;
@@ -1339,33 +1357,24 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
1339 return -EINVAL; 1357 return -EINVAL;
1340 } 1358 }
1341 1359
1342 adev->ip_block_status = kcalloc(adev->num_ip_blocks,
1343 sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
1344 if (adev->ip_block_status == NULL)
1345 return -ENOMEM;
1346
1347 if (adev->ip_blocks == NULL) {
1348 DRM_ERROR("No IP blocks found!\n");
1349 return r;
1350 }
1351
1352 for (i = 0; i < adev->num_ip_blocks; i++) { 1360 for (i = 0; i < adev->num_ip_blocks; i++) {
1353 if ((amdgpu_ip_block_mask & (1 << i)) == 0) { 1361 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1354 DRM_ERROR("disabled ip block: %d\n", i); 1362 DRM_ERROR("disabled ip block: %d\n", i);
1355 adev->ip_block_status[i].valid = false; 1363 adev->ip_blocks[i].status.valid = false;
1356 } else { 1364 } else {
1357 if (adev->ip_blocks[i].funcs->early_init) { 1365 if (adev->ip_blocks[i].version->funcs->early_init) {
1358 r = adev->ip_blocks[i].funcs->early_init((void *)adev); 1366 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1359 if (r == -ENOENT) { 1367 if (r == -ENOENT) {
1360 adev->ip_block_status[i].valid = false; 1368 adev->ip_blocks[i].status.valid = false;
1361 } else if (r) { 1369 } else if (r) {
1362 DRM_ERROR("early_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); 1370 DRM_ERROR("early_init of IP block <%s> failed %d\n",
1371 adev->ip_blocks[i].version->funcs->name, r);
1363 return r; 1372 return r;
1364 } else { 1373 } else {
1365 adev->ip_block_status[i].valid = true; 1374 adev->ip_blocks[i].status.valid = true;
1366 } 1375 }
1367 } else { 1376 } else {
1368 adev->ip_block_status[i].valid = true; 1377 adev->ip_blocks[i].status.valid = true;
1369 } 1378 }
1370 } 1379 }
1371 } 1380 }
@@ -1381,22 +1390,23 @@ static int amdgpu_init(struct amdgpu_device *adev)
1381 int i, r; 1390 int i, r;
1382 1391
1383 for (i = 0; i < adev->num_ip_blocks; i++) { 1392 for (i = 0; i < adev->num_ip_blocks; i++) {
1384 if (!adev->ip_block_status[i].valid) 1393 if (!adev->ip_blocks[i].status.valid)
1385 continue; 1394 continue;
1386 r = adev->ip_blocks[i].funcs->sw_init((void *)adev); 1395 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1387 if (r) { 1396 if (r) {
1388 DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); 1397 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1398 adev->ip_blocks[i].version->funcs->name, r);
1389 return r; 1399 return r;
1390 } 1400 }
1391 adev->ip_block_status[i].sw = true; 1401 adev->ip_blocks[i].status.sw = true;
1392 /* need to do gmc hw init early so we can allocate gpu mem */ 1402 /* need to do gmc hw init early so we can allocate gpu mem */
1393 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) { 1403 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1394 r = amdgpu_vram_scratch_init(adev); 1404 r = amdgpu_vram_scratch_init(adev);
1395 if (r) { 1405 if (r) {
1396 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); 1406 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1397 return r; 1407 return r;
1398 } 1408 }
1399 r = adev->ip_blocks[i].funcs->hw_init((void *)adev); 1409 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1400 if (r) { 1410 if (r) {
1401 DRM_ERROR("hw_init %d failed %d\n", i, r); 1411 DRM_ERROR("hw_init %d failed %d\n", i, r);
1402 return r; 1412 return r;
@@ -1406,22 +1416,23 @@ static int amdgpu_init(struct amdgpu_device *adev)
1406 DRM_ERROR("amdgpu_wb_init failed %d\n", r); 1416 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1407 return r; 1417 return r;
1408 } 1418 }
1409 adev->ip_block_status[i].hw = true; 1419 adev->ip_blocks[i].status.hw = true;
1410 } 1420 }
1411 } 1421 }
1412 1422
1413 for (i = 0; i < adev->num_ip_blocks; i++) { 1423 for (i = 0; i < adev->num_ip_blocks; i++) {
1414 if (!adev->ip_block_status[i].sw) 1424 if (!adev->ip_blocks[i].status.sw)
1415 continue; 1425 continue;
1416 /* gmc hw init is done early */ 1426 /* gmc hw init is done early */
1417 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) 1427 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC)
1418 continue; 1428 continue;
1419 r = adev->ip_blocks[i].funcs->hw_init((void *)adev); 1429 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1420 if (r) { 1430 if (r) {
1421 DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); 1431 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1432 adev->ip_blocks[i].version->funcs->name, r);
1422 return r; 1433 return r;
1423 } 1434 }
1424 adev->ip_block_status[i].hw = true; 1435 adev->ip_blocks[i].status.hw = true;
1425 } 1436 }
1426 1437
1427 return 0; 1438 return 0;
@@ -1432,25 +1443,26 @@ static int amdgpu_late_init(struct amdgpu_device *adev)
1432 int i = 0, r; 1443 int i = 0, r;
1433 1444
1434 for (i = 0; i < adev->num_ip_blocks; i++) { 1445 for (i = 0; i < adev->num_ip_blocks; i++) {
1435 if (!adev->ip_block_status[i].valid) 1446 if (!adev->ip_blocks[i].status.valid)
1436 continue; 1447 continue;
1437 if (adev->ip_blocks[i].funcs->late_init) { 1448 if (adev->ip_blocks[i].version->funcs->late_init) {
1438 r = adev->ip_blocks[i].funcs->late_init((void *)adev); 1449 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1439 if (r) { 1450 if (r) {
1440 DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); 1451 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1452 adev->ip_blocks[i].version->funcs->name, r);
1441 return r; 1453 return r;
1442 } 1454 }
1443 adev->ip_block_status[i].late_initialized = true; 1455 adev->ip_blocks[i].status.late_initialized = true;
1444 } 1456 }
1445 /* skip CG for VCE/UVD, it's handled specially */ 1457 /* skip CG for VCE/UVD, it's handled specially */
1446 if (adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_UVD && 1458 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1447 adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_VCE) { 1459 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1448 /* enable clockgating to save power */ 1460 /* enable clockgating to save power */
1449 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, 1461 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1450 AMD_CG_STATE_GATE); 1462 AMD_CG_STATE_GATE);
1451 if (r) { 1463 if (r) {
1452 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", 1464 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1453 adev->ip_blocks[i].funcs->name, r); 1465 adev->ip_blocks[i].version->funcs->name, r);
1454 return r; 1466 return r;
1455 } 1467 }
1456 } 1468 }
@@ -1465,68 +1477,71 @@ static int amdgpu_fini(struct amdgpu_device *adev)
1465 1477
1466 /* need to disable SMC first */ 1478 /* need to disable SMC first */
1467 for (i = 0; i < adev->num_ip_blocks; i++) { 1479 for (i = 0; i < adev->num_ip_blocks; i++) {
1468 if (!adev->ip_block_status[i].hw) 1480 if (!adev->ip_blocks[i].status.hw)
1469 continue; 1481 continue;
1470 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_SMC) { 1482 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1471 /* ungate blocks before hw fini so that we can shutdown the blocks safely */ 1483 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1472 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, 1484 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1473 AMD_CG_STATE_UNGATE); 1485 AMD_CG_STATE_UNGATE);
1474 if (r) { 1486 if (r) {
1475 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", 1487 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1476 adev->ip_blocks[i].funcs->name, r); 1488 adev->ip_blocks[i].version->funcs->name, r);
1477 return r; 1489 return r;
1478 } 1490 }
1479 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev); 1491 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1480 /* XXX handle errors */ 1492 /* XXX handle errors */
1481 if (r) { 1493 if (r) {
1482 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", 1494 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1483 adev->ip_blocks[i].funcs->name, r); 1495 adev->ip_blocks[i].version->funcs->name, r);
1484 } 1496 }
1485 adev->ip_block_status[i].hw = false; 1497 adev->ip_blocks[i].status.hw = false;
1486 break; 1498 break;
1487 } 1499 }
1488 } 1500 }
1489 1501
1490 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 1502 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1491 if (!adev->ip_block_status[i].hw) 1503 if (!adev->ip_blocks[i].status.hw)
1492 continue; 1504 continue;
1493 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) { 1505 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1494 amdgpu_wb_fini(adev); 1506 amdgpu_wb_fini(adev);
1495 amdgpu_vram_scratch_fini(adev); 1507 amdgpu_vram_scratch_fini(adev);
1496 } 1508 }
1497 /* ungate blocks before hw fini so that we can shutdown the blocks safely */ 1509 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1498 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, 1510 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1499 AMD_CG_STATE_UNGATE); 1511 AMD_CG_STATE_UNGATE);
1500 if (r) { 1512 if (r) {
1501 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); 1513 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1514 adev->ip_blocks[i].version->funcs->name, r);
1502 return r; 1515 return r;
1503 } 1516 }
1504 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev); 1517 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1505 /* XXX handle errors */ 1518 /* XXX handle errors */
1506 if (r) { 1519 if (r) {
1507 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); 1520 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1521 adev->ip_blocks[i].version->funcs->name, r);
1508 } 1522 }
1509 adev->ip_block_status[i].hw = false; 1523 adev->ip_blocks[i].status.hw = false;
1510 } 1524 }
1511 1525
1512 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 1526 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1513 if (!adev->ip_block_status[i].sw) 1527 if (!adev->ip_blocks[i].status.sw)
1514 continue; 1528 continue;
1515 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev); 1529 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1516 /* XXX handle errors */ 1530 /* XXX handle errors */
1517 if (r) { 1531 if (r) {
1518 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); 1532 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1533 adev->ip_blocks[i].version->funcs->name, r);
1519 } 1534 }
1520 adev->ip_block_status[i].sw = false; 1535 adev->ip_blocks[i].status.sw = false;
1521 adev->ip_block_status[i].valid = false; 1536 adev->ip_blocks[i].status.valid = false;
1522 } 1537 }
1523 1538
1524 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 1539 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1525 if (!adev->ip_block_status[i].late_initialized) 1540 if (!adev->ip_blocks[i].status.late_initialized)
1526 continue; 1541 continue;
1527 if (adev->ip_blocks[i].funcs->late_fini) 1542 if (adev->ip_blocks[i].version->funcs->late_fini)
1528 adev->ip_blocks[i].funcs->late_fini((void *)adev); 1543 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1529 adev->ip_block_status[i].late_initialized = false; 1544 adev->ip_blocks[i].status.late_initialized = false;
1530 } 1545 }
1531 1546
1532 return 0; 1547 return 0;
@@ -1544,21 +1559,23 @@ static int amdgpu_suspend(struct amdgpu_device *adev)
1544 } 1559 }
1545 1560
1546 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 1561 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1547 if (!adev->ip_block_status[i].valid) 1562 if (!adev->ip_blocks[i].status.valid)
1548 continue; 1563 continue;
1549 /* ungate blocks so that suspend can properly shut them down */ 1564 /* ungate blocks so that suspend can properly shut them down */
1550 if (i != AMD_IP_BLOCK_TYPE_SMC) { 1565 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1551 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, 1566 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1552 AMD_CG_STATE_UNGATE); 1567 AMD_CG_STATE_UNGATE);
1553 if (r) { 1568 if (r) {
1554 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); 1569 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1570 adev->ip_blocks[i].version->funcs->name, r);
1555 } 1571 }
1556 } 1572 }
1557 /* XXX handle errors */ 1573 /* XXX handle errors */
1558 r = adev->ip_blocks[i].funcs->suspend(adev); 1574 r = adev->ip_blocks[i].version->funcs->suspend(adev);
1559 /* XXX handle errors */ 1575 /* XXX handle errors */
1560 if (r) { 1576 if (r) {
1561 DRM_ERROR("suspend of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); 1577 DRM_ERROR("suspend of IP block <%s> failed %d\n",
1578 adev->ip_blocks[i].version->funcs->name, r);
1562 } 1579 }
1563 } 1580 }
1564 1581
@@ -1570,11 +1587,12 @@ static int amdgpu_resume(struct amdgpu_device *adev)
1570 int i, r; 1587 int i, r;
1571 1588
1572 for (i = 0; i < adev->num_ip_blocks; i++) { 1589 for (i = 0; i < adev->num_ip_blocks; i++) {
1573 if (!adev->ip_block_status[i].valid) 1590 if (!adev->ip_blocks[i].status.valid)
1574 continue; 1591 continue;
1575 r = adev->ip_blocks[i].funcs->resume(adev); 1592 r = adev->ip_blocks[i].version->funcs->resume(adev);
1576 if (r) { 1593 if (r) {
1577 DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); 1594 DRM_ERROR("resume of IP block <%s> failed %d\n",
1595 adev->ip_blocks[i].version->funcs->name, r);
1578 return r; 1596 return r;
1579 } 1597 }
1580 } 1598 }
@@ -1885,8 +1903,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
1885 amdgpu_fence_driver_fini(adev); 1903 amdgpu_fence_driver_fini(adev);
1886 amdgpu_fbdev_fini(adev); 1904 amdgpu_fbdev_fini(adev);
1887 r = amdgpu_fini(adev); 1905 r = amdgpu_fini(adev);
1888 kfree(adev->ip_block_status);
1889 adev->ip_block_status = NULL;
1890 adev->accel_working = false; 1906 adev->accel_working = false;
1891 /* free i2c buses */ 1907 /* free i2c buses */
1892 amdgpu_i2c_fini(adev); 1908 amdgpu_i2c_fini(adev);
@@ -2125,13 +2141,13 @@ static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
2125 bool asic_hang = false; 2141 bool asic_hang = false;
2126 2142
2127 for (i = 0; i < adev->num_ip_blocks; i++) { 2143 for (i = 0; i < adev->num_ip_blocks; i++) {
2128 if (!adev->ip_block_status[i].valid) 2144 if (!adev->ip_blocks[i].status.valid)
2129 continue; 2145 continue;
2130 if (adev->ip_blocks[i].funcs->check_soft_reset) 2146 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
2131 adev->ip_block_status[i].hang = 2147 adev->ip_blocks[i].status.hang =
2132 adev->ip_blocks[i].funcs->check_soft_reset(adev); 2148 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
2133 if (adev->ip_block_status[i].hang) { 2149 if (adev->ip_blocks[i].status.hang) {
2134 DRM_INFO("IP block:%d is hang!\n", i); 2150 DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
2135 asic_hang = true; 2151 asic_hang = true;
2136 } 2152 }
2137 } 2153 }
@@ -2143,11 +2159,11 @@ static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
2143 int i, r = 0; 2159 int i, r = 0;
2144 2160
2145 for (i = 0; i < adev->num_ip_blocks; i++) { 2161 for (i = 0; i < adev->num_ip_blocks; i++) {
2146 if (!adev->ip_block_status[i].valid) 2162 if (!adev->ip_blocks[i].status.valid)
2147 continue; 2163 continue;
2148 if (adev->ip_block_status[i].hang && 2164 if (adev->ip_blocks[i].status.hang &&
2149 adev->ip_blocks[i].funcs->pre_soft_reset) { 2165 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
2150 r = adev->ip_blocks[i].funcs->pre_soft_reset(adev); 2166 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
2151 if (r) 2167 if (r)
2152 return r; 2168 return r;
2153 } 2169 }
@@ -2161,13 +2177,13 @@ static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
2161 int i; 2177 int i;
2162 2178
2163 for (i = 0; i < adev->num_ip_blocks; i++) { 2179 for (i = 0; i < adev->num_ip_blocks; i++) {
2164 if (!adev->ip_block_status[i].valid) 2180 if (!adev->ip_blocks[i].status.valid)
2165 continue; 2181 continue;
2166 if ((adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) || 2182 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
2167 (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_SMC) || 2183 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
2168 (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_ACP) || 2184 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
2169 (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_DCE)) { 2185 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) {
2170 if (adev->ip_block_status[i].hang) { 2186 if (adev->ip_blocks[i].status.hang) {
2171 DRM_INFO("Some block need full reset!\n"); 2187 DRM_INFO("Some block need full reset!\n");
2172 return true; 2188 return true;
2173 } 2189 }
@@ -2181,11 +2197,11 @@ static int amdgpu_soft_reset(struct amdgpu_device *adev)
2181 int i, r = 0; 2197 int i, r = 0;
2182 2198
2183 for (i = 0; i < adev->num_ip_blocks; i++) { 2199 for (i = 0; i < adev->num_ip_blocks; i++) {
2184 if (!adev->ip_block_status[i].valid) 2200 if (!adev->ip_blocks[i].status.valid)
2185 continue; 2201 continue;
2186 if (adev->ip_block_status[i].hang && 2202 if (adev->ip_blocks[i].status.hang &&
2187 adev->ip_blocks[i].funcs->soft_reset) { 2203 adev->ip_blocks[i].version->funcs->soft_reset) {
2188 r = adev->ip_blocks[i].funcs->soft_reset(adev); 2204 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
2189 if (r) 2205 if (r)
2190 return r; 2206 return r;
2191 } 2207 }
@@ -2199,11 +2215,11 @@ static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
2199 int i, r = 0; 2215 int i, r = 0;
2200 2216
2201 for (i = 0; i < adev->num_ip_blocks; i++) { 2217 for (i = 0; i < adev->num_ip_blocks; i++) {
2202 if (!adev->ip_block_status[i].valid) 2218 if (!adev->ip_blocks[i].status.valid)
2203 continue; 2219 continue;
2204 if (adev->ip_block_status[i].hang && 2220 if (adev->ip_blocks[i].status.hang &&
2205 adev->ip_blocks[i].funcs->post_soft_reset) 2221 adev->ip_blocks[i].version->funcs->post_soft_reset)
2206 r = adev->ip_blocks[i].funcs->post_soft_reset(adev); 2222 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
2207 if (r) 2223 if (r)
2208 return r; 2224 return r;
2209 } 2225 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 3570124ed186..d17424663fe2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -306,10 +306,10 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
306 } 306 }
307 307
308 for (i = 0; i < adev->num_ip_blocks; i++) { 308 for (i = 0; i < adev->num_ip_blocks; i++) {
309 if (adev->ip_blocks[i].type == type && 309 if (adev->ip_blocks[i].version->type == type &&
310 adev->ip_block_status[i].valid) { 310 adev->ip_blocks[i].status.valid) {
311 ip.hw_ip_version_major = adev->ip_blocks[i].major; 311 ip.hw_ip_version_major = adev->ip_blocks[i].version->major;
312 ip.hw_ip_version_minor = adev->ip_blocks[i].minor; 312 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor;
313 ip.capabilities_flags = 0; 313 ip.capabilities_flags = 0;
314 ip.available_rings = ring_mask; 314 ip.available_rings = ring_mask;
315 ip.ib_start_alignment = ib_start_alignment; 315 ip.ib_start_alignment = ib_start_alignment;
@@ -345,8 +345,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
345 } 345 }
346 346
347 for (i = 0; i < adev->num_ip_blocks; i++) 347 for (i = 0; i < adev->num_ip_blocks; i++)
348 if (adev->ip_blocks[i].type == type && 348 if (adev->ip_blocks[i].version->type == type &&
349 adev->ip_block_status[i].valid && 349 adev->ip_blocks[i].status.valid &&
350 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 350 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
351 count++; 351 count++;
352 352
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index 7532ff822aa7..fa6baf31a35d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -299,7 +299,7 @@ static int amdgpu_pp_soft_reset(void *handle)
299 return ret; 299 return ret;
300} 300}
301 301
302const struct amd_ip_funcs amdgpu_pp_ip_funcs = { 302static const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
303 .name = "amdgpu_powerplay", 303 .name = "amdgpu_powerplay",
304 .early_init = amdgpu_pp_early_init, 304 .early_init = amdgpu_pp_early_init,
305 .late_init = amdgpu_pp_late_init, 305 .late_init = amdgpu_pp_late_init,
@@ -316,3 +316,12 @@ const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
316 .set_clockgating_state = amdgpu_pp_set_clockgating_state, 316 .set_clockgating_state = amdgpu_pp_set_clockgating_state,
317 .set_powergating_state = amdgpu_pp_set_powergating_state, 317 .set_powergating_state = amdgpu_pp_set_powergating_state,
318}; 318};
319
320const struct amdgpu_ip_block_version amdgpu_pp_ip_block =
321{
322 .type = AMD_IP_BLOCK_TYPE_SMC,
323 .major = 1,
324 .minor = 0,
325 .rev = 0,
326 .funcs = &amdgpu_pp_ip_funcs,
327};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h
index ee6ea6c98e4f..c0c4bfdcdb14 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h
@@ -28,6 +28,6 @@
28 28
29#include "amd_shared.h" 29#include "amd_shared.h"
30 30
31extern const struct amd_ip_funcs amdgpu_pp_ip_funcs; 31extern const struct amdgpu_ip_block_version amdgpu_pp_ip_block;
32 32
33#endif /* __AMDGPU_POWERPLAY_H__ */ 33#endif /* __AMDGPU_POWERPLAY_H__ */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index da66823eff1c..ded57dd538e2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -346,7 +346,7 @@ error:
346static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring) 346static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring)
347{ 347{
348 struct amdgpu_device *adev = ring->adev; 348 struct amdgpu_device *adev = ring->adev;
349 const struct amdgpu_ip_block_version *ip_block; 349 const struct amdgpu_ip_block *ip_block;
350 350
351 if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE) 351 if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
352 /* only compute rings */ 352 /* only compute rings */
@@ -356,10 +356,10 @@ static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring)
356 if (!ip_block) 356 if (!ip_block)
357 return false; 357 return false;
358 358
359 if (ip_block->major <= 7) { 359 if (ip_block->version->major <= 7) {
360 /* gfx7 has no workaround */ 360 /* gfx7 has no workaround */
361 return true; 361 return true;
362 } else if (ip_block->major == 8) { 362 } else if (ip_block->version->major == 8) {
363 if (adev->gfx.mec_fw_version >= 673) 363 if (adev->gfx.mec_fw_version >= 673)
364 /* gfx8 is fixed in MEC firmware 673 */ 364 /* gfx8 is fixed in MEC firmware 673 */
365 return false; 365 return false;
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 3f891076c070..885f08c3f496 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -6663,3 +6663,12 @@ static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev)
6663 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; 6663 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
6664 adev->pm.dpm.thermal.irq.funcs = &ci_dpm_irq_funcs; 6664 adev->pm.dpm.thermal.irq.funcs = &ci_dpm_irq_funcs;
6665} 6665}
6666
6667const struct amdgpu_ip_block_version ci_dpm_ip_block =
6668{
6669 .type = AMD_IP_BLOCK_TYPE_SMC,
6670 .major = 7,
6671 .minor = 0,
6672 .rev = 0,
6673 .funcs = &ci_dpm_ip_funcs,
6674};
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index a845b6a93b79..1b70f8fa4280 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1641,745 +1641,6 @@ static void cik_detect_hw_virtualization(struct amdgpu_device *adev)
1641 adev->virtualization.virtual_caps |= AMDGPU_PASSTHROUGH_MODE; 1641 adev->virtualization.virtual_caps |= AMDGPU_PASSTHROUGH_MODE;
1642} 1642}
1643 1643
1644static const struct amdgpu_ip_block_version bonaire_ip_blocks[] =
1645{
1646 /* ORDER MATTERS! */
1647 {
1648 .type = AMD_IP_BLOCK_TYPE_COMMON,
1649 .major = 1,
1650 .minor = 0,
1651 .rev = 0,
1652 .funcs = &cik_common_ip_funcs,
1653 },
1654 {
1655 .type = AMD_IP_BLOCK_TYPE_GMC,
1656 .major = 7,
1657 .minor = 0,
1658 .rev = 0,
1659 .funcs = &gmc_v7_0_ip_funcs,
1660 },
1661 {
1662 .type = AMD_IP_BLOCK_TYPE_IH,
1663 .major = 2,
1664 .minor = 0,
1665 .rev = 0,
1666 .funcs = &cik_ih_ip_funcs,
1667 },
1668 {
1669 .type = AMD_IP_BLOCK_TYPE_SMC,
1670 .major = 7,
1671 .minor = 0,
1672 .rev = 0,
1673 .funcs = &amdgpu_pp_ip_funcs,
1674 },
1675 {
1676 .type = AMD_IP_BLOCK_TYPE_DCE,
1677 .major = 8,
1678 .minor = 2,
1679 .rev = 0,
1680 .funcs = &dce_v8_0_ip_funcs,
1681 },
1682 {
1683 .type = AMD_IP_BLOCK_TYPE_GFX,
1684 .major = 7,
1685 .minor = 2,
1686 .rev = 0,
1687 .funcs = &gfx_v7_0_ip_funcs,
1688 },
1689 {
1690 .type = AMD_IP_BLOCK_TYPE_SDMA,
1691 .major = 2,
1692 .minor = 0,
1693 .rev = 0,
1694 .funcs = &cik_sdma_ip_funcs,
1695 },
1696 {
1697 .type = AMD_IP_BLOCK_TYPE_UVD,
1698 .major = 4,
1699 .minor = 2,
1700 .rev = 0,
1701 .funcs = &uvd_v4_2_ip_funcs,
1702 },
1703 {
1704 .type = AMD_IP_BLOCK_TYPE_VCE,
1705 .major = 2,
1706 .minor = 0,
1707 .rev = 0,
1708 .funcs = &vce_v2_0_ip_funcs,
1709 },
1710};
1711
1712static const struct amdgpu_ip_block_version bonaire_ip_blocks_vd[] =
1713{
1714 /* ORDER MATTERS! */
1715 {
1716 .type = AMD_IP_BLOCK_TYPE_COMMON,
1717 .major = 1,
1718 .minor = 0,
1719 .rev = 0,
1720 .funcs = &cik_common_ip_funcs,
1721 },
1722 {
1723 .type = AMD_IP_BLOCK_TYPE_GMC,
1724 .major = 7,
1725 .minor = 0,
1726 .rev = 0,
1727 .funcs = &gmc_v7_0_ip_funcs,
1728 },
1729 {
1730 .type = AMD_IP_BLOCK_TYPE_IH,
1731 .major = 2,
1732 .minor = 0,
1733 .rev = 0,
1734 .funcs = &cik_ih_ip_funcs,
1735 },
1736 {
1737 .type = AMD_IP_BLOCK_TYPE_SMC,
1738 .major = 7,
1739 .minor = 0,
1740 .rev = 0,
1741 .funcs = &amdgpu_pp_ip_funcs,
1742 },
1743 {
1744 .type = AMD_IP_BLOCK_TYPE_DCE,
1745 .major = 8,
1746 .minor = 2,
1747 .rev = 0,
1748 .funcs = &dce_virtual_ip_funcs,
1749 },
1750 {
1751 .type = AMD_IP_BLOCK_TYPE_GFX,
1752 .major = 7,
1753 .minor = 2,
1754 .rev = 0,
1755 .funcs = &gfx_v7_0_ip_funcs,
1756 },
1757 {
1758 .type = AMD_IP_BLOCK_TYPE_SDMA,
1759 .major = 2,
1760 .minor = 0,
1761 .rev = 0,
1762 .funcs = &cik_sdma_ip_funcs,
1763 },
1764 {
1765 .type = AMD_IP_BLOCK_TYPE_UVD,
1766 .major = 4,
1767 .minor = 2,
1768 .rev = 0,
1769 .funcs = &uvd_v4_2_ip_funcs,
1770 },
1771 {
1772 .type = AMD_IP_BLOCK_TYPE_VCE,
1773 .major = 2,
1774 .minor = 0,
1775 .rev = 0,
1776 .funcs = &vce_v2_0_ip_funcs,
1777 },
1778};
1779
1780static const struct amdgpu_ip_block_version hawaii_ip_blocks[] =
1781{
1782 /* ORDER MATTERS! */
1783 {
1784 .type = AMD_IP_BLOCK_TYPE_COMMON,
1785 .major = 1,
1786 .minor = 0,
1787 .rev = 0,
1788 .funcs = &cik_common_ip_funcs,
1789 },
1790 {
1791 .type = AMD_IP_BLOCK_TYPE_GMC,
1792 .major = 7,
1793 .minor = 0,
1794 .rev = 0,
1795 .funcs = &gmc_v7_0_ip_funcs,
1796 },
1797 {
1798 .type = AMD_IP_BLOCK_TYPE_IH,
1799 .major = 2,
1800 .minor = 0,
1801 .rev = 0,
1802 .funcs = &cik_ih_ip_funcs,
1803 },
1804 {
1805 .type = AMD_IP_BLOCK_TYPE_SMC,
1806 .major = 7,
1807 .minor = 0,
1808 .rev = 0,
1809 .funcs = &amdgpu_pp_ip_funcs,
1810 },
1811 {
1812 .type = AMD_IP_BLOCK_TYPE_DCE,
1813 .major = 8,
1814 .minor = 5,
1815 .rev = 0,
1816 .funcs = &dce_v8_0_ip_funcs,
1817 },
1818 {
1819 .type = AMD_IP_BLOCK_TYPE_GFX,
1820 .major = 7,
1821 .minor = 3,
1822 .rev = 0,
1823 .funcs = &gfx_v7_0_ip_funcs,
1824 },
1825 {
1826 .type = AMD_IP_BLOCK_TYPE_SDMA,
1827 .major = 2,
1828 .minor = 0,
1829 .rev = 0,
1830 .funcs = &cik_sdma_ip_funcs,
1831 },
1832 {
1833 .type = AMD_IP_BLOCK_TYPE_UVD,
1834 .major = 4,
1835 .minor = 2,
1836 .rev = 0,
1837 .funcs = &uvd_v4_2_ip_funcs,
1838 },
1839 {
1840 .type = AMD_IP_BLOCK_TYPE_VCE,
1841 .major = 2,
1842 .minor = 0,
1843 .rev = 0,
1844 .funcs = &vce_v2_0_ip_funcs,
1845 },
1846};
1847
1848static const struct amdgpu_ip_block_version hawaii_ip_blocks_vd[] =
1849{
1850 /* ORDER MATTERS! */
1851 {
1852 .type = AMD_IP_BLOCK_TYPE_COMMON,
1853 .major = 1,
1854 .minor = 0,
1855 .rev = 0,
1856 .funcs = &cik_common_ip_funcs,
1857 },
1858 {
1859 .type = AMD_IP_BLOCK_TYPE_GMC,
1860 .major = 7,
1861 .minor = 0,
1862 .rev = 0,
1863 .funcs = &gmc_v7_0_ip_funcs,
1864 },
1865 {
1866 .type = AMD_IP_BLOCK_TYPE_IH,
1867 .major = 2,
1868 .minor = 0,
1869 .rev = 0,
1870 .funcs = &cik_ih_ip_funcs,
1871 },
1872 {
1873 .type = AMD_IP_BLOCK_TYPE_SMC,
1874 .major = 7,
1875 .minor = 0,
1876 .rev = 0,
1877 .funcs = &amdgpu_pp_ip_funcs,
1878 },
1879 {
1880 .type = AMD_IP_BLOCK_TYPE_DCE,
1881 .major = 8,
1882 .minor = 5,
1883 .rev = 0,
1884 .funcs = &dce_virtual_ip_funcs,
1885 },
1886 {
1887 .type = AMD_IP_BLOCK_TYPE_GFX,
1888 .major = 7,
1889 .minor = 3,
1890 .rev = 0,
1891 .funcs = &gfx_v7_0_ip_funcs,
1892 },
1893 {
1894 .type = AMD_IP_BLOCK_TYPE_SDMA,
1895 .major = 2,
1896 .minor = 0,
1897 .rev = 0,
1898 .funcs = &cik_sdma_ip_funcs,
1899 },
1900 {
1901 .type = AMD_IP_BLOCK_TYPE_UVD,
1902 .major = 4,
1903 .minor = 2,
1904 .rev = 0,
1905 .funcs = &uvd_v4_2_ip_funcs,
1906 },
1907 {
1908 .type = AMD_IP_BLOCK_TYPE_VCE,
1909 .major = 2,
1910 .minor = 0,
1911 .rev = 0,
1912 .funcs = &vce_v2_0_ip_funcs,
1913 },
1914};
1915
1916static const struct amdgpu_ip_block_version kabini_ip_blocks[] =
1917{
1918 /* ORDER MATTERS! */
1919 {
1920 .type = AMD_IP_BLOCK_TYPE_COMMON,
1921 .major = 1,
1922 .minor = 0,
1923 .rev = 0,
1924 .funcs = &cik_common_ip_funcs,
1925 },
1926 {
1927 .type = AMD_IP_BLOCK_TYPE_GMC,
1928 .major = 7,
1929 .minor = 0,
1930 .rev = 0,
1931 .funcs = &gmc_v7_0_ip_funcs,
1932 },
1933 {
1934 .type = AMD_IP_BLOCK_TYPE_IH,
1935 .major = 2,
1936 .minor = 0,
1937 .rev = 0,
1938 .funcs = &cik_ih_ip_funcs,
1939 },
1940 {
1941 .type = AMD_IP_BLOCK_TYPE_SMC,
1942 .major = 7,
1943 .minor = 0,
1944 .rev = 0,
1945 .funcs = &amdgpu_pp_ip_funcs,
1946 },
1947 {
1948 .type = AMD_IP_BLOCK_TYPE_DCE,
1949 .major = 8,
1950 .minor = 3,
1951 .rev = 0,
1952 .funcs = &dce_v8_0_ip_funcs,
1953 },
1954 {
1955 .type = AMD_IP_BLOCK_TYPE_GFX,
1956 .major = 7,
1957 .minor = 2,
1958 .rev = 0,
1959 .funcs = &gfx_v7_0_ip_funcs,
1960 },
1961 {
1962 .type = AMD_IP_BLOCK_TYPE_SDMA,
1963 .major = 2,
1964 .minor = 0,
1965 .rev = 0,
1966 .funcs = &cik_sdma_ip_funcs,
1967 },
1968 {
1969 .type = AMD_IP_BLOCK_TYPE_UVD,
1970 .major = 4,
1971 .minor = 2,
1972 .rev = 0,
1973 .funcs = &uvd_v4_2_ip_funcs,
1974 },
1975 {
1976 .type = AMD_IP_BLOCK_TYPE_VCE,
1977 .major = 2,
1978 .minor = 0,
1979 .rev = 0,
1980 .funcs = &vce_v2_0_ip_funcs,
1981 },
1982};
1983
1984static const struct amdgpu_ip_block_version kabini_ip_blocks_vd[] =
1985{
1986 /* ORDER MATTERS! */
1987 {
1988 .type = AMD_IP_BLOCK_TYPE_COMMON,
1989 .major = 1,
1990 .minor = 0,
1991 .rev = 0,
1992 .funcs = &cik_common_ip_funcs,
1993 },
1994 {
1995 .type = AMD_IP_BLOCK_TYPE_GMC,
1996 .major = 7,
1997 .minor = 0,
1998 .rev = 0,
1999 .funcs = &gmc_v7_0_ip_funcs,
2000 },
2001 {
2002 .type = AMD_IP_BLOCK_TYPE_IH,
2003 .major = 2,
2004 .minor = 0,
2005 .rev = 0,
2006 .funcs = &cik_ih_ip_funcs,
2007 },
2008 {
2009 .type = AMD_IP_BLOCK_TYPE_SMC,
2010 .major = 7,
2011 .minor = 0,
2012 .rev = 0,
2013 .funcs = &amdgpu_pp_ip_funcs,
2014 },
2015 {
2016 .type = AMD_IP_BLOCK_TYPE_DCE,
2017 .major = 8,
2018 .minor = 3,
2019 .rev = 0,
2020 .funcs = &dce_virtual_ip_funcs,
2021 },
2022 {
2023 .type = AMD_IP_BLOCK_TYPE_GFX,
2024 .major = 7,
2025 .minor = 2,
2026 .rev = 0,
2027 .funcs = &gfx_v7_0_ip_funcs,
2028 },
2029 {
2030 .type = AMD_IP_BLOCK_TYPE_SDMA,
2031 .major = 2,
2032 .minor = 0,
2033 .rev = 0,
2034 .funcs = &cik_sdma_ip_funcs,
2035 },
2036 {
2037 .type = AMD_IP_BLOCK_TYPE_UVD,
2038 .major = 4,
2039 .minor = 2,
2040 .rev = 0,
2041 .funcs = &uvd_v4_2_ip_funcs,
2042 },
2043 {
2044 .type = AMD_IP_BLOCK_TYPE_VCE,
2045 .major = 2,
2046 .minor = 0,
2047 .rev = 0,
2048 .funcs = &vce_v2_0_ip_funcs,
2049 },
2050};
2051
2052static const struct amdgpu_ip_block_version mullins_ip_blocks[] =
2053{
2054 /* ORDER MATTERS! */
2055 {
2056 .type = AMD_IP_BLOCK_TYPE_COMMON,
2057 .major = 1,
2058 .minor = 0,
2059 .rev = 0,
2060 .funcs = &cik_common_ip_funcs,
2061 },
2062 {
2063 .type = AMD_IP_BLOCK_TYPE_GMC,
2064 .major = 7,
2065 .minor = 0,
2066 .rev = 0,
2067 .funcs = &gmc_v7_0_ip_funcs,
2068 },
2069 {
2070 .type = AMD_IP_BLOCK_TYPE_IH,
2071 .major = 2,
2072 .minor = 0,
2073 .rev = 0,
2074 .funcs = &cik_ih_ip_funcs,
2075 },
2076 {
2077 .type = AMD_IP_BLOCK_TYPE_SMC,
2078 .major = 7,
2079 .minor = 0,
2080 .rev = 0,
2081 .funcs = &amdgpu_pp_ip_funcs,
2082 },
2083 {
2084 .type = AMD_IP_BLOCK_TYPE_DCE,
2085 .major = 8,
2086 .minor = 3,
2087 .rev = 0,
2088 .funcs = &dce_v8_0_ip_funcs,
2089 },
2090 {
2091 .type = AMD_IP_BLOCK_TYPE_GFX,
2092 .major = 7,
2093 .minor = 2,
2094 .rev = 0,
2095 .funcs = &gfx_v7_0_ip_funcs,
2096 },
2097 {
2098 .type = AMD_IP_BLOCK_TYPE_SDMA,
2099 .major = 2,
2100 .minor = 0,
2101 .rev = 0,
2102 .funcs = &cik_sdma_ip_funcs,
2103 },
2104 {
2105 .type = AMD_IP_BLOCK_TYPE_UVD,
2106 .major = 4,
2107 .minor = 2,
2108 .rev = 0,
2109 .funcs = &uvd_v4_2_ip_funcs,
2110 },
2111 {
2112 .type = AMD_IP_BLOCK_TYPE_VCE,
2113 .major = 2,
2114 .minor = 0,
2115 .rev = 0,
2116 .funcs = &vce_v2_0_ip_funcs,
2117 },
2118};
2119
2120static const struct amdgpu_ip_block_version mullins_ip_blocks_vd[] =
2121{
2122 /* ORDER MATTERS! */
2123 {
2124 .type = AMD_IP_BLOCK_TYPE_COMMON,
2125 .major = 1,
2126 .minor = 0,
2127 .rev = 0,
2128 .funcs = &cik_common_ip_funcs,
2129 },
2130 {
2131 .type = AMD_IP_BLOCK_TYPE_GMC,
2132 .major = 7,
2133 .minor = 0,
2134 .rev = 0,
2135 .funcs = &gmc_v7_0_ip_funcs,
2136 },
2137 {
2138 .type = AMD_IP_BLOCK_TYPE_IH,
2139 .major = 2,
2140 .minor = 0,
2141 .rev = 0,
2142 .funcs = &cik_ih_ip_funcs,
2143 },
2144 {
2145 .type = AMD_IP_BLOCK_TYPE_SMC,
2146 .major = 7,
2147 .minor = 0,
2148 .rev = 0,
2149 .funcs = &amdgpu_pp_ip_funcs,
2150 },
2151 {
2152 .type = AMD_IP_BLOCK_TYPE_DCE,
2153 .major = 8,
2154 .minor = 3,
2155 .rev = 0,
2156 .funcs = &dce_virtual_ip_funcs,
2157 },
2158 {
2159 .type = AMD_IP_BLOCK_TYPE_GFX,
2160 .major = 7,
2161 .minor = 2,
2162 .rev = 0,
2163 .funcs = &gfx_v7_0_ip_funcs,
2164 },
2165 {
2166 .type = AMD_IP_BLOCK_TYPE_SDMA,
2167 .major = 2,
2168 .minor = 0,
2169 .rev = 0,
2170 .funcs = &cik_sdma_ip_funcs,
2171 },
2172 {
2173 .type = AMD_IP_BLOCK_TYPE_UVD,
2174 .major = 4,
2175 .minor = 2,
2176 .rev = 0,
2177 .funcs = &uvd_v4_2_ip_funcs,
2178 },
2179 {
2180 .type = AMD_IP_BLOCK_TYPE_VCE,
2181 .major = 2,
2182 .minor = 0,
2183 .rev = 0,
2184 .funcs = &vce_v2_0_ip_funcs,
2185 },
2186};
2187
2188static const struct amdgpu_ip_block_version kaveri_ip_blocks[] =
2189{
2190 /* ORDER MATTERS! */
2191 {
2192 .type = AMD_IP_BLOCK_TYPE_COMMON,
2193 .major = 1,
2194 .minor = 0,
2195 .rev = 0,
2196 .funcs = &cik_common_ip_funcs,
2197 },
2198 {
2199 .type = AMD_IP_BLOCK_TYPE_GMC,
2200 .major = 7,
2201 .minor = 0,
2202 .rev = 0,
2203 .funcs = &gmc_v7_0_ip_funcs,
2204 },
2205 {
2206 .type = AMD_IP_BLOCK_TYPE_IH,
2207 .major = 2,
2208 .minor = 0,
2209 .rev = 0,
2210 .funcs = &cik_ih_ip_funcs,
2211 },
2212 {
2213 .type = AMD_IP_BLOCK_TYPE_SMC,
2214 .major = 7,
2215 .minor = 0,
2216 .rev = 0,
2217 .funcs = &amdgpu_pp_ip_funcs,
2218 },
2219 {
2220 .type = AMD_IP_BLOCK_TYPE_DCE,
2221 .major = 8,
2222 .minor = 1,
2223 .rev = 0,
2224 .funcs = &dce_v8_0_ip_funcs,
2225 },
2226 {
2227 .type = AMD_IP_BLOCK_TYPE_GFX,
2228 .major = 7,
2229 .minor = 1,
2230 .rev = 0,
2231 .funcs = &gfx_v7_0_ip_funcs,
2232 },
2233 {
2234 .type = AMD_IP_BLOCK_TYPE_SDMA,
2235 .major = 2,
2236 .minor = 0,
2237 .rev = 0,
2238 .funcs = &cik_sdma_ip_funcs,
2239 },
2240 {
2241 .type = AMD_IP_BLOCK_TYPE_UVD,
2242 .major = 4,
2243 .minor = 2,
2244 .rev = 0,
2245 .funcs = &uvd_v4_2_ip_funcs,
2246 },
2247 {
2248 .type = AMD_IP_BLOCK_TYPE_VCE,
2249 .major = 2,
2250 .minor = 0,
2251 .rev = 0,
2252 .funcs = &vce_v2_0_ip_funcs,
2253 },
2254};
2255
2256static const struct amdgpu_ip_block_version kaveri_ip_blocks_vd[] =
2257{
2258 /* ORDER MATTERS! */
2259 {
2260 .type = AMD_IP_BLOCK_TYPE_COMMON,
2261 .major = 1,
2262 .minor = 0,
2263 .rev = 0,
2264 .funcs = &cik_common_ip_funcs,
2265 },
2266 {
2267 .type = AMD_IP_BLOCK_TYPE_GMC,
2268 .major = 7,
2269 .minor = 0,
2270 .rev = 0,
2271 .funcs = &gmc_v7_0_ip_funcs,
2272 },
2273 {
2274 .type = AMD_IP_BLOCK_TYPE_IH,
2275 .major = 2,
2276 .minor = 0,
2277 .rev = 0,
2278 .funcs = &cik_ih_ip_funcs,
2279 },
2280 {
2281 .type = AMD_IP_BLOCK_TYPE_SMC,
2282 .major = 7,
2283 .minor = 0,
2284 .rev = 0,
2285 .funcs = &amdgpu_pp_ip_funcs,
2286 },
2287 {
2288 .type = AMD_IP_BLOCK_TYPE_DCE,
2289 .major = 8,
2290 .minor = 1,
2291 .rev = 0,
2292 .funcs = &dce_virtual_ip_funcs,
2293 },
2294 {
2295 .type = AMD_IP_BLOCK_TYPE_GFX,
2296 .major = 7,
2297 .minor = 1,
2298 .rev = 0,
2299 .funcs = &gfx_v7_0_ip_funcs,
2300 },
2301 {
2302 .type = AMD_IP_BLOCK_TYPE_SDMA,
2303 .major = 2,
2304 .minor = 0,
2305 .rev = 0,
2306 .funcs = &cik_sdma_ip_funcs,
2307 },
2308 {
2309 .type = AMD_IP_BLOCK_TYPE_UVD,
2310 .major = 4,
2311 .minor = 2,
2312 .rev = 0,
2313 .funcs = &uvd_v4_2_ip_funcs,
2314 },
2315 {
2316 .type = AMD_IP_BLOCK_TYPE_VCE,
2317 .major = 2,
2318 .minor = 0,
2319 .rev = 0,
2320 .funcs = &vce_v2_0_ip_funcs,
2321 },
2322};
2323
2324int cik_set_ip_blocks(struct amdgpu_device *adev)
2325{
2326 if (adev->enable_virtual_display) {
2327 switch (adev->asic_type) {
2328 case CHIP_BONAIRE:
2329 adev->ip_blocks = bonaire_ip_blocks_vd;
2330 adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks_vd);
2331 break;
2332 case CHIP_HAWAII:
2333 adev->ip_blocks = hawaii_ip_blocks_vd;
2334 adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks_vd);
2335 break;
2336 case CHIP_KAVERI:
2337 adev->ip_blocks = kaveri_ip_blocks_vd;
2338 adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks_vd);
2339 break;
2340 case CHIP_KABINI:
2341 adev->ip_blocks = kabini_ip_blocks_vd;
2342 adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks_vd);
2343 break;
2344 case CHIP_MULLINS:
2345 adev->ip_blocks = mullins_ip_blocks_vd;
2346 adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks_vd);
2347 break;
2348 default:
2349 /* FIXME: not supported yet */
2350 return -EINVAL;
2351 }
2352 } else {
2353 switch (adev->asic_type) {
2354 case CHIP_BONAIRE:
2355 adev->ip_blocks = bonaire_ip_blocks;
2356 adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks);
2357 break;
2358 case CHIP_HAWAII:
2359 adev->ip_blocks = hawaii_ip_blocks;
2360 adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks);
2361 break;
2362 case CHIP_KAVERI:
2363 adev->ip_blocks = kaveri_ip_blocks;
2364 adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks);
2365 break;
2366 case CHIP_KABINI:
2367 adev->ip_blocks = kabini_ip_blocks;
2368 adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks);
2369 break;
2370 case CHIP_MULLINS:
2371 adev->ip_blocks = mullins_ip_blocks;
2372 adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks);
2373 break;
2374 default:
2375 /* FIXME: not supported yet */
2376 return -EINVAL;
2377 }
2378 }
2379
2380 return 0;
2381}
2382
2383static const struct amdgpu_asic_funcs cik_asic_funcs = 1644static const struct amdgpu_asic_funcs cik_asic_funcs =
2384{ 1645{
2385 .read_disabled_bios = &cik_read_disabled_bios, 1646 .read_disabled_bios = &cik_read_disabled_bios,
@@ -2612,7 +1873,7 @@ static int cik_common_set_powergating_state(void *handle,
2612 return 0; 1873 return 0;
2613} 1874}
2614 1875
2615const struct amd_ip_funcs cik_common_ip_funcs = { 1876static const struct amd_ip_funcs cik_common_ip_funcs = {
2616 .name = "cik_common", 1877 .name = "cik_common",
2617 .early_init = cik_common_early_init, 1878 .early_init = cik_common_early_init,
2618 .late_init = NULL, 1879 .late_init = NULL,
@@ -2628,3 +1889,79 @@ const struct amd_ip_funcs cik_common_ip_funcs = {
2628 .set_clockgating_state = cik_common_set_clockgating_state, 1889 .set_clockgating_state = cik_common_set_clockgating_state,
2629 .set_powergating_state = cik_common_set_powergating_state, 1890 .set_powergating_state = cik_common_set_powergating_state,
2630}; 1891};
1892
1893static const struct amdgpu_ip_block_version cik_common_ip_block =
1894{
1895 .type = AMD_IP_BLOCK_TYPE_COMMON,
1896 .major = 1,
1897 .minor = 0,
1898 .rev = 0,
1899 .funcs = &cik_common_ip_funcs,
1900};
1901
1902int cik_set_ip_blocks(struct amdgpu_device *adev)
1903{
1904 switch (adev->asic_type) {
1905 case CHIP_BONAIRE:
1906 amdgpu_ip_block_add(adev, &cik_common_ip_block);
1907 amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
1908 amdgpu_ip_block_add(adev, &cik_ih_ip_block);
1909 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1910 if (adev->enable_virtual_display)
1911 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1912 else
1913 amdgpu_ip_block_add(adev, &dce_v8_2_ip_block);
1914 amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block);
1915 amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
1916 amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
1917 amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
1918 break;
1919 case CHIP_HAWAII:
1920 amdgpu_ip_block_add(adev, &cik_common_ip_block);
1921 amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
1922 amdgpu_ip_block_add(adev, &cik_ih_ip_block);
1923 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1924 if (adev->enable_virtual_display)
1925 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1926 else
1927 amdgpu_ip_block_add(adev, &dce_v8_5_ip_block);
1928 amdgpu_ip_block_add(adev, &gfx_v7_3_ip_block);
1929 amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
1930 amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
1931 amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
1932 break;
1933 case CHIP_KAVERI:
1934 amdgpu_ip_block_add(adev, &cik_common_ip_block);
1935 amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
1936 amdgpu_ip_block_add(adev, &cik_ih_ip_block);
1937 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1938 if (adev->enable_virtual_display)
1939 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1940 else
1941 amdgpu_ip_block_add(adev, &dce_v8_1_ip_block);
1942 amdgpu_ip_block_add(adev, &gfx_v7_1_ip_block);
1943 amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
1944 amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
1945 amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
1946 break;
1947 case CHIP_KABINI:
1948 case CHIP_MULLINS:
1949 amdgpu_ip_block_add(adev, &cik_common_ip_block);
1950 amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
1951 amdgpu_ip_block_add(adev, &cik_ih_ip_block);
1952 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1953 if (adev->enable_virtual_display)
1954 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1955 else
1956 amdgpu_ip_block_add(adev, &dce_v8_3_ip_block);
1957 amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block);
1958 amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
1959 amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
1960 amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
1961 break;
1962 default:
1963 /* FIXME: not supported yet */
1964 return -EINVAL;
1965 }
1966 return 0;
1967}
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.h b/drivers/gpu/drm/amd/amdgpu/cik.h
index 5ebd2d7a0327..c4989f51ecef 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.h
+++ b/drivers/gpu/drm/amd/amdgpu/cik.h
@@ -24,8 +24,6 @@
24#ifndef __CIK_H__ 24#ifndef __CIK_H__
25#define __CIK_H__ 25#define __CIK_H__
26 26
27extern const struct amd_ip_funcs cik_common_ip_funcs;
28
29void cik_srbm_select(struct amdgpu_device *adev, 27void cik_srbm_select(struct amdgpu_device *adev,
30 u32 me, u32 pipe, u32 queue, u32 vmid); 28 u32 me, u32 pipe, u32 queue, u32 vmid);
31int cik_set_ip_blocks(struct amdgpu_device *adev); 29int cik_set_ip_blocks(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index be3d6f79a864..319b32cdea84 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -413,7 +413,7 @@ static int cik_ih_set_powergating_state(void *handle,
413 return 0; 413 return 0;
414} 414}
415 415
416const struct amd_ip_funcs cik_ih_ip_funcs = { 416static const struct amd_ip_funcs cik_ih_ip_funcs = {
417 .name = "cik_ih", 417 .name = "cik_ih",
418 .early_init = cik_ih_early_init, 418 .early_init = cik_ih_early_init,
419 .late_init = NULL, 419 .late_init = NULL,
@@ -441,3 +441,12 @@ static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev)
441 if (adev->irq.ih_funcs == NULL) 441 if (adev->irq.ih_funcs == NULL)
442 adev->irq.ih_funcs = &cik_ih_funcs; 442 adev->irq.ih_funcs = &cik_ih_funcs;
443} 443}
444
445const struct amdgpu_ip_block_version cik_ih_ip_block =
446{
447 .type = AMD_IP_BLOCK_TYPE_IH,
448 .major = 2,
449 .minor = 0,
450 .rev = 0,
451 .funcs = &cik_ih_ip_funcs,
452};
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.h b/drivers/gpu/drm/amd/amdgpu/cik_ih.h
index 6b0f375ec244..1d9ddee2868e 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.h
@@ -24,6 +24,6 @@
24#ifndef __CIK_IH_H__ 24#ifndef __CIK_IH_H__
25#define __CIK_IH_H__ 25#define __CIK_IH_H__
26 26
27extern const struct amd_ip_funcs cik_ih_ip_funcs; 27extern const struct amdgpu_ip_block_version cik_ih_ip_block;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index b96ef20e871f..c7340b6e17c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -1190,7 +1190,7 @@ static int cik_sdma_set_powergating_state(void *handle,
1190 return 0; 1190 return 0;
1191} 1191}
1192 1192
1193const struct amd_ip_funcs cik_sdma_ip_funcs = { 1193static const struct amd_ip_funcs cik_sdma_ip_funcs = {
1194 .name = "cik_sdma", 1194 .name = "cik_sdma",
1195 .early_init = cik_sdma_early_init, 1195 .early_init = cik_sdma_early_init,
1196 .late_init = NULL, 1196 .late_init = NULL,
@@ -1342,3 +1342,12 @@ static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1342 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 1342 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1343 } 1343 }
1344} 1344}
1345
1346const struct amdgpu_ip_block_version cik_sdma_ip_block =
1347{
1348 .type = AMD_IP_BLOCK_TYPE_SDMA,
1349 .major = 2,
1350 .minor = 0,
1351 .rev = 0,
1352 .funcs = &cik_sdma_ip_funcs,
1353};
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.h b/drivers/gpu/drm/amd/amdgpu/cik_sdma.h
index 027727c677b8..a4a8fe01410b 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.h
@@ -24,6 +24,6 @@
24#ifndef __CIK_SDMA_H__ 24#ifndef __CIK_SDMA_H__
25#define __CIK_SDMA_H__ 25#define __CIK_SDMA_H__
26 26
27extern const struct amd_ip_funcs cik_sdma_ip_funcs; 27extern const struct amdgpu_ip_block_version cik_sdma_ip_block;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
index 3c082e143730..ad2cc4be6737 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
@@ -2296,3 +2296,12 @@ static void cz_dpm_set_funcs(struct amdgpu_device *adev)
2296 if (NULL == adev->pm.funcs) 2296 if (NULL == adev->pm.funcs)
2297 adev->pm.funcs = &cz_dpm_funcs; 2297 adev->pm.funcs = &cz_dpm_funcs;
2298} 2298}
2299
2300const struct amdgpu_ip_block_version cz_dpm_ip_block =
2301{
2302 .type = AMD_IP_BLOCK_TYPE_SMC,
2303 .major = 8,
2304 .minor = 0,
2305 .rev = 0,
2306 .funcs = &cz_dpm_ip_funcs,
2307};
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index 3d23a70b6432..fe7cbb24da7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -394,7 +394,7 @@ static int cz_ih_set_powergating_state(void *handle,
394 return 0; 394 return 0;
395} 395}
396 396
397const struct amd_ip_funcs cz_ih_ip_funcs = { 397static const struct amd_ip_funcs cz_ih_ip_funcs = {
398 .name = "cz_ih", 398 .name = "cz_ih",
399 .early_init = cz_ih_early_init, 399 .early_init = cz_ih_early_init,
400 .late_init = NULL, 400 .late_init = NULL,
@@ -423,3 +423,11 @@ static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev)
423 adev->irq.ih_funcs = &cz_ih_funcs; 423 adev->irq.ih_funcs = &cz_ih_funcs;
424} 424}
425 425
426const struct amdgpu_ip_block_version cz_ih_ip_block =
427{
428 .type = AMD_IP_BLOCK_TYPE_IH,
429 .major = 3,
430 .minor = 0,
431 .rev = 0,
432 .funcs = &cz_ih_ip_funcs,
433};
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.h b/drivers/gpu/drm/amd/amdgpu/cz_ih.h
index fc4057a2ecb9..14be7753221b 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.h
@@ -24,6 +24,6 @@
24#ifndef __CZ_IH_H__ 24#ifndef __CZ_IH_H__
25#define __CZ_IH_H__ 25#define __CZ_IH_H__
26 26
27extern const struct amd_ip_funcs cz_ih_ip_funcs; 27extern const struct amdgpu_ip_block_version cz_ih_ip_block;
28 28
29#endif /* __CZ_IH_H__ */ 29#endif /* __CZ_IH_H__ */
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 15c38331a319..e5d0edfb4309 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -3470,7 +3470,7 @@ static int dce_v10_0_set_powergating_state(void *handle,
3470 return 0; 3470 return 0;
3471} 3471}
3472 3472
3473const struct amd_ip_funcs dce_v10_0_ip_funcs = { 3473static const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3474 .name = "dce_v10_0", 3474 .name = "dce_v10_0",
3475 .early_init = dce_v10_0_early_init, 3475 .early_init = dce_v10_0_early_init,
3476 .late_init = NULL, 3476 .late_init = NULL,
@@ -3801,3 +3801,21 @@ static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3801 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; 3801 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3802 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs; 3802 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3803} 3803}
3804
3805const struct amdgpu_ip_block_version dce_v10_0_ip_block =
3806{
3807 .type = AMD_IP_BLOCK_TYPE_DCE,
3808 .major = 10,
3809 .minor = 0,
3810 .rev = 0,
3811 .funcs = &dce_v10_0_ip_funcs,
3812};
3813
3814const struct amdgpu_ip_block_version dce_v10_1_ip_block =
3815{
3816 .type = AMD_IP_BLOCK_TYPE_DCE,
3817 .major = 10,
3818 .minor = 1,
3819 .rev = 0,
3820 .funcs = &dce_v10_0_ip_funcs,
3821};
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h
index e3dc04d293e4..7a0747789f1d 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h
@@ -24,7 +24,9 @@
24#ifndef __DCE_V10_0_H__ 24#ifndef __DCE_V10_0_H__
25#define __DCE_V10_0_H__ 25#define __DCE_V10_0_H__
26 26
27extern const struct amd_ip_funcs dce_v10_0_ip_funcs; 27
28extern const struct amdgpu_ip_block_version dce_v10_0_ip_block;
29extern const struct amdgpu_ip_block_version dce_v10_1_ip_block;
28 30
29void dce_v10_0_disable_dce(struct amdgpu_device *adev); 31void dce_v10_0_disable_dce(struct amdgpu_device *adev);
30 32
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 2696428bed05..9719b2b14186 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -3527,7 +3527,7 @@ static int dce_v11_0_set_powergating_state(void *handle,
3527 return 0; 3527 return 0;
3528} 3528}
3529 3529
3530const struct amd_ip_funcs dce_v11_0_ip_funcs = { 3530static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3531 .name = "dce_v11_0", 3531 .name = "dce_v11_0",
3532 .early_init = dce_v11_0_early_init, 3532 .early_init = dce_v11_0_early_init,
3533 .late_init = NULL, 3533 .late_init = NULL,
@@ -3857,3 +3857,21 @@ static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3857 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; 3857 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3858 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs; 3858 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3859} 3859}
3860
3861const struct amdgpu_ip_block_version dce_v11_0_ip_block =
3862{
3863 .type = AMD_IP_BLOCK_TYPE_DCE,
3864 .major = 11,
3865 .minor = 0,
3866 .rev = 0,
3867 .funcs = &dce_v11_0_ip_funcs,
3868};
3869
3870const struct amdgpu_ip_block_version dce_v11_2_ip_block =
3871{
3872 .type = AMD_IP_BLOCK_TYPE_DCE,
3873 .major = 11,
3874 .minor = 2,
3875 .rev = 0,
3876 .funcs = &dce_v11_0_ip_funcs,
3877};
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h
index 1f58a65ba2ef..0d878ca3acba 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h
@@ -24,7 +24,8 @@
24#ifndef __DCE_V11_0_H__ 24#ifndef __DCE_V11_0_H__
25#define __DCE_V11_0_H__ 25#define __DCE_V11_0_H__
26 26
27extern const struct amd_ip_funcs dce_v11_0_ip_funcs; 27extern const struct amdgpu_ip_block_version dce_v11_0_ip_block;
28extern const struct amdgpu_ip_block_version dce_v11_2_ip_block;
28 29
29void dce_v11_0_disable_dce(struct amdgpu_device *adev); 30void dce_v11_0_disable_dce(struct amdgpu_device *adev);
30 31
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 502e97963d6d..44547f951d92 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -2734,7 +2734,7 @@ static int dce_v6_0_set_powergating_state(void *handle,
2734 return 0; 2734 return 0;
2735} 2735}
2736 2736
2737const struct amd_ip_funcs dce_v6_0_ip_funcs = { 2737static const struct amd_ip_funcs dce_v6_0_ip_funcs = {
2738 .name = "dce_v6_0", 2738 .name = "dce_v6_0",
2739 .early_init = dce_v6_0_early_init, 2739 .early_init = dce_v6_0_early_init,
2740 .late_init = NULL, 2740 .late_init = NULL,
@@ -3075,3 +3075,21 @@ static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3075 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; 3075 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3076 adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs; 3076 adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs;
3077} 3077}
3078
3079const struct amdgpu_ip_block_version dce_v6_0_ip_block =
3080{
3081 .type = AMD_IP_BLOCK_TYPE_DCE,
3082 .major = 6,
3083 .minor = 0,
3084 .rev = 0,
3085 .funcs = &dce_v6_0_ip_funcs,
3086};
3087
3088const struct amdgpu_ip_block_version dce_v6_4_ip_block =
3089{
3090 .type = AMD_IP_BLOCK_TYPE_DCE,
3091 .major = 6,
3092 .minor = 4,
3093 .rev = 0,
3094 .funcs = &dce_v6_0_ip_funcs,
3095};
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
index 4c6cd18e9053..7b546b596de1 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
@@ -24,7 +24,8 @@
24#ifndef __DCE_V6_0_H__ 24#ifndef __DCE_V6_0_H__
25#define __DCE_V6_0_H__ 25#define __DCE_V6_0_H__
26 26
27extern const struct amd_ip_funcs dce_v6_0_ip_funcs; 27extern const struct amdgpu_ip_block_version dce_v6_0_ip_block;
28extern const struct amdgpu_ip_block_version dce_v6_4_ip_block;
28 29
29void dce_v6_0_disable_dce(struct amdgpu_device *adev); 30void dce_v6_0_disable_dce(struct amdgpu_device *adev);
30 31
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 0245ed605107..16a2f1faaf19 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -3308,7 +3308,7 @@ static int dce_v8_0_set_powergating_state(void *handle,
3308 return 0; 3308 return 0;
3309} 3309}
3310 3310
3311const struct amd_ip_funcs dce_v8_0_ip_funcs = { 3311static const struct amd_ip_funcs dce_v8_0_ip_funcs = {
3312 .name = "dce_v8_0", 3312 .name = "dce_v8_0",
3313 .early_init = dce_v8_0_early_init, 3313 .early_init = dce_v8_0_early_init,
3314 .late_init = NULL, 3314 .late_init = NULL,
@@ -3638,3 +3638,48 @@ static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
3638 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; 3638 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3639 adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs; 3639 adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
3640} 3640}
3641
3642const struct amdgpu_ip_block_version dce_v8_0_ip_block =
3643{
3644 .type = AMD_IP_BLOCK_TYPE_DCE,
3645 .major = 8,
3646 .minor = 0,
3647 .rev = 0,
3648 .funcs = &dce_v8_0_ip_funcs,
3649};
3650
3651const struct amdgpu_ip_block_version dce_v8_1_ip_block =
3652{
3653 .type = AMD_IP_BLOCK_TYPE_DCE,
3654 .major = 8,
3655 .minor = 1,
3656 .rev = 0,
3657 .funcs = &dce_v8_0_ip_funcs,
3658};
3659
3660const struct amdgpu_ip_block_version dce_v8_2_ip_block =
3661{
3662 .type = AMD_IP_BLOCK_TYPE_DCE,
3663 .major = 8,
3664 .minor = 2,
3665 .rev = 0,
3666 .funcs = &dce_v8_0_ip_funcs,
3667};
3668
3669const struct amdgpu_ip_block_version dce_v8_3_ip_block =
3670{
3671 .type = AMD_IP_BLOCK_TYPE_DCE,
3672 .major = 8,
3673 .minor = 3,
3674 .rev = 0,
3675 .funcs = &dce_v8_0_ip_funcs,
3676};
3677
3678const struct amdgpu_ip_block_version dce_v8_5_ip_block =
3679{
3680 .type = AMD_IP_BLOCK_TYPE_DCE,
3681 .major = 8,
3682 .minor = 5,
3683 .rev = 0,
3684 .funcs = &dce_v8_0_ip_funcs,
3685};
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h
index 7d0770c3a49b..13b802dd946a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h
@@ -24,7 +24,11 @@
24#ifndef __DCE_V8_0_H__ 24#ifndef __DCE_V8_0_H__
25#define __DCE_V8_0_H__ 25#define __DCE_V8_0_H__
26 26
27extern const struct amd_ip_funcs dce_v8_0_ip_funcs; 27extern const struct amdgpu_ip_block_version dce_v8_0_ip_block;
28extern const struct amdgpu_ip_block_version dce_v8_1_ip_block;
29extern const struct amdgpu_ip_block_version dce_v8_2_ip_block;
30extern const struct amdgpu_ip_block_version dce_v8_3_ip_block;
31extern const struct amdgpu_ip_block_version dce_v8_5_ip_block;
28 32
29void dce_v8_0_disable_dce(struct amdgpu_device *adev); 33void dce_v8_0_disable_dce(struct amdgpu_device *adev);
30 34
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index 7d041b9a4d61..cc85676a68d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -574,7 +574,7 @@ static int dce_virtual_set_powergating_state(void *handle,
574 return 0; 574 return 0;
575} 575}
576 576
577const struct amd_ip_funcs dce_virtual_ip_funcs = { 577static const struct amd_ip_funcs dce_virtual_ip_funcs = {
578 .name = "dce_virtual", 578 .name = "dce_virtual",
579 .early_init = dce_virtual_early_init, 579 .early_init = dce_virtual_early_init,
580 .late_init = NULL, 580 .late_init = NULL,
@@ -824,3 +824,11 @@ static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev)
824 adev->crtc_irq.funcs = &dce_virtual_crtc_irq_funcs; 824 adev->crtc_irq.funcs = &dce_virtual_crtc_irq_funcs;
825} 825}
826 826
827const struct amdgpu_ip_block_version dce_virtual_ip_block =
828{
829 .type = AMD_IP_BLOCK_TYPE_DCE,
830 .major = 1,
831 .minor = 0,
832 .rev = 0,
833 .funcs = &dce_virtual_ip_funcs,
834};
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.h b/drivers/gpu/drm/amd/amdgpu/dce_virtual.h
index 393ce97f783e..ed422012c8c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.h
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.h
@@ -24,7 +24,7 @@
24#ifndef __DCE_VIRTUAL_H__ 24#ifndef __DCE_VIRTUAL_H__
25#define __DCE_VIRTUAL_H__ 25#define __DCE_VIRTUAL_H__
26 26
27extern const struct amd_ip_funcs dce_virtual_ip_funcs; 27extern const struct amdgpu_ip_block_version dce_virtual_ip_block;
28 28
29#endif 29#endif
30 30
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 367b14e16e53..96dd05dca694 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -3206,7 +3206,7 @@ static int gfx_v6_0_set_powergating_state(void *handle,
3206 return 0; 3206 return 0;
3207} 3207}
3208 3208
3209const struct amd_ip_funcs gfx_v6_0_ip_funcs = { 3209static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3210 .name = "gfx_v6_0", 3210 .name = "gfx_v6_0",
3211 .early_init = gfx_v6_0_early_init, 3211 .early_init = gfx_v6_0_early_init,
3212 .late_init = NULL, 3212 .late_init = NULL,
@@ -3344,3 +3344,12 @@ static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3344 cu_info->number = active_cu_number; 3344 cu_info->number = active_cu_number;
3345 cu_info->ao_cu_mask = ao_cu_mask; 3345 cu_info->ao_cu_mask = ao_cu_mask;
3346} 3346}
3347
3348const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
3349{
3350 .type = AMD_IP_BLOCK_TYPE_GFX,
3351 .major = 6,
3352 .minor = 0,
3353 .rev = 0,
3354 .funcs = &gfx_v6_0_ip_funcs,
3355};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.h
index b9657e72b248..ced6fc42f688 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.h
@@ -24,6 +24,6 @@
24#ifndef __GFX_V6_0_H__ 24#ifndef __GFX_V6_0_H__
25#define __GFX_V6_0_H__ 25#define __GFX_V6_0_H__
26 26
27extern const struct amd_ip_funcs gfx_v6_0_ip_funcs; 27extern const struct amdgpu_ip_block_version gfx_v6_0_ip_block;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 388649734b36..bc6ccd05010f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -5087,7 +5087,7 @@ static int gfx_v7_0_set_powergating_state(void *handle,
5087 return 0; 5087 return 0;
5088} 5088}
5089 5089
5090const struct amd_ip_funcs gfx_v7_0_ip_funcs = { 5090static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
5091 .name = "gfx_v7_0", 5091 .name = "gfx_v7_0",
5092 .early_init = gfx_v7_0_early_init, 5092 .early_init = gfx_v7_0_early_init,
5093 .late_init = gfx_v7_0_late_init, 5093 .late_init = gfx_v7_0_late_init,
@@ -5270,3 +5270,39 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
5270 cu_info->number = active_cu_number; 5270 cu_info->number = active_cu_number;
5271 cu_info->ao_cu_mask = ao_cu_mask; 5271 cu_info->ao_cu_mask = ao_cu_mask;
5272} 5272}
5273
5274const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
5275{
5276 .type = AMD_IP_BLOCK_TYPE_GFX,
5277 .major = 7,
5278 .minor = 0,
5279 .rev = 0,
5280 .funcs = &gfx_v7_0_ip_funcs,
5281};
5282
5283const struct amdgpu_ip_block_version gfx_v7_1_ip_block =
5284{
5285 .type = AMD_IP_BLOCK_TYPE_GFX,
5286 .major = 7,
5287 .minor = 1,
5288 .rev = 0,
5289 .funcs = &gfx_v7_0_ip_funcs,
5290};
5291
5292const struct amdgpu_ip_block_version gfx_v7_2_ip_block =
5293{
5294 .type = AMD_IP_BLOCK_TYPE_GFX,
5295 .major = 7,
5296 .minor = 2,
5297 .rev = 0,
5298 .funcs = &gfx_v7_0_ip_funcs,
5299};
5300
5301const struct amdgpu_ip_block_version gfx_v7_3_ip_block =
5302{
5303 .type = AMD_IP_BLOCK_TYPE_GFX,
5304 .major = 7,
5305 .minor = 3,
5306 .rev = 0,
5307 .funcs = &gfx_v7_0_ip_funcs,
5308};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
index 94e3ea147c26..2f5164cc0e53 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
@@ -24,6 +24,9 @@
24#ifndef __GFX_V7_0_H__ 24#ifndef __GFX_V7_0_H__
25#define __GFX_V7_0_H__ 25#define __GFX_V7_0_H__
26 26
27extern const struct amd_ip_funcs gfx_v7_0_ip_funcs; 27extern const struct amdgpu_ip_block_version gfx_v7_0_ip_block;
28extern const struct amdgpu_ip_block_version gfx_v7_1_ip_block;
29extern const struct amdgpu_ip_block_version gfx_v7_2_ip_block;
30extern const struct amdgpu_ip_block_version gfx_v7_3_ip_block;
28 31
29#endif 32#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 6f3996f6d39a..27b3de44add7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6504,7 +6504,7 @@ static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
6504 return 0; 6504 return 0;
6505} 6505}
6506 6506
6507const struct amd_ip_funcs gfx_v8_0_ip_funcs = { 6507static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
6508 .name = "gfx_v8_0", 6508 .name = "gfx_v8_0",
6509 .early_init = gfx_v8_0_early_init, 6509 .early_init = gfx_v8_0_early_init,
6510 .late_init = gfx_v8_0_late_init, 6510 .late_init = gfx_v8_0_late_init,
@@ -6734,3 +6734,21 @@ static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
6734 cu_info->number = active_cu_number; 6734 cu_info->number = active_cu_number;
6735 cu_info->ao_cu_mask = ao_cu_mask; 6735 cu_info->ao_cu_mask = ao_cu_mask;
6736} 6736}
6737
6738const struct amdgpu_ip_block_version gfx_v8_0_ip_block =
6739{
6740 .type = AMD_IP_BLOCK_TYPE_GFX,
6741 .major = 8,
6742 .minor = 0,
6743 .rev = 0,
6744 .funcs = &gfx_v8_0_ip_funcs,
6745};
6746
6747const struct amdgpu_ip_block_version gfx_v8_1_ip_block =
6748{
6749 .type = AMD_IP_BLOCK_TYPE_GFX,
6750 .major = 8,
6751 .minor = 1,
6752 .rev = 0,
6753 .funcs = &gfx_v8_0_ip_funcs,
6754};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h
index ebed1f829297..788cc3ab584b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h
@@ -24,6 +24,7 @@
24#ifndef __GFX_V8_0_H__ 24#ifndef __GFX_V8_0_H__
25#define __GFX_V8_0_H__ 25#define __GFX_V8_0_H__
26 26
27extern const struct amd_ip_funcs gfx_v8_0_ip_funcs; 27extern const struct amdgpu_ip_block_version gfx_v8_0_ip_block;
28extern const struct amdgpu_ip_block_version gfx_v8_1_ip_block;
28 29
29#endif 30#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index b13c8aaec078..1940d36bc304 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -1030,7 +1030,7 @@ static int gmc_v6_0_set_powergating_state(void *handle,
1030 return 0; 1030 return 0;
1031} 1031}
1032 1032
1033const struct amd_ip_funcs gmc_v6_0_ip_funcs = { 1033static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
1034 .name = "gmc_v6_0", 1034 .name = "gmc_v6_0",
1035 .early_init = gmc_v6_0_early_init, 1035 .early_init = gmc_v6_0_early_init,
1036 .late_init = gmc_v6_0_late_init, 1036 .late_init = gmc_v6_0_late_init,
@@ -1069,3 +1069,11 @@ static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1069 adev->mc.vm_fault.funcs = &gmc_v6_0_irq_funcs; 1069 adev->mc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1070} 1070}
1071 1071
1072const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
1073{
1074 .type = AMD_IP_BLOCK_TYPE_GMC,
1075 .major = 6,
1076 .minor = 0,
1077 .rev = 0,
1078 .funcs = &gmc_v6_0_ip_funcs,
1079};
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.h
index 42c4fc676cd4..ed2f64dec47a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.h
@@ -24,6 +24,6 @@
24#ifndef __GMC_V6_0_H__ 24#ifndef __GMC_V6_0_H__
25#define __GMC_V6_0_H__ 25#define __GMC_V6_0_H__
26 26
27extern const struct amd_ip_funcs gmc_v6_0_ip_funcs; 27extern const struct amdgpu_ip_block_version gmc_v6_0_ip_block;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index aa0c4b964621..3a25f72980c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -1235,7 +1235,7 @@ static int gmc_v7_0_set_powergating_state(void *handle,
1235 return 0; 1235 return 0;
1236} 1236}
1237 1237
1238const struct amd_ip_funcs gmc_v7_0_ip_funcs = { 1238static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1239 .name = "gmc_v7_0", 1239 .name = "gmc_v7_0",
1240 .early_init = gmc_v7_0_early_init, 1240 .early_init = gmc_v7_0_early_init,
1241 .late_init = gmc_v7_0_late_init, 1241 .late_init = gmc_v7_0_late_init,
@@ -1273,3 +1273,21 @@ static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1273 adev->mc.vm_fault.num_types = 1; 1273 adev->mc.vm_fault.num_types = 1;
1274 adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs; 1274 adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1275} 1275}
1276
1277const struct amdgpu_ip_block_version gmc_v7_0_ip_block =
1278{
1279 .type = AMD_IP_BLOCK_TYPE_GMC,
1280 .major = 7,
1281 .minor = 0,
1282 .rev = 0,
1283 .funcs = &gmc_v7_0_ip_funcs,
1284};
1285
1286const struct amdgpu_ip_block_version gmc_v7_4_ip_block =
1287{
1288 .type = AMD_IP_BLOCK_TYPE_GMC,
1289 .major = 7,
1290 .minor = 4,
1291 .rev = 0,
1292 .funcs = &gmc_v7_0_ip_funcs,
1293};
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h
index 0b386b5d2f7a..ebce2966c1c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h
@@ -24,6 +24,7 @@
24#ifndef __GMC_V7_0_H__ 24#ifndef __GMC_V7_0_H__
25#define __GMC_V7_0_H__ 25#define __GMC_V7_0_H__
26 26
27extern const struct amd_ip_funcs gmc_v7_0_ip_funcs; 27extern const struct amdgpu_ip_block_version gmc_v7_0_ip_block;
28extern const struct amdgpu_ip_block_version gmc_v7_4_ip_block;
28 29
29#endif 30#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index c22ef140a542..74d7cc3f7e8c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1436,7 +1436,7 @@ static int gmc_v8_0_set_powergating_state(void *handle,
1436 return 0; 1436 return 0;
1437} 1437}
1438 1438
1439const struct amd_ip_funcs gmc_v8_0_ip_funcs = { 1439static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1440 .name = "gmc_v8_0", 1440 .name = "gmc_v8_0",
1441 .early_init = gmc_v8_0_early_init, 1441 .early_init = gmc_v8_0_early_init,
1442 .late_init = gmc_v8_0_late_init, 1442 .late_init = gmc_v8_0_late_init,
@@ -1477,3 +1477,30 @@ static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1477 adev->mc.vm_fault.num_types = 1; 1477 adev->mc.vm_fault.num_types = 1;
1478 adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs; 1478 adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1479} 1479}
1480
1481const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
1482{
1483 .type = AMD_IP_BLOCK_TYPE_GMC,
1484 .major = 8,
1485 .minor = 0,
1486 .rev = 0,
1487 .funcs = &gmc_v8_0_ip_funcs,
1488};
1489
1490const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
1491{
1492 .type = AMD_IP_BLOCK_TYPE_GMC,
1493 .major = 8,
1494 .minor = 1,
1495 .rev = 0,
1496 .funcs = &gmc_v8_0_ip_funcs,
1497};
1498
1499const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
1500{
1501 .type = AMD_IP_BLOCK_TYPE_GMC,
1502 .major = 8,
1503 .minor = 5,
1504 .rev = 0,
1505 .funcs = &gmc_v8_0_ip_funcs,
1506};
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h
index fc5001a8119d..19b8a8aed204 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h
@@ -24,6 +24,8 @@
24#ifndef __GMC_V8_0_H__ 24#ifndef __GMC_V8_0_H__
25#define __GMC_V8_0_H__ 25#define __GMC_V8_0_H__
26 26
27extern const struct amd_ip_funcs gmc_v8_0_ip_funcs; 27extern const struct amdgpu_ip_block_version gmc_v8_0_ip_block;
28extern const struct amdgpu_ip_block_version gmc_v8_1_ip_block;
29extern const struct amdgpu_ip_block_version gmc_v8_5_ip_block;
28 30
29#endif 31#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index 3b8906ce3511..ac21bb7bc0f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -392,7 +392,7 @@ static int iceland_ih_set_powergating_state(void *handle,
392 return 0; 392 return 0;
393} 393}
394 394
395const struct amd_ip_funcs iceland_ih_ip_funcs = { 395static const struct amd_ip_funcs iceland_ih_ip_funcs = {
396 .name = "iceland_ih", 396 .name = "iceland_ih",
397 .early_init = iceland_ih_early_init, 397 .early_init = iceland_ih_early_init,
398 .late_init = NULL, 398 .late_init = NULL,
@@ -421,3 +421,11 @@ static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev)
421 adev->irq.ih_funcs = &iceland_ih_funcs; 421 adev->irq.ih_funcs = &iceland_ih_funcs;
422} 422}
423 423
424const struct amdgpu_ip_block_version iceland_ih_ip_block =
425{
426 .type = AMD_IP_BLOCK_TYPE_IH,
427 .major = 2,
428 .minor = 4,
429 .rev = 0,
430 .funcs = &iceland_ih_ip_funcs,
431};
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.h b/drivers/gpu/drm/amd/amdgpu/iceland_ih.h
index 57558cddfbcb..3235f4277548 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.h
@@ -24,6 +24,6 @@
24#ifndef __ICELAND_IH_H__ 24#ifndef __ICELAND_IH_H__
25#define __ICELAND_IH_H__ 25#define __ICELAND_IH_H__
26 26
27extern const struct amd_ip_funcs iceland_ih_ip_funcs; 27extern const struct amdgpu_ip_block_version iceland_ih_ip_block;
28 28
29#endif /* __ICELAND_IH_H__ */ 29#endif /* __ICELAND_IH_H__ */
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index c3367d6f311a..42e5c9400f97 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -3292,3 +3292,12 @@ static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev)
3292 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; 3292 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
3293 adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs; 3293 adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs;
3294} 3294}
3295
3296const struct amdgpu_ip_block_version kv_dpm_ip_block =
3297{
3298 .type = AMD_IP_BLOCK_TYPE_SMC,
3299 .major = 7,
3300 .minor = 0,
3301 .rev = 0,
3302 .funcs = &kv_dpm_ip_funcs,
3303};
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 5859a106608b..03e8856b08ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -1187,7 +1187,7 @@ static int sdma_v2_4_set_powergating_state(void *handle,
1187 return 0; 1187 return 0;
1188} 1188}
1189 1189
1190const struct amd_ip_funcs sdma_v2_4_ip_funcs = { 1190static const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1191 .name = "sdma_v2_4", 1191 .name = "sdma_v2_4",
1192 .early_init = sdma_v2_4_early_init, 1192 .early_init = sdma_v2_4_early_init,
1193 .late_init = NULL, 1193 .late_init = NULL,
@@ -1340,3 +1340,12 @@ static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1340 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 1340 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1341 } 1341 }
1342} 1342}
1343
1344const struct amdgpu_ip_block_version sdma_v2_4_ip_block =
1345{
1346 .type = AMD_IP_BLOCK_TYPE_SDMA,
1347 .major = 2,
1348 .minor = 4,
1349 .rev = 0,
1350 .funcs = &sdma_v2_4_ip_funcs,
1351};
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h
index 07349f5ee10f..28b433729216 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h
@@ -24,6 +24,6 @@
24#ifndef __SDMA_V2_4_H__ 24#ifndef __SDMA_V2_4_H__
25#define __SDMA_V2_4_H__ 25#define __SDMA_V2_4_H__
26 26
27extern const struct amd_ip_funcs sdma_v2_4_ip_funcs; 27extern const struct amdgpu_ip_block_version sdma_v2_4_ip_block;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 24642f92b4b5..6172d01e985a 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1527,7 +1527,7 @@ static int sdma_v3_0_set_powergating_state(void *handle,
1527 return 0; 1527 return 0;
1528} 1528}
1529 1529
1530const struct amd_ip_funcs sdma_v3_0_ip_funcs = { 1530static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1531 .name = "sdma_v3_0", 1531 .name = "sdma_v3_0",
1532 .early_init = sdma_v3_0_early_init, 1532 .early_init = sdma_v3_0_early_init,
1533 .late_init = NULL, 1533 .late_init = NULL,
@@ -1683,3 +1683,21 @@ static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1683 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 1683 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1684 } 1684 }
1685} 1685}
1686
1687const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
1688{
1689 .type = AMD_IP_BLOCK_TYPE_SDMA,
1690 .major = 3,
1691 .minor = 0,
1692 .rev = 0,
1693 .funcs = &sdma_v3_0_ip_funcs,
1694};
1695
1696const struct amdgpu_ip_block_version sdma_v3_1_ip_block =
1697{
1698 .type = AMD_IP_BLOCK_TYPE_SDMA,
1699 .major = 3,
1700 .minor = 1,
1701 .rev = 0,
1702 .funcs = &sdma_v3_0_ip_funcs,
1703};
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h
index 0cb9698a3054..7aa223d35f1b 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h
@@ -24,6 +24,7 @@
24#ifndef __SDMA_V3_0_H__ 24#ifndef __SDMA_V3_0_H__
25#define __SDMA_V3_0_H__ 25#define __SDMA_V3_0_H__
26 26
27extern const struct amd_ip_funcs sdma_v3_0_ip_funcs; 27extern const struct amdgpu_ip_block_version sdma_v3_0_ip_block;
28extern const struct amdgpu_ip_block_version sdma_v3_1_ip_block;
28 29
29#endif 30#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 1d40c26de324..d2d79206bcf9 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1812,7 +1812,7 @@ static int si_common_set_powergating_state(void *handle,
1812 return 0; 1812 return 0;
1813} 1813}
1814 1814
1815const struct amd_ip_funcs si_common_ip_funcs = { 1815static const struct amd_ip_funcs si_common_ip_funcs = {
1816 .name = "si_common", 1816 .name = "si_common",
1817 .early_init = si_common_early_init, 1817 .early_init = si_common_early_init,
1818 .late_init = NULL, 1818 .late_init = NULL,
@@ -1829,240 +1829,13 @@ const struct amd_ip_funcs si_common_ip_funcs = {
1829 .set_powergating_state = si_common_set_powergating_state, 1829 .set_powergating_state = si_common_set_powergating_state,
1830}; 1830};
1831 1831
1832static const struct amdgpu_ip_block_version verde_ip_blocks[] = 1832static const struct amdgpu_ip_block_version si_common_ip_block =
1833{ 1833{
1834 { 1834 .type = AMD_IP_BLOCK_TYPE_COMMON,
1835 .type = AMD_IP_BLOCK_TYPE_COMMON, 1835 .major = 1,
1836 .major = 1, 1836 .minor = 0,
1837 .minor = 0, 1837 .rev = 0,
1838 .rev = 0, 1838 .funcs = &si_common_ip_funcs,
1839 .funcs = &si_common_ip_funcs,
1840 },
1841 {
1842 .type = AMD_IP_BLOCK_TYPE_GMC,
1843 .major = 6,
1844 .minor = 0,
1845 .rev = 0,
1846 .funcs = &gmc_v6_0_ip_funcs,
1847 },
1848 {
1849 .type = AMD_IP_BLOCK_TYPE_IH,
1850 .major = 1,
1851 .minor = 0,
1852 .rev = 0,
1853 .funcs = &si_ih_ip_funcs,
1854 },
1855 {
1856 .type = AMD_IP_BLOCK_TYPE_SMC,
1857 .major = 6,
1858 .minor = 0,
1859 .rev = 0,
1860 .funcs = &amdgpu_pp_ip_funcs,
1861 },
1862 {
1863 .type = AMD_IP_BLOCK_TYPE_DCE,
1864 .major = 6,
1865 .minor = 0,
1866 .rev = 0,
1867 .funcs = &dce_v6_0_ip_funcs,
1868 },
1869 {
1870 .type = AMD_IP_BLOCK_TYPE_GFX,
1871 .major = 6,
1872 .minor = 0,
1873 .rev = 0,
1874 .funcs = &gfx_v6_0_ip_funcs,
1875 },
1876 {
1877 .type = AMD_IP_BLOCK_TYPE_SDMA,
1878 .major = 1,
1879 .minor = 0,
1880 .rev = 0,
1881 .funcs = &si_dma_ip_funcs,
1882 },
1883/* {
1884 .type = AMD_IP_BLOCK_TYPE_UVD,
1885 .major = 3,
1886 .minor = 1,
1887 .rev = 0,
1888 .funcs = &si_null_ip_funcs,
1889 },
1890 {
1891 .type = AMD_IP_BLOCK_TYPE_VCE,
1892 .major = 1,
1893 .minor = 0,
1894 .rev = 0,
1895 .funcs = &si_null_ip_funcs,
1896 },
1897 */
1898};
1899
1900
1901static const struct amdgpu_ip_block_version verde_ip_blocks_vd[] =
1902{
1903 {
1904 .type = AMD_IP_BLOCK_TYPE_COMMON,
1905 .major = 1,
1906 .minor = 0,
1907 .rev = 0,
1908 .funcs = &si_common_ip_funcs,
1909 },
1910 {
1911 .type = AMD_IP_BLOCK_TYPE_GMC,
1912 .major = 6,
1913 .minor = 0,
1914 .rev = 0,
1915 .funcs = &gmc_v6_0_ip_funcs,
1916 },
1917 {
1918 .type = AMD_IP_BLOCK_TYPE_IH,
1919 .major = 1,
1920 .minor = 0,
1921 .rev = 0,
1922 .funcs = &si_ih_ip_funcs,
1923 },
1924 {
1925 .type = AMD_IP_BLOCK_TYPE_SMC,
1926 .major = 6,
1927 .minor = 0,
1928 .rev = 0,
1929 .funcs = &amdgpu_pp_ip_funcs,
1930 },
1931 {
1932 .type = AMD_IP_BLOCK_TYPE_DCE,
1933 .major = 6,
1934 .minor = 0,
1935 .rev = 0,
1936 .funcs = &dce_virtual_ip_funcs,
1937 },
1938 {
1939 .type = AMD_IP_BLOCK_TYPE_GFX,
1940 .major = 6,
1941 .minor = 0,
1942 .rev = 0,
1943 .funcs = &gfx_v6_0_ip_funcs,
1944 },
1945 {
1946 .type = AMD_IP_BLOCK_TYPE_SDMA,
1947 .major = 1,
1948 .minor = 0,
1949 .rev = 0,
1950 .funcs = &si_dma_ip_funcs,
1951 },
1952/* {
1953 .type = AMD_IP_BLOCK_TYPE_UVD,
1954 .major = 3,
1955 .minor = 1,
1956 .rev = 0,
1957 .funcs = &si_null_ip_funcs,
1958 },
1959 {
1960 .type = AMD_IP_BLOCK_TYPE_VCE,
1961 .major = 1,
1962 .minor = 0,
1963 .rev = 0,
1964 .funcs = &si_null_ip_funcs,
1965 },
1966 */
1967};
1968
1969static const struct amdgpu_ip_block_version hainan_ip_blocks[] =
1970{
1971 {
1972 .type = AMD_IP_BLOCK_TYPE_COMMON,
1973 .major = 1,
1974 .minor = 0,
1975 .rev = 0,
1976 .funcs = &si_common_ip_funcs,
1977 },
1978 {
1979 .type = AMD_IP_BLOCK_TYPE_GMC,
1980 .major = 6,
1981 .minor = 0,
1982 .rev = 0,
1983 .funcs = &gmc_v6_0_ip_funcs,
1984 },
1985 {
1986 .type = AMD_IP_BLOCK_TYPE_IH,
1987 .major = 1,
1988 .minor = 0,
1989 .rev = 0,
1990 .funcs = &si_ih_ip_funcs,
1991 },
1992 {
1993 .type = AMD_IP_BLOCK_TYPE_SMC,
1994 .major = 6,
1995 .minor = 0,
1996 .rev = 0,
1997 .funcs = &amdgpu_pp_ip_funcs,
1998 },
1999 {
2000 .type = AMD_IP_BLOCK_TYPE_GFX,
2001 .major = 6,
2002 .minor = 0,
2003 .rev = 0,
2004 .funcs = &gfx_v6_0_ip_funcs,
2005 },
2006 {
2007 .type = AMD_IP_BLOCK_TYPE_SDMA,
2008 .major = 1,
2009 .minor = 0,
2010 .rev = 0,
2011 .funcs = &si_dma_ip_funcs,
2012 },
2013};
2014
2015static const struct amdgpu_ip_block_version hainan_ip_blocks_vd[] =
2016{
2017 {
2018 .type = AMD_IP_BLOCK_TYPE_COMMON,
2019 .major = 1,
2020 .minor = 0,
2021 .rev = 0,
2022 .funcs = &si_common_ip_funcs,
2023 },
2024 {
2025 .type = AMD_IP_BLOCK_TYPE_GMC,
2026 .major = 6,
2027 .minor = 0,
2028 .rev = 0,
2029 .funcs = &gmc_v6_0_ip_funcs,
2030 },
2031 {
2032 .type = AMD_IP_BLOCK_TYPE_IH,
2033 .major = 1,
2034 .minor = 0,
2035 .rev = 0,
2036 .funcs = &si_ih_ip_funcs,
2037 },
2038 {
2039 .type = AMD_IP_BLOCK_TYPE_SMC,
2040 .major = 6,
2041 .minor = 0,
2042 .rev = 0,
2043 .funcs = &amdgpu_pp_ip_funcs,
2044 },
2045 {
2046 .type = AMD_IP_BLOCK_TYPE_DCE,
2047 .major = 1,
2048 .minor = 0,
2049 .rev = 0,
2050 .funcs = &dce_virtual_ip_funcs,
2051 },
2052 {
2053 .type = AMD_IP_BLOCK_TYPE_GFX,
2054 .major = 6,
2055 .minor = 0,
2056 .rev = 0,
2057 .funcs = &gfx_v6_0_ip_funcs,
2058 },
2059 {
2060 .type = AMD_IP_BLOCK_TYPE_SDMA,
2061 .major = 1,
2062 .minor = 0,
2063 .rev = 0,
2064 .funcs = &si_dma_ip_funcs,
2065 },
2066}; 1839};
2067 1840
2068int si_set_ip_blocks(struct amdgpu_device *adev) 1841int si_set_ip_blocks(struct amdgpu_device *adev)
@@ -2071,23 +1844,42 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
2071 case CHIP_VERDE: 1844 case CHIP_VERDE:
2072 case CHIP_TAHITI: 1845 case CHIP_TAHITI:
2073 case CHIP_PITCAIRN: 1846 case CHIP_PITCAIRN:
1847 amdgpu_ip_block_add(adev, &si_common_ip_block);
1848 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1849 amdgpu_ip_block_add(adev, &si_ih_ip_block);
1850 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1851 if (adev->enable_virtual_display)
1852 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1853 else
1854 amdgpu_ip_block_add(adev, &dce_v6_0_ip_block);
1855 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1856 amdgpu_ip_block_add(adev, &si_dma_ip_block);
1857 /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
1858 /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
1859 break;
2074 case CHIP_OLAND: 1860 case CHIP_OLAND:
2075 if (adev->enable_virtual_display) { 1861 amdgpu_ip_block_add(adev, &si_common_ip_block);
2076 adev->ip_blocks = verde_ip_blocks_vd; 1862 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
2077 adev->num_ip_blocks = ARRAY_SIZE(verde_ip_blocks_vd); 1863 amdgpu_ip_block_add(adev, &si_ih_ip_block);
2078 } else { 1864 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
2079 adev->ip_blocks = verde_ip_blocks; 1865 if (adev->enable_virtual_display)
2080 adev->num_ip_blocks = ARRAY_SIZE(verde_ip_blocks); 1866 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
2081 } 1867 else
1868 amdgpu_ip_block_add(adev, &dce_v6_4_ip_block);
1869 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1870 amdgpu_ip_block_add(adev, &si_dma_ip_block);
1871 /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
1872 /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
2082 break; 1873 break;
2083 case CHIP_HAINAN: 1874 case CHIP_HAINAN:
2084 if (adev->enable_virtual_display) { 1875 amdgpu_ip_block_add(adev, &si_common_ip_block);
2085 adev->ip_blocks = hainan_ip_blocks_vd; 1876 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
2086 adev->num_ip_blocks = ARRAY_SIZE(hainan_ip_blocks_vd); 1877 amdgpu_ip_block_add(adev, &si_ih_ip_block);
2087 } else { 1878 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
2088 adev->ip_blocks = hainan_ip_blocks; 1879 if (adev->enable_virtual_display)
2089 adev->num_ip_blocks = ARRAY_SIZE(hainan_ip_blocks); 1880 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
2090 } 1881 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1882 amdgpu_ip_block_add(adev, &si_dma_ip_block);
2091 break; 1883 break;
2092 default: 1884 default:
2093 BUG(); 1885 BUG();
diff --git a/drivers/gpu/drm/amd/amdgpu/si.h b/drivers/gpu/drm/amd/amdgpu/si.h
index 959d7b63e0e5..589225080c24 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.h
+++ b/drivers/gpu/drm/amd/amdgpu/si.h
@@ -24,8 +24,6 @@
24#ifndef __SI_H__ 24#ifndef __SI_H__
25#define __SI_H__ 25#define __SI_H__
26 26
27extern const struct amd_ip_funcs si_common_ip_funcs;
28
29void si_srbm_select(struct amdgpu_device *adev, 27void si_srbm_select(struct amdgpu_device *adev,
30 u32 me, u32 pipe, u32 queue, u32 vmid); 28 u32 me, u32 pipe, u32 queue, u32 vmid);
31int si_set_ip_blocks(struct amdgpu_device *adev); 29int si_set_ip_blocks(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 7fece1fe4130..14265c5c349e 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -745,7 +745,7 @@ static int si_dma_set_powergating_state(void *handle,
745 return 0; 745 return 0;
746} 746}
747 747
748const struct amd_ip_funcs si_dma_ip_funcs = { 748static const struct amd_ip_funcs si_dma_ip_funcs = {
749 .name = "si_dma", 749 .name = "si_dma",
750 .early_init = si_dma_early_init, 750 .early_init = si_dma_early_init,
751 .late_init = NULL, 751 .late_init = NULL,
@@ -903,3 +903,12 @@ static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev)
903 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 903 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
904 } 904 }
905} 905}
906
907const struct amdgpu_ip_block_version si_dma_ip_block =
908{
909 .type = AMD_IP_BLOCK_TYPE_SDMA,
910 .major = 1,
911 .minor = 0,
912 .rev = 0,
913 .funcs = &si_dma_ip_funcs,
914};
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.h b/drivers/gpu/drm/amd/amdgpu/si_dma.h
index 3a3e0c78a54b..5ac1b8452fb4 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.h
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.h
@@ -24,6 +24,6 @@
24#ifndef __SI_DMA_H__ 24#ifndef __SI_DMA_H__
25#define __SI_DMA_H__ 25#define __SI_DMA_H__
26 26
27extern const struct amd_ip_funcs si_dma_ip_funcs; 27extern const struct amdgpu_ip_block_version si_dma_ip_block;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 38b4b9789584..6e6c7cee3332 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -8011,3 +8011,11 @@ static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8011 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs; 8011 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
8012} 8012}
8013 8013
8014const struct amdgpu_ip_block_version si_dpm_ip_block =
8015{
8016 .type = AMD_IP_BLOCK_TYPE_SMC,
8017 .major = 6,
8018 .minor = 0,
8019 .rev = 0,
8020 .funcs = &si_dpm_ip_funcs,
8021};
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index 8fae3d4a2360..db0f36846661 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -268,7 +268,7 @@ static int si_ih_set_powergating_state(void *handle,
268 return 0; 268 return 0;
269} 269}
270 270
271const struct amd_ip_funcs si_ih_ip_funcs = { 271static const struct amd_ip_funcs si_ih_ip_funcs = {
272 .name = "si_ih", 272 .name = "si_ih",
273 .early_init = si_ih_early_init, 273 .early_init = si_ih_early_init,
274 .late_init = NULL, 274 .late_init = NULL,
@@ -297,3 +297,11 @@ static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev)
297 adev->irq.ih_funcs = &si_ih_funcs; 297 adev->irq.ih_funcs = &si_ih_funcs;
298} 298}
299 299
300const struct amdgpu_ip_block_version si_ih_ip_block =
301{
302 .type = AMD_IP_BLOCK_TYPE_IH,
303 .major = 1,
304 .minor = 0,
305 .rev = 0,
306 .funcs = &si_ih_ip_funcs,
307};
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.h b/drivers/gpu/drm/amd/amdgpu/si_ih.h
index f3e3a954369c..42e64a53e24f 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.h
@@ -24,6 +24,6 @@
24#ifndef __SI_IH_H__ 24#ifndef __SI_IH_H__
25#define __SI_IH_H__ 25#define __SI_IH_H__
26 26
27extern const struct amd_ip_funcs si_ih_ip_funcs; 27extern const struct amdgpu_ip_block_version si_ih_ip_block;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index b4ea229bb449..52b71ee58793 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -455,7 +455,7 @@ static int tonga_ih_set_powergating_state(void *handle,
455 return 0; 455 return 0;
456} 456}
457 457
458const struct amd_ip_funcs tonga_ih_ip_funcs = { 458static const struct amd_ip_funcs tonga_ih_ip_funcs = {
459 .name = "tonga_ih", 459 .name = "tonga_ih",
460 .early_init = tonga_ih_early_init, 460 .early_init = tonga_ih_early_init,
461 .late_init = NULL, 461 .late_init = NULL,
@@ -487,3 +487,11 @@ static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
487 adev->irq.ih_funcs = &tonga_ih_funcs; 487 adev->irq.ih_funcs = &tonga_ih_funcs;
488} 488}
489 489
490const struct amdgpu_ip_block_version tonga_ih_ip_block =
491{
492 .type = AMD_IP_BLOCK_TYPE_IH,
493 .major = 3,
494 .minor = 0,
495 .rev = 0,
496 .funcs = &tonga_ih_ip_funcs,
497};
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.h b/drivers/gpu/drm/amd/amdgpu/tonga_ih.h
index 7392d70fa4a7..499027eee5c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.h
@@ -24,6 +24,6 @@
24#ifndef __TONGA_IH_H__ 24#ifndef __TONGA_IH_H__
25#define __TONGA_IH_H__ 25#define __TONGA_IH_H__
26 26
27extern const struct amd_ip_funcs tonga_ih_ip_funcs; 27extern const struct amdgpu_ip_block_version tonga_ih_ip_block;
28 28
29#endif /* __CZ_IH_H__ */ 29#endif /* __TONGA_IH_H__ */
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 1bab75afba5d..3c2dce67b5f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -723,7 +723,7 @@ static int uvd_v4_2_set_powergating_state(void *handle,
723 } 723 }
724} 724}
725 725
726const struct amd_ip_funcs uvd_v4_2_ip_funcs = { 726static const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
727 .name = "uvd_v4_2", 727 .name = "uvd_v4_2",
728 .early_init = uvd_v4_2_early_init, 728 .early_init = uvd_v4_2_early_init,
729 .late_init = NULL, 729 .late_init = NULL,
@@ -780,3 +780,12 @@ static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev)
780 adev->uvd.irq.num_types = 1; 780 adev->uvd.irq.num_types = 1;
781 adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs; 781 adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs;
782} 782}
783
784const struct amdgpu_ip_block_version uvd_v4_2_ip_block =
785{
786 .type = AMD_IP_BLOCK_TYPE_UVD,
787 .major = 4,
788 .minor = 2,
789 .rev = 0,
790 .funcs = &uvd_v4_2_ip_funcs,
791};
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h
index 0a615dd50840..8a0444bb8b95 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h
@@ -24,6 +24,6 @@
24#ifndef __UVD_V4_2_H__ 24#ifndef __UVD_V4_2_H__
25#define __UVD_V4_2_H__ 25#define __UVD_V4_2_H__
26 26
27extern const struct amd_ip_funcs uvd_v4_2_ip_funcs; 27extern const struct amdgpu_ip_block_version uvd_v4_2_ip_block;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index ec848fc57f70..05088ec4c41b 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -774,7 +774,7 @@ static int uvd_v5_0_set_powergating_state(void *handle,
774 } 774 }
775} 775}
776 776
777const struct amd_ip_funcs uvd_v5_0_ip_funcs = { 777static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
778 .name = "uvd_v5_0", 778 .name = "uvd_v5_0",
779 .early_init = uvd_v5_0_early_init, 779 .early_init = uvd_v5_0_early_init,
780 .late_init = NULL, 780 .late_init = NULL,
@@ -831,3 +831,12 @@ static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev)
831 adev->uvd.irq.num_types = 1; 831 adev->uvd.irq.num_types = 1;
832 adev->uvd.irq.funcs = &uvd_v5_0_irq_funcs; 832 adev->uvd.irq.funcs = &uvd_v5_0_irq_funcs;
833} 833}
834
835const struct amdgpu_ip_block_version uvd_v5_0_ip_block =
836{
837 .type = AMD_IP_BLOCK_TYPE_UVD,
838 .major = 5,
839 .minor = 0,
840 .rev = 0,
841 .funcs = &uvd_v5_0_ip_funcs,
842};
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h
index e3b3c49fa5de..2eaaea793ac5 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h
@@ -24,6 +24,6 @@
24#ifndef __UVD_V5_0_H__ 24#ifndef __UVD_V5_0_H__
25#define __UVD_V5_0_H__ 25#define __UVD_V5_0_H__
26 26
27extern const struct amd_ip_funcs uvd_v5_0_ip_funcs; 27extern const struct amdgpu_ip_block_version uvd_v5_0_ip_block;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index be912933b073..2e2baa614b28 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -1001,7 +1001,7 @@ static int uvd_v6_0_set_powergating_state(void *handle,
1001 } 1001 }
1002} 1002}
1003 1003
1004const struct amd_ip_funcs uvd_v6_0_ip_funcs = { 1004static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
1005 .name = "uvd_v6_0", 1005 .name = "uvd_v6_0",
1006 .early_init = uvd_v6_0_early_init, 1006 .early_init = uvd_v6_0_early_init,
1007 .late_init = NULL, 1007 .late_init = NULL,
@@ -1096,3 +1096,30 @@ static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1096 adev->uvd.irq.num_types = 1; 1096 adev->uvd.irq.num_types = 1;
1097 adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs; 1097 adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
1098} 1098}
1099
1100const struct amdgpu_ip_block_version uvd_v6_0_ip_block =
1101{
1102 .type = AMD_IP_BLOCK_TYPE_UVD,
1103 .major = 6,
1104 .minor = 0,
1105 .rev = 0,
1106 .funcs = &uvd_v6_0_ip_funcs,
1107};
1108
1109const struct amdgpu_ip_block_version uvd_v6_2_ip_block =
1110{
1111 .type = AMD_IP_BLOCK_TYPE_UVD,
1112 .major = 6,
1113 .minor = 2,
1114 .rev = 0,
1115 .funcs = &uvd_v6_0_ip_funcs,
1116};
1117
1118const struct amdgpu_ip_block_version uvd_v6_3_ip_block =
1119{
1120 .type = AMD_IP_BLOCK_TYPE_UVD,
1121 .major = 6,
1122 .minor = 3,
1123 .rev = 0,
1124 .funcs = &uvd_v6_0_ip_funcs,
1125};
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h
index 6b92a2352986..d3d48c6428cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h
@@ -24,6 +24,8 @@
24#ifndef __UVD_V6_0_H__ 24#ifndef __UVD_V6_0_H__
25#define __UVD_V6_0_H__ 25#define __UVD_V6_0_H__
26 26
27extern const struct amd_ip_funcs uvd_v6_0_ip_funcs; 27extern const struct amdgpu_ip_block_version uvd_v6_0_ip_block;
28extern const struct amdgpu_ip_block_version uvd_v6_2_ip_block;
29extern const struct amdgpu_ip_block_version uvd_v6_3_ip_block;
28 30
29#endif 31#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index d58583983b11..38ed903dd6f8 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -592,7 +592,7 @@ static int vce_v2_0_set_powergating_state(void *handle,
592 return vce_v2_0_start(adev); 592 return vce_v2_0_start(adev);
593} 593}
594 594
595const struct amd_ip_funcs vce_v2_0_ip_funcs = { 595static const struct amd_ip_funcs vce_v2_0_ip_funcs = {
596 .name = "vce_v2_0", 596 .name = "vce_v2_0",
597 .early_init = vce_v2_0_early_init, 597 .early_init = vce_v2_0_early_init,
598 .late_init = NULL, 598 .late_init = NULL,
@@ -647,3 +647,12 @@ static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev)
647 adev->vce.irq.num_types = 1; 647 adev->vce.irq.num_types = 1;
648 adev->vce.irq.funcs = &vce_v2_0_irq_funcs; 648 adev->vce.irq.funcs = &vce_v2_0_irq_funcs;
649}; 649};
650
651const struct amdgpu_ip_block_version vce_v2_0_ip_block =
652{
653 .type = AMD_IP_BLOCK_TYPE_VCE,
654 .major = 2,
655 .minor = 0,
656 .rev = 0,
657 .funcs = &vce_v2_0_ip_funcs,
658};
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h
index 0d2ae8a01acd..4d15167654a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h
@@ -24,6 +24,6 @@
24#ifndef __VCE_V2_0_H__ 24#ifndef __VCE_V2_0_H__
25#define __VCE_V2_0_H__ 25#define __VCE_V2_0_H__
26 26
27extern const struct amd_ip_funcs vce_v2_0_ip_funcs; 27extern const struct amdgpu_ip_block_version vce_v2_0_ip_block;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 589fff19aa78..3f899e3326d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -807,7 +807,7 @@ static void vce_v3_0_emit_pipeline_sync(struct amdgpu_ring *ring)
807 amdgpu_ring_write(ring, seq); 807 amdgpu_ring_write(ring, seq);
808} 808}
809 809
810const struct amd_ip_funcs vce_v3_0_ip_funcs = { 810static const struct amd_ip_funcs vce_v3_0_ip_funcs = {
811 .name = "vce_v3_0", 811 .name = "vce_v3_0",
812 .early_init = vce_v3_0_early_init, 812 .early_init = vce_v3_0_early_init,
813 .late_init = NULL, 813 .late_init = NULL,
@@ -898,3 +898,30 @@ static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev)
898 adev->vce.irq.num_types = 1; 898 adev->vce.irq.num_types = 1;
899 adev->vce.irq.funcs = &vce_v3_0_irq_funcs; 899 adev->vce.irq.funcs = &vce_v3_0_irq_funcs;
900}; 900};
901
902const struct amdgpu_ip_block_version vce_v3_0_ip_block =
903{
904 .type = AMD_IP_BLOCK_TYPE_VCE,
905 .major = 3,
906 .minor = 0,
907 .rev = 0,
908 .funcs = &vce_v3_0_ip_funcs,
909};
910
911const struct amdgpu_ip_block_version vce_v3_1_ip_block =
912{
913 .type = AMD_IP_BLOCK_TYPE_VCE,
914 .major = 3,
915 .minor = 1,
916 .rev = 0,
917 .funcs = &vce_v3_0_ip_funcs,
918};
919
920const struct amdgpu_ip_block_version vce_v3_4_ip_block =
921{
922 .type = AMD_IP_BLOCK_TYPE_VCE,
923 .major = 3,
924 .minor = 4,
925 .rev = 0,
926 .funcs = &vce_v3_0_ip_funcs,
927};
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h
index b45af65da81f..08b908c7de0f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h
@@ -24,6 +24,8 @@
24#ifndef __VCE_V3_0_H__ 24#ifndef __VCE_V3_0_H__
25#define __VCE_V3_0_H__ 25#define __VCE_V3_0_H__
26 26
27extern const struct amd_ip_funcs vce_v3_0_ip_funcs; 27extern const struct amdgpu_ip_block_version vce_v3_0_ip_block;
28extern const struct amdgpu_ip_block_version vce_v3_1_ip_block;
29extern const struct amdgpu_ip_block_version vce_v3_4_ip_block;
28 30
29#endif 31#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 82f72cd1aebe..e33399cd1376 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -858,734 +858,6 @@ static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
858 WREG32(mmBIF_DOORBELL_APER_EN, tmp); 858 WREG32(mmBIF_DOORBELL_APER_EN, tmp);
859} 859}
860 860
861/* topaz has no DCE, UVD, VCE */
862static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
863{
864 /* ORDER MATTERS! */
865 {
866 .type = AMD_IP_BLOCK_TYPE_COMMON,
867 .major = 2,
868 .minor = 0,
869 .rev = 0,
870 .funcs = &vi_common_ip_funcs,
871 },
872 {
873 .type = AMD_IP_BLOCK_TYPE_GMC,
874 .major = 7,
875 .minor = 4,
876 .rev = 0,
877 .funcs = &gmc_v7_0_ip_funcs,
878 },
879 {
880 .type = AMD_IP_BLOCK_TYPE_IH,
881 .major = 2,
882 .minor = 4,
883 .rev = 0,
884 .funcs = &iceland_ih_ip_funcs,
885 },
886 {
887 .type = AMD_IP_BLOCK_TYPE_SMC,
888 .major = 7,
889 .minor = 1,
890 .rev = 0,
891 .funcs = &amdgpu_pp_ip_funcs,
892 },
893 {
894 .type = AMD_IP_BLOCK_TYPE_GFX,
895 .major = 8,
896 .minor = 0,
897 .rev = 0,
898 .funcs = &gfx_v8_0_ip_funcs,
899 },
900 {
901 .type = AMD_IP_BLOCK_TYPE_SDMA,
902 .major = 2,
903 .minor = 4,
904 .rev = 0,
905 .funcs = &sdma_v2_4_ip_funcs,
906 },
907};
908
909static const struct amdgpu_ip_block_version topaz_ip_blocks_vd[] =
910{
911 /* ORDER MATTERS! */
912 {
913 .type = AMD_IP_BLOCK_TYPE_COMMON,
914 .major = 2,
915 .minor = 0,
916 .rev = 0,
917 .funcs = &vi_common_ip_funcs,
918 },
919 {
920 .type = AMD_IP_BLOCK_TYPE_GMC,
921 .major = 7,
922 .minor = 4,
923 .rev = 0,
924 .funcs = &gmc_v7_0_ip_funcs,
925 },
926 {
927 .type = AMD_IP_BLOCK_TYPE_IH,
928 .major = 2,
929 .minor = 4,
930 .rev = 0,
931 .funcs = &iceland_ih_ip_funcs,
932 },
933 {
934 .type = AMD_IP_BLOCK_TYPE_SMC,
935 .major = 7,
936 .minor = 1,
937 .rev = 0,
938 .funcs = &amdgpu_pp_ip_funcs,
939 },
940 {
941 .type = AMD_IP_BLOCK_TYPE_DCE,
942 .major = 1,
943 .minor = 0,
944 .rev = 0,
945 .funcs = &dce_virtual_ip_funcs,
946 },
947 {
948 .type = AMD_IP_BLOCK_TYPE_GFX,
949 .major = 8,
950 .minor = 0,
951 .rev = 0,
952 .funcs = &gfx_v8_0_ip_funcs,
953 },
954 {
955 .type = AMD_IP_BLOCK_TYPE_SDMA,
956 .major = 2,
957 .minor = 4,
958 .rev = 0,
959 .funcs = &sdma_v2_4_ip_funcs,
960 },
961};
962
963static const struct amdgpu_ip_block_version tonga_ip_blocks[] =
964{
965 /* ORDER MATTERS! */
966 {
967 .type = AMD_IP_BLOCK_TYPE_COMMON,
968 .major = 2,
969 .minor = 0,
970 .rev = 0,
971 .funcs = &vi_common_ip_funcs,
972 },
973 {
974 .type = AMD_IP_BLOCK_TYPE_GMC,
975 .major = 8,
976 .minor = 0,
977 .rev = 0,
978 .funcs = &gmc_v8_0_ip_funcs,
979 },
980 {
981 .type = AMD_IP_BLOCK_TYPE_IH,
982 .major = 3,
983 .minor = 0,
984 .rev = 0,
985 .funcs = &tonga_ih_ip_funcs,
986 },
987 {
988 .type = AMD_IP_BLOCK_TYPE_SMC,
989 .major = 7,
990 .minor = 1,
991 .rev = 0,
992 .funcs = &amdgpu_pp_ip_funcs,
993 },
994 {
995 .type = AMD_IP_BLOCK_TYPE_DCE,
996 .major = 10,
997 .minor = 0,
998 .rev = 0,
999 .funcs = &dce_v10_0_ip_funcs,
1000 },
1001 {
1002 .type = AMD_IP_BLOCK_TYPE_GFX,
1003 .major = 8,
1004 .minor = 0,
1005 .rev = 0,
1006 .funcs = &gfx_v8_0_ip_funcs,
1007 },
1008 {
1009 .type = AMD_IP_BLOCK_TYPE_SDMA,
1010 .major = 3,
1011 .minor = 0,
1012 .rev = 0,
1013 .funcs = &sdma_v3_0_ip_funcs,
1014 },
1015 {
1016 .type = AMD_IP_BLOCK_TYPE_UVD,
1017 .major = 5,
1018 .minor = 0,
1019 .rev = 0,
1020 .funcs = &uvd_v5_0_ip_funcs,
1021 },
1022 {
1023 .type = AMD_IP_BLOCK_TYPE_VCE,
1024 .major = 3,
1025 .minor = 0,
1026 .rev = 0,
1027 .funcs = &vce_v3_0_ip_funcs,
1028 },
1029};
1030
1031static const struct amdgpu_ip_block_version tonga_ip_blocks_vd[] =
1032{
1033 /* ORDER MATTERS! */
1034 {
1035 .type = AMD_IP_BLOCK_TYPE_COMMON,
1036 .major = 2,
1037 .minor = 0,
1038 .rev = 0,
1039 .funcs = &vi_common_ip_funcs,
1040 },
1041 {
1042 .type = AMD_IP_BLOCK_TYPE_GMC,
1043 .major = 8,
1044 .minor = 0,
1045 .rev = 0,
1046 .funcs = &gmc_v8_0_ip_funcs,
1047 },
1048 {
1049 .type = AMD_IP_BLOCK_TYPE_IH,
1050 .major = 3,
1051 .minor = 0,
1052 .rev = 0,
1053 .funcs = &tonga_ih_ip_funcs,
1054 },
1055 {
1056 .type = AMD_IP_BLOCK_TYPE_SMC,
1057 .major = 7,
1058 .minor = 1,
1059 .rev = 0,
1060 .funcs = &amdgpu_pp_ip_funcs,
1061 },
1062 {
1063 .type = AMD_IP_BLOCK_TYPE_DCE,
1064 .major = 10,
1065 .minor = 0,
1066 .rev = 0,
1067 .funcs = &dce_virtual_ip_funcs,
1068 },
1069 {
1070 .type = AMD_IP_BLOCK_TYPE_GFX,
1071 .major = 8,
1072 .minor = 0,
1073 .rev = 0,
1074 .funcs = &gfx_v8_0_ip_funcs,
1075 },
1076 {
1077 .type = AMD_IP_BLOCK_TYPE_SDMA,
1078 .major = 3,
1079 .minor = 0,
1080 .rev = 0,
1081 .funcs = &sdma_v3_0_ip_funcs,
1082 },
1083 {
1084 .type = AMD_IP_BLOCK_TYPE_UVD,
1085 .major = 5,
1086 .minor = 0,
1087 .rev = 0,
1088 .funcs = &uvd_v5_0_ip_funcs,
1089 },
1090 {
1091 .type = AMD_IP_BLOCK_TYPE_VCE,
1092 .major = 3,
1093 .minor = 0,
1094 .rev = 0,
1095 .funcs = &vce_v3_0_ip_funcs,
1096 },
1097};
1098
1099static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
1100{
1101 /* ORDER MATTERS! */
1102 {
1103 .type = AMD_IP_BLOCK_TYPE_COMMON,
1104 .major = 2,
1105 .minor = 0,
1106 .rev = 0,
1107 .funcs = &vi_common_ip_funcs,
1108 },
1109 {
1110 .type = AMD_IP_BLOCK_TYPE_GMC,
1111 .major = 8,
1112 .minor = 5,
1113 .rev = 0,
1114 .funcs = &gmc_v8_0_ip_funcs,
1115 },
1116 {
1117 .type = AMD_IP_BLOCK_TYPE_IH,
1118 .major = 3,
1119 .minor = 0,
1120 .rev = 0,
1121 .funcs = &tonga_ih_ip_funcs,
1122 },
1123 {
1124 .type = AMD_IP_BLOCK_TYPE_SMC,
1125 .major = 7,
1126 .minor = 1,
1127 .rev = 0,
1128 .funcs = &amdgpu_pp_ip_funcs,
1129 },
1130 {
1131 .type = AMD_IP_BLOCK_TYPE_DCE,
1132 .major = 10,
1133 .minor = 1,
1134 .rev = 0,
1135 .funcs = &dce_v10_0_ip_funcs,
1136 },
1137 {
1138 .type = AMD_IP_BLOCK_TYPE_GFX,
1139 .major = 8,
1140 .minor = 0,
1141 .rev = 0,
1142 .funcs = &gfx_v8_0_ip_funcs,
1143 },
1144 {
1145 .type = AMD_IP_BLOCK_TYPE_SDMA,
1146 .major = 3,
1147 .minor = 0,
1148 .rev = 0,
1149 .funcs = &sdma_v3_0_ip_funcs,
1150 },
1151 {
1152 .type = AMD_IP_BLOCK_TYPE_UVD,
1153 .major = 6,
1154 .minor = 0,
1155 .rev = 0,
1156 .funcs = &uvd_v6_0_ip_funcs,
1157 },
1158 {
1159 .type = AMD_IP_BLOCK_TYPE_VCE,
1160 .major = 3,
1161 .minor = 0,
1162 .rev = 0,
1163 .funcs = &vce_v3_0_ip_funcs,
1164 },
1165};
1166
1167static const struct amdgpu_ip_block_version fiji_ip_blocks_vd[] =
1168{
1169 /* ORDER MATTERS! */
1170 {
1171 .type = AMD_IP_BLOCK_TYPE_COMMON,
1172 .major = 2,
1173 .minor = 0,
1174 .rev = 0,
1175 .funcs = &vi_common_ip_funcs,
1176 },
1177 {
1178 .type = AMD_IP_BLOCK_TYPE_GMC,
1179 .major = 8,
1180 .minor = 5,
1181 .rev = 0,
1182 .funcs = &gmc_v8_0_ip_funcs,
1183 },
1184 {
1185 .type = AMD_IP_BLOCK_TYPE_IH,
1186 .major = 3,
1187 .minor = 0,
1188 .rev = 0,
1189 .funcs = &tonga_ih_ip_funcs,
1190 },
1191 {
1192 .type = AMD_IP_BLOCK_TYPE_SMC,
1193 .major = 7,
1194 .minor = 1,
1195 .rev = 0,
1196 .funcs = &amdgpu_pp_ip_funcs,
1197 },
1198 {
1199 .type = AMD_IP_BLOCK_TYPE_DCE,
1200 .major = 10,
1201 .minor = 1,
1202 .rev = 0,
1203 .funcs = &dce_virtual_ip_funcs,
1204 },
1205 {
1206 .type = AMD_IP_BLOCK_TYPE_GFX,
1207 .major = 8,
1208 .minor = 0,
1209 .rev = 0,
1210 .funcs = &gfx_v8_0_ip_funcs,
1211 },
1212 {
1213 .type = AMD_IP_BLOCK_TYPE_SDMA,
1214 .major = 3,
1215 .minor = 0,
1216 .rev = 0,
1217 .funcs = &sdma_v3_0_ip_funcs,
1218 },
1219 {
1220 .type = AMD_IP_BLOCK_TYPE_UVD,
1221 .major = 6,
1222 .minor = 0,
1223 .rev = 0,
1224 .funcs = &uvd_v6_0_ip_funcs,
1225 },
1226 {
1227 .type = AMD_IP_BLOCK_TYPE_VCE,
1228 .major = 3,
1229 .minor = 0,
1230 .rev = 0,
1231 .funcs = &vce_v3_0_ip_funcs,
1232 },
1233};
1234
1235static const struct amdgpu_ip_block_version polaris11_ip_blocks[] =
1236{
1237 /* ORDER MATTERS! */
1238 {
1239 .type = AMD_IP_BLOCK_TYPE_COMMON,
1240 .major = 2,
1241 .minor = 0,
1242 .rev = 0,
1243 .funcs = &vi_common_ip_funcs,
1244 },
1245 {
1246 .type = AMD_IP_BLOCK_TYPE_GMC,
1247 .major = 8,
1248 .minor = 1,
1249 .rev = 0,
1250 .funcs = &gmc_v8_0_ip_funcs,
1251 },
1252 {
1253 .type = AMD_IP_BLOCK_TYPE_IH,
1254 .major = 3,
1255 .minor = 1,
1256 .rev = 0,
1257 .funcs = &tonga_ih_ip_funcs,
1258 },
1259 {
1260 .type = AMD_IP_BLOCK_TYPE_SMC,
1261 .major = 7,
1262 .minor = 2,
1263 .rev = 0,
1264 .funcs = &amdgpu_pp_ip_funcs,
1265 },
1266 {
1267 .type = AMD_IP_BLOCK_TYPE_DCE,
1268 .major = 11,
1269 .minor = 2,
1270 .rev = 0,
1271 .funcs = &dce_v11_0_ip_funcs,
1272 },
1273 {
1274 .type = AMD_IP_BLOCK_TYPE_GFX,
1275 .major = 8,
1276 .minor = 0,
1277 .rev = 0,
1278 .funcs = &gfx_v8_0_ip_funcs,
1279 },
1280 {
1281 .type = AMD_IP_BLOCK_TYPE_SDMA,
1282 .major = 3,
1283 .minor = 1,
1284 .rev = 0,
1285 .funcs = &sdma_v3_0_ip_funcs,
1286 },
1287 {
1288 .type = AMD_IP_BLOCK_TYPE_UVD,
1289 .major = 6,
1290 .minor = 3,
1291 .rev = 0,
1292 .funcs = &uvd_v6_0_ip_funcs,
1293 },
1294 {
1295 .type = AMD_IP_BLOCK_TYPE_VCE,
1296 .major = 3,
1297 .minor = 4,
1298 .rev = 0,
1299 .funcs = &vce_v3_0_ip_funcs,
1300 },
1301};
1302
1303static const struct amdgpu_ip_block_version polaris11_ip_blocks_vd[] =
1304{
1305 /* ORDER MATTERS! */
1306 {
1307 .type = AMD_IP_BLOCK_TYPE_COMMON,
1308 .major = 2,
1309 .minor = 0,
1310 .rev = 0,
1311 .funcs = &vi_common_ip_funcs,
1312 },
1313 {
1314 .type = AMD_IP_BLOCK_TYPE_GMC,
1315 .major = 8,
1316 .minor = 1,
1317 .rev = 0,
1318 .funcs = &gmc_v8_0_ip_funcs,
1319 },
1320 {
1321 .type = AMD_IP_BLOCK_TYPE_IH,
1322 .major = 3,
1323 .minor = 1,
1324 .rev = 0,
1325 .funcs = &tonga_ih_ip_funcs,
1326 },
1327 {
1328 .type = AMD_IP_BLOCK_TYPE_SMC,
1329 .major = 7,
1330 .minor = 2,
1331 .rev = 0,
1332 .funcs = &amdgpu_pp_ip_funcs,
1333 },
1334 {
1335 .type = AMD_IP_BLOCK_TYPE_DCE,
1336 .major = 11,
1337 .minor = 2,
1338 .rev = 0,
1339 .funcs = &dce_virtual_ip_funcs,
1340 },
1341 {
1342 .type = AMD_IP_BLOCK_TYPE_GFX,
1343 .major = 8,
1344 .minor = 0,
1345 .rev = 0,
1346 .funcs = &gfx_v8_0_ip_funcs,
1347 },
1348 {
1349 .type = AMD_IP_BLOCK_TYPE_SDMA,
1350 .major = 3,
1351 .minor = 1,
1352 .rev = 0,
1353 .funcs = &sdma_v3_0_ip_funcs,
1354 },
1355 {
1356 .type = AMD_IP_BLOCK_TYPE_UVD,
1357 .major = 6,
1358 .minor = 3,
1359 .rev = 0,
1360 .funcs = &uvd_v6_0_ip_funcs,
1361 },
1362 {
1363 .type = AMD_IP_BLOCK_TYPE_VCE,
1364 .major = 3,
1365 .minor = 4,
1366 .rev = 0,
1367 .funcs = &vce_v3_0_ip_funcs,
1368 },
1369};
1370
1371static const struct amdgpu_ip_block_version cz_ip_blocks[] =
1372{
1373 /* ORDER MATTERS! */
1374 {
1375 .type = AMD_IP_BLOCK_TYPE_COMMON,
1376 .major = 2,
1377 .minor = 0,
1378 .rev = 0,
1379 .funcs = &vi_common_ip_funcs,
1380 },
1381 {
1382 .type = AMD_IP_BLOCK_TYPE_GMC,
1383 .major = 8,
1384 .minor = 0,
1385 .rev = 0,
1386 .funcs = &gmc_v8_0_ip_funcs,
1387 },
1388 {
1389 .type = AMD_IP_BLOCK_TYPE_IH,
1390 .major = 3,
1391 .minor = 0,
1392 .rev = 0,
1393 .funcs = &cz_ih_ip_funcs,
1394 },
1395 {
1396 .type = AMD_IP_BLOCK_TYPE_SMC,
1397 .major = 8,
1398 .minor = 0,
1399 .rev = 0,
1400 .funcs = &amdgpu_pp_ip_funcs
1401 },
1402 {
1403 .type = AMD_IP_BLOCK_TYPE_DCE,
1404 .major = 11,
1405 .minor = 0,
1406 .rev = 0,
1407 .funcs = &dce_v11_0_ip_funcs,
1408 },
1409 {
1410 .type = AMD_IP_BLOCK_TYPE_GFX,
1411 .major = 8,
1412 .minor = 0,
1413 .rev = 0,
1414 .funcs = &gfx_v8_0_ip_funcs,
1415 },
1416 {
1417 .type = AMD_IP_BLOCK_TYPE_SDMA,
1418 .major = 3,
1419 .minor = 0,
1420 .rev = 0,
1421 .funcs = &sdma_v3_0_ip_funcs,
1422 },
1423 {
1424 .type = AMD_IP_BLOCK_TYPE_UVD,
1425 .major = 6,
1426 .minor = 0,
1427 .rev = 0,
1428 .funcs = &uvd_v6_0_ip_funcs,
1429 },
1430 {
1431 .type = AMD_IP_BLOCK_TYPE_VCE,
1432 .major = 3,
1433 .minor = 0,
1434 .rev = 0,
1435 .funcs = &vce_v3_0_ip_funcs,
1436 },
1437#if defined(CONFIG_DRM_AMD_ACP)
1438 {
1439 .type = AMD_IP_BLOCK_TYPE_ACP,
1440 .major = 2,
1441 .minor = 2,
1442 .rev = 0,
1443 .funcs = &acp_ip_funcs,
1444 },
1445#endif
1446};
1447
1448static const struct amdgpu_ip_block_version cz_ip_blocks_vd[] =
1449{
1450 /* ORDER MATTERS! */
1451 {
1452 .type = AMD_IP_BLOCK_TYPE_COMMON,
1453 .major = 2,
1454 .minor = 0,
1455 .rev = 0,
1456 .funcs = &vi_common_ip_funcs,
1457 },
1458 {
1459 .type = AMD_IP_BLOCK_TYPE_GMC,
1460 .major = 8,
1461 .minor = 0,
1462 .rev = 0,
1463 .funcs = &gmc_v8_0_ip_funcs,
1464 },
1465 {
1466 .type = AMD_IP_BLOCK_TYPE_IH,
1467 .major = 3,
1468 .minor = 0,
1469 .rev = 0,
1470 .funcs = &cz_ih_ip_funcs,
1471 },
1472 {
1473 .type = AMD_IP_BLOCK_TYPE_SMC,
1474 .major = 8,
1475 .minor = 0,
1476 .rev = 0,
1477 .funcs = &amdgpu_pp_ip_funcs
1478 },
1479 {
1480 .type = AMD_IP_BLOCK_TYPE_DCE,
1481 .major = 11,
1482 .minor = 0,
1483 .rev = 0,
1484 .funcs = &dce_virtual_ip_funcs,
1485 },
1486 {
1487 .type = AMD_IP_BLOCK_TYPE_GFX,
1488 .major = 8,
1489 .minor = 0,
1490 .rev = 0,
1491 .funcs = &gfx_v8_0_ip_funcs,
1492 },
1493 {
1494 .type = AMD_IP_BLOCK_TYPE_SDMA,
1495 .major = 3,
1496 .minor = 0,
1497 .rev = 0,
1498 .funcs = &sdma_v3_0_ip_funcs,
1499 },
1500 {
1501 .type = AMD_IP_BLOCK_TYPE_UVD,
1502 .major = 6,
1503 .minor = 0,
1504 .rev = 0,
1505 .funcs = &uvd_v6_0_ip_funcs,
1506 },
1507 {
1508 .type = AMD_IP_BLOCK_TYPE_VCE,
1509 .major = 3,
1510 .minor = 0,
1511 .rev = 0,
1512 .funcs = &vce_v3_0_ip_funcs,
1513 },
1514#if defined(CONFIG_DRM_AMD_ACP)
1515 {
1516 .type = AMD_IP_BLOCK_TYPE_ACP,
1517 .major = 2,
1518 .minor = 2,
1519 .rev = 0,
1520 .funcs = &acp_ip_funcs,
1521 },
1522#endif
1523};
1524
1525int vi_set_ip_blocks(struct amdgpu_device *adev)
1526{
1527 if (adev->enable_virtual_display) {
1528 switch (adev->asic_type) {
1529 case CHIP_TOPAZ:
1530 adev->ip_blocks = topaz_ip_blocks_vd;
1531 adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks_vd);
1532 break;
1533 case CHIP_FIJI:
1534 adev->ip_blocks = fiji_ip_blocks_vd;
1535 adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks_vd);
1536 break;
1537 case CHIP_TONGA:
1538 adev->ip_blocks = tonga_ip_blocks_vd;
1539 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks_vd);
1540 break;
1541 case CHIP_POLARIS11:
1542 case CHIP_POLARIS10:
1543 adev->ip_blocks = polaris11_ip_blocks_vd;
1544 adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks_vd);
1545 break;
1546
1547 case CHIP_CARRIZO:
1548 case CHIP_STONEY:
1549 adev->ip_blocks = cz_ip_blocks_vd;
1550 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks_vd);
1551 break;
1552 default:
1553 /* FIXME: not supported yet */
1554 return -EINVAL;
1555 }
1556 } else {
1557 switch (adev->asic_type) {
1558 case CHIP_TOPAZ:
1559 adev->ip_blocks = topaz_ip_blocks;
1560 adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
1561 break;
1562 case CHIP_FIJI:
1563 adev->ip_blocks = fiji_ip_blocks;
1564 adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
1565 break;
1566 case CHIP_TONGA:
1567 adev->ip_blocks = tonga_ip_blocks;
1568 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
1569 break;
1570 case CHIP_POLARIS11:
1571 case CHIP_POLARIS10:
1572 adev->ip_blocks = polaris11_ip_blocks;
1573 adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks);
1574 break;
1575 case CHIP_CARRIZO:
1576 case CHIP_STONEY:
1577 adev->ip_blocks = cz_ip_blocks;
1578 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
1579 break;
1580 default:
1581 /* FIXME: not supported yet */
1582 return -EINVAL;
1583 }
1584 }
1585
1586 return 0;
1587}
1588
1589#define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044 861#define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044
1590#define ATI_REV_ID_FUSE_MACRO__SHIFT 9 862#define ATI_REV_ID_FUSE_MACRO__SHIFT 9
1591#define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00 863#define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00
@@ -1985,7 +1257,7 @@ static int vi_common_set_powergating_state(void *handle,
1985 return 0; 1257 return 0;
1986} 1258}
1987 1259
1988const struct amd_ip_funcs vi_common_ip_funcs = { 1260static const struct amd_ip_funcs vi_common_ip_funcs = {
1989 .name = "vi_common", 1261 .name = "vi_common",
1990 .early_init = vi_common_early_init, 1262 .early_init = vi_common_early_init,
1991 .late_init = NULL, 1263 .late_init = NULL,
@@ -2002,3 +1274,110 @@ const struct amd_ip_funcs vi_common_ip_funcs = {
2002 .set_powergating_state = vi_common_set_powergating_state, 1274 .set_powergating_state = vi_common_set_powergating_state,
2003}; 1275};
2004 1276
1277static const struct amdgpu_ip_block_version vi_common_ip_block =
1278{
1279 .type = AMD_IP_BLOCK_TYPE_COMMON,
1280 .major = 1,
1281 .minor = 0,
1282 .rev = 0,
1283 .funcs = &vi_common_ip_funcs,
1284};
1285
1286int vi_set_ip_blocks(struct amdgpu_device *adev)
1287{
1288 switch (adev->asic_type) {
1289 case CHIP_TOPAZ:
1290 /* topaz has no DCE, UVD, VCE */
1291 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1292 amdgpu_ip_block_add(adev, &gmc_v7_4_ip_block);
1293 amdgpu_ip_block_add(adev, &iceland_ih_ip_block);
1294 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1295 if (adev->enable_virtual_display)
1296 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1297 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1298 amdgpu_ip_block_add(adev, &sdma_v2_4_ip_block);
1299 break;
1300 case CHIP_FIJI:
1301 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1302 amdgpu_ip_block_add(adev, &gmc_v8_5_ip_block);
1303 amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
1304 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1305 if (adev->enable_virtual_display)
1306 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1307 else
1308 amdgpu_ip_block_add(adev, &dce_v10_1_ip_block);
1309 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1310 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1311 amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block);
1312 amdgpu_ip_block_add(adev, &vce_v3_0_ip_block);
1313 break;
1314 case CHIP_TONGA:
1315 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1316 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
1317 amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
1318 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1319 if (adev->enable_virtual_display)
1320 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1321 else
1322 amdgpu_ip_block_add(adev, &dce_v10_0_ip_block);
1323 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1324 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1325 amdgpu_ip_block_add(adev, &uvd_v5_0_ip_block);
1326 amdgpu_ip_block_add(adev, &vce_v3_0_ip_block);
1327 break;
1328 case CHIP_POLARIS11:
1329 case CHIP_POLARIS10:
1330 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1331 amdgpu_ip_block_add(adev, &gmc_v8_1_ip_block);
1332 amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
1333 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1334 if (adev->enable_virtual_display)
1335 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1336 else
1337 amdgpu_ip_block_add(adev, &dce_v11_2_ip_block);
1338 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1339 amdgpu_ip_block_add(adev, &sdma_v3_1_ip_block);
1340 amdgpu_ip_block_add(adev, &uvd_v6_3_ip_block);
1341 amdgpu_ip_block_add(adev, &vce_v3_4_ip_block);
1342 break;
1343 case CHIP_CARRIZO:
1344 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1345 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
1346 amdgpu_ip_block_add(adev, &cz_ih_ip_block);
1347 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1348 if (adev->enable_virtual_display)
1349 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1350 else
1351 amdgpu_ip_block_add(adev, &dce_v11_0_ip_block);
1352 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1353 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1354 amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block);
1355 amdgpu_ip_block_add(adev, &vce_v3_1_ip_block);
1356#if defined(CONFIG_DRM_AMD_ACP)
1357 amdgpu_ip_block_add(adev, &acp_ip_block);
1358#endif
1359 break;
1360 case CHIP_STONEY:
1361 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1362 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
1363 amdgpu_ip_block_add(adev, &cz_ih_ip_block);
1364 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1365 if (adev->enable_virtual_display)
1366 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1367 else
1368 amdgpu_ip_block_add(adev, &dce_v11_0_ip_block);
1369 amdgpu_ip_block_add(adev, &gfx_v8_1_ip_block);
1370 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1371 amdgpu_ip_block_add(adev, &uvd_v6_2_ip_block);
1372 amdgpu_ip_block_add(adev, &vce_v3_4_ip_block);
1373#if defined(CONFIG_DRM_AMD_ACP)
1374 amdgpu_ip_block_add(adev, &acp_ip_block);
1375#endif
1376 break;
1377 default:
1378 /* FIXME: not supported yet */
1379 return -EINVAL;
1380 }
1381
1382 return 0;
1383}
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h
index 502094042462..575d7aed5d32 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.h
+++ b/drivers/gpu/drm/amd/amdgpu/vi.h
@@ -24,8 +24,6 @@
24#ifndef __VI_H__ 24#ifndef __VI_H__
25#define __VI_H__ 25#define __VI_H__
26 26
27extern const struct amd_ip_funcs vi_common_ip_funcs;
28
29void vi_srbm_select(struct amdgpu_device *adev, 27void vi_srbm_select(struct amdgpu_device *adev,
30 u32 me, u32 pipe, u32 queue, u32 vmid); 28 u32 me, u32 pipe, u32 queue, u32 vmid);
31int vi_set_ip_blocks(struct amdgpu_device *adev); 29int vi_set_ip_blocks(struct amdgpu_device *adev);
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-11 11:42:31 -0400