diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2016-07-06 12:40:16 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2016-07-07 15:06:19 -0400 |
commit | 33b7ed0122e4da0d92d50cc226cd9db659834eaa (patch) | |
tree | 83c0d13e85faa249a1f7ca0833f297c32ce474d4 /drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | |
parent | bb06d7ef99272ecf4f3d777b256cbae042888123 (diff) |
drm/amdgpu: remove more of the ring backup code
Not used anymore.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 28 |
1 files changed, 2 insertions, 26 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 1306a3b741a5..f6bd9465dbdc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | |||
@@ -2056,17 +2056,6 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, | |||
2056 | unsigned vm_id, bool ctx_switch) | 2056 | unsigned vm_id, bool ctx_switch) |
2057 | { | 2057 | { |
2058 | u32 header, control = 0; | 2058 | u32 header, control = 0; |
2059 | u32 next_rptr = ring->wptr + 5; | ||
2060 | |||
2061 | if (ctx_switch) | ||
2062 | next_rptr += 2; | ||
2063 | |||
2064 | next_rptr += 4; | ||
2065 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | ||
2066 | amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); | ||
2067 | amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); | ||
2068 | amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); | ||
2069 | amdgpu_ring_write(ring, next_rptr); | ||
2070 | 2059 | ||
2071 | /* insert SWITCH_BUFFER packet before first IB in the ring frame */ | 2060 | /* insert SWITCH_BUFFER packet before first IB in the ring frame */ |
2072 | if (ctx_switch) { | 2061 | if (ctx_switch) { |
@@ -2095,22 +2084,9 @@ static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring, | |||
2095 | struct amdgpu_ib *ib, | 2084 | struct amdgpu_ib *ib, |
2096 | unsigned vm_id, bool ctx_switch) | 2085 | unsigned vm_id, bool ctx_switch) |
2097 | { | 2086 | { |
2098 | u32 header, control = 0; | 2087 | u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24); |
2099 | u32 next_rptr = ring->wptr + 5; | ||
2100 | |||
2101 | control |= INDIRECT_BUFFER_VALID; | ||
2102 | next_rptr += 4; | ||
2103 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | ||
2104 | amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); | ||
2105 | amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); | ||
2106 | amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); | ||
2107 | amdgpu_ring_write(ring, next_rptr); | ||
2108 | |||
2109 | header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); | ||
2110 | 2088 | ||
2111 | control |= ib->length_dw | (vm_id << 24); | 2089 | amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
2112 | |||
2113 | amdgpu_ring_write(ring, header); | ||
2114 | amdgpu_ring_write(ring, | 2090 | amdgpu_ring_write(ring, |
2115 | #ifdef __BIG_ENDIAN | 2091 | #ifdef __BIG_ENDIAN |
2116 | (2 << 0) | | 2092 | (2 << 0) | |