diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2016-07-06 12:40:16 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2016-07-07 15:06:19 -0400 |
commit | 33b7ed0122e4da0d92d50cc226cd9db659834eaa (patch) | |
tree | 83c0d13e85faa249a1f7ca0833f297c32ce474d4 /drivers/gpu | |
parent | bb06d7ef99272ecf4f3d777b256cbae042888123 (diff) |
drm/amdgpu: remove more of the ring backup code
Not used anymore.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 9 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 11 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 28 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 29 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 13 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 12 |
7 files changed, 4 insertions, 101 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index ac686e514e01..814f12cc7f08 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h | |||
@@ -776,8 +776,6 @@ struct amdgpu_ring { | |||
776 | struct amdgpu_bo *ring_obj; | 776 | struct amdgpu_bo *ring_obj; |
777 | volatile uint32_t *ring; | 777 | volatile uint32_t *ring; |
778 | unsigned rptr_offs; | 778 | unsigned rptr_offs; |
779 | u64 next_rptr_gpu_addr; | ||
780 | volatile u32 *next_rptr_cpu_addr; | ||
781 | unsigned wptr; | 779 | unsigned wptr; |
782 | unsigned wptr_old; | 780 | unsigned wptr_old; |
783 | unsigned ring_size; | 781 | unsigned ring_size; |
@@ -796,7 +794,6 @@ struct amdgpu_ring { | |||
796 | u32 doorbell_index; | 794 | u32 doorbell_index; |
797 | bool use_doorbell; | 795 | bool use_doorbell; |
798 | unsigned wptr_offs; | 796 | unsigned wptr_offs; |
799 | unsigned next_rptr_offs; | ||
800 | unsigned fence_offs; | 797 | unsigned fence_offs; |
801 | uint64_t current_ctx; | 798 | uint64_t current_ctx; |
802 | enum amdgpu_ring_type type; | 799 | enum amdgpu_ring_type type; |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 71e146180e8e..3b885e3e9b56 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | |||
@@ -190,14 +190,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, | |||
190 | return r; | 190 | return r; |
191 | } | 191 | } |
192 | 192 | ||
193 | r = amdgpu_wb_get(adev, &ring->next_rptr_offs); | ||
194 | if (r) { | ||
195 | dev_err(adev->dev, "(%d) ring next_rptr wb alloc failed\n", r); | ||
196 | return r; | ||
197 | } | ||
198 | ring->next_rptr_gpu_addr = adev->wb.gpu_addr + ring->next_rptr_offs * 4; | ||
199 | ring->next_rptr_cpu_addr = &adev->wb.wb[ring->next_rptr_offs]; | ||
200 | |||
201 | r = amdgpu_wb_get(adev, &ring->cond_exe_offs); | 193 | r = amdgpu_wb_get(adev, &ring->cond_exe_offs); |
202 | if (r) { | 194 | if (r) { |
203 | dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r); | 195 | dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r); |
@@ -280,7 +272,6 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring) | |||
280 | amdgpu_wb_free(ring->adev, ring->fence_offs); | 272 | amdgpu_wb_free(ring->adev, ring->fence_offs); |
281 | amdgpu_wb_free(ring->adev, ring->rptr_offs); | 273 | amdgpu_wb_free(ring->adev, ring->rptr_offs); |
282 | amdgpu_wb_free(ring->adev, ring->wptr_offs); | 274 | amdgpu_wb_free(ring->adev, ring->wptr_offs); |
283 | amdgpu_wb_free(ring->adev, ring->next_rptr_offs); | ||
284 | 275 | ||
285 | if (ring_obj) { | 276 | if (ring_obj) { |
286 | r = amdgpu_bo_reserve(ring_obj, false); | 277 | r = amdgpu_bo_reserve(ring_obj, false); |
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 9dc4e24e31e7..46aca16a40aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c | |||
@@ -224,17 +224,6 @@ static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, | |||
224 | unsigned vm_id, bool ctx_switch) | 224 | unsigned vm_id, bool ctx_switch) |
225 | { | 225 | { |
226 | u32 extra_bits = vm_id & 0xf; | 226 | u32 extra_bits = vm_id & 0xf; |
227 | u32 next_rptr = ring->wptr + 5; | ||
228 | |||
229 | while ((next_rptr & 7) != 4) | ||
230 | next_rptr++; | ||
231 | |||
232 | next_rptr += 4; | ||
233 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); | ||
234 | amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); | ||
235 | amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); | ||
236 | amdgpu_ring_write(ring, 1); /* number of DWs to follow */ | ||
237 | amdgpu_ring_write(ring, next_rptr); | ||
238 | 227 | ||
239 | /* IB packet must end on a 8 DW boundary */ | 228 | /* IB packet must end on a 8 DW boundary */ |
240 | cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8); | 229 | cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8); |
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 1306a3b741a5..f6bd9465dbdc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | |||
@@ -2056,17 +2056,6 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, | |||
2056 | unsigned vm_id, bool ctx_switch) | 2056 | unsigned vm_id, bool ctx_switch) |
2057 | { | 2057 | { |
2058 | u32 header, control = 0; | 2058 | u32 header, control = 0; |
2059 | u32 next_rptr = ring->wptr + 5; | ||
2060 | |||
2061 | if (ctx_switch) | ||
2062 | next_rptr += 2; | ||
2063 | |||
2064 | next_rptr += 4; | ||
2065 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | ||
2066 | amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); | ||
2067 | amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); | ||
2068 | amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); | ||
2069 | amdgpu_ring_write(ring, next_rptr); | ||
2070 | 2059 | ||
2071 | /* insert SWITCH_BUFFER packet before first IB in the ring frame */ | 2060 | /* insert SWITCH_BUFFER packet before first IB in the ring frame */ |
2072 | if (ctx_switch) { | 2061 | if (ctx_switch) { |
@@ -2095,22 +2084,9 @@ static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring, | |||
2095 | struct amdgpu_ib *ib, | 2084 | struct amdgpu_ib *ib, |
2096 | unsigned vm_id, bool ctx_switch) | 2085 | unsigned vm_id, bool ctx_switch) |
2097 | { | 2086 | { |
2098 | u32 header, control = 0; | 2087 | u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24); |
2099 | u32 next_rptr = ring->wptr + 5; | ||
2100 | |||
2101 | control |= INDIRECT_BUFFER_VALID; | ||
2102 | next_rptr += 4; | ||
2103 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | ||
2104 | amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); | ||
2105 | amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); | ||
2106 | amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); | ||
2107 | amdgpu_ring_write(ring, next_rptr); | ||
2108 | |||
2109 | header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); | ||
2110 | 2088 | ||
2111 | control |= ib->length_dw | (vm_id << 24); | 2089 | amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
2112 | |||
2113 | amdgpu_ring_write(ring, header); | ||
2114 | amdgpu_ring_write(ring, | 2090 | amdgpu_ring_write(ring, |
2115 | #ifdef __BIG_ENDIAN | 2091 | #ifdef __BIG_ENDIAN |
2116 | (2 << 0) | | 2092 | (2 << 0) | |
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 892a41022d8f..c30b6ac25d89 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | |||
@@ -5929,17 +5929,6 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, | |||
5929 | unsigned vm_id, bool ctx_switch) | 5929 | unsigned vm_id, bool ctx_switch) |
5930 | { | 5930 | { |
5931 | u32 header, control = 0; | 5931 | u32 header, control = 0; |
5932 | u32 next_rptr = ring->wptr + 5; | ||
5933 | |||
5934 | if (ctx_switch) | ||
5935 | next_rptr += 2; | ||
5936 | |||
5937 | next_rptr += 4; | ||
5938 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | ||
5939 | amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); | ||
5940 | amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); | ||
5941 | amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); | ||
5942 | amdgpu_ring_write(ring, next_rptr); | ||
5943 | 5932 | ||
5944 | /* insert SWITCH_BUFFER packet before first IB in the ring frame */ | 5933 | /* insert SWITCH_BUFFER packet before first IB in the ring frame */ |
5945 | if (ctx_switch) { | 5934 | if (ctx_switch) { |
@@ -5968,23 +5957,9 @@ static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring, | |||
5968 | struct amdgpu_ib *ib, | 5957 | struct amdgpu_ib *ib, |
5969 | unsigned vm_id, bool ctx_switch) | 5958 | unsigned vm_id, bool ctx_switch) |
5970 | { | 5959 | { |
5971 | u32 header, control = 0; | 5960 | u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24); |
5972 | u32 next_rptr = ring->wptr + 5; | ||
5973 | |||
5974 | control |= INDIRECT_BUFFER_VALID; | ||
5975 | 5961 | ||
5976 | next_rptr += 4; | 5962 | amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
5977 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | ||
5978 | amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); | ||
5979 | amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); | ||
5980 | amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); | ||
5981 | amdgpu_ring_write(ring, next_rptr); | ||
5982 | |||
5983 | header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); | ||
5984 | |||
5985 | control |= ib->length_dw | (vm_id << 24); | ||
5986 | |||
5987 | amdgpu_ring_write(ring, header); | ||
5988 | amdgpu_ring_write(ring, | 5963 | amdgpu_ring_write(ring, |
5989 | #ifdef __BIG_ENDIAN | 5964 | #ifdef __BIG_ENDIAN |
5990 | (2 << 0) | | 5965 | (2 << 0) | |
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index b556bd0a8797..ac3730a6e49f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | |||
@@ -255,19 +255,6 @@ static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring, | |||
255 | unsigned vm_id, bool ctx_switch) | 255 | unsigned vm_id, bool ctx_switch) |
256 | { | 256 | { |
257 | u32 vmid = vm_id & 0xf; | 257 | u32 vmid = vm_id & 0xf; |
258 | u32 next_rptr = ring->wptr + 5; | ||
259 | |||
260 | while ((next_rptr & 7) != 2) | ||
261 | next_rptr++; | ||
262 | |||
263 | next_rptr += 6; | ||
264 | |||
265 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | | ||
266 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); | ||
267 | amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc); | ||
268 | amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); | ||
269 | amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); | ||
270 | amdgpu_ring_write(ring, next_rptr); | ||
271 | 258 | ||
272 | /* IB packet must end on a 8 DW boundary */ | 259 | /* IB packet must end on a 8 DW boundary */ |
273 | sdma_v2_4_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8); | 260 | sdma_v2_4_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8); |
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 532ea88da66a..f00db6f4c04c 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | |||
@@ -415,18 +415,6 @@ static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, | |||
415 | unsigned vm_id, bool ctx_switch) | 415 | unsigned vm_id, bool ctx_switch) |
416 | { | 416 | { |
417 | u32 vmid = vm_id & 0xf; | 417 | u32 vmid = vm_id & 0xf; |
418 | u32 next_rptr = ring->wptr + 5; | ||
419 | |||
420 | while ((next_rptr & 7) != 2) | ||
421 | next_rptr++; | ||
422 | next_rptr += 6; | ||
423 | |||
424 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | | ||
425 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); | ||
426 | amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc); | ||
427 | amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); | ||
428 | amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); | ||
429 | amdgpu_ring_write(ring, next_rptr); | ||
430 | 418 | ||
431 | /* IB packet must end on a 8 DW boundary */ | 419 | /* IB packet must end on a 8 DW boundary */ |
432 | sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8); | 420 | sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8); |