diff options
author | Dave Airlie <airlied@redhat.com> | 2017-04-10 17:31:18 -0400 |
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committer | Dave Airlie <airlied@redhat.com> | 2017-04-10 17:31:18 -0400 |
commit | 1420f63b8207e966f54caec26d08abdc2ff37193 (patch) | |
tree | eabaabbcaf7a39e36267a68f867f21504250fee5 /drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | |
parent | 2b2fc72aa51ba20f047d4825f8ea3e0d9306d8fb (diff) | |
parent | 32df87dff04833bbf53f1750f6c6048192ed29bf (diff) |
Merge branch 'drm-next-4.12' of git://people.freedesktop.org/~agd5f/linux into drm-next
Just some bug fixes and vega10 updates for 4.12.
* 'drm-next-4.12' of git://people.freedesktop.org/~agd5f/linux:
drm/amdgpu: fix fence memory leak in wait_all_fence V2
drm/amdgpu: fix "fix 64bit division"
drm/amd/powerplay: add fan controller table v11 support.
drm/amd/powerplay: port newest process pptable code for vega10.
drm/amdgpu: set vm size and block size by individual gmc by default (v3)
drm/amdgpu: Avoid overflows/divide-by-zero in latency_watermark calculations.
drm/amdgpu: Make display watermark calculations more accurate
drm/radeon: fix typo in bandwidth calculation
drm/radeon: Refuse to migrate a prime BO to VRAM. (v2)
drm/radeon: Maintain prime import/export refcount for BOs
drm/amdgpu: Refuse to pin or change acceptable domains of prime BOs to VRAM. (v2)
drm/amdgpu: Fail fb creation from imported dma-bufs. (v2)
drm/radeon: Fail fb creation from imported dma-bufs.
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/dce_v8_0.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 29 |
1 files changed, 8 insertions, 21 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 1b0717b11efe..e10c82f7a37a 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | |||
@@ -974,23 +974,10 @@ static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm) | |||
974 | a.full = dfixed_const(available_bandwidth); | 974 | a.full = dfixed_const(available_bandwidth); |
975 | b.full = dfixed_const(wm->num_heads); | 975 | b.full = dfixed_const(wm->num_heads); |
976 | a.full = dfixed_div(a, b); | 976 | a.full = dfixed_div(a, b); |
977 | tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); | ||
978 | tmp = min(dfixed_trunc(a), tmp); | ||
977 | 979 | ||
978 | b.full = dfixed_const(mc_latency + 512); | 980 | lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); |
979 | c.full = dfixed_const(wm->disp_clk); | ||
980 | b.full = dfixed_div(b, c); | ||
981 | |||
982 | c.full = dfixed_const(dmif_size); | ||
983 | b.full = dfixed_div(c, b); | ||
984 | |||
985 | tmp = min(dfixed_trunc(a), dfixed_trunc(b)); | ||
986 | |||
987 | b.full = dfixed_const(1000); | ||
988 | c.full = dfixed_const(wm->disp_clk); | ||
989 | b.full = dfixed_div(c, b); | ||
990 | c.full = dfixed_const(wm->bytes_per_pixel); | ||
991 | b.full = dfixed_mul(b, c); | ||
992 | |||
993 | lb_fill_bw = min(tmp, dfixed_trunc(b)); | ||
994 | 981 | ||
995 | a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); | 982 | a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); |
996 | b.full = dfixed_const(1000); | 983 | b.full = dfixed_const(1000); |
@@ -1098,14 +1085,14 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev, | |||
1098 | { | 1085 | { |
1099 | struct drm_display_mode *mode = &amdgpu_crtc->base.mode; | 1086 | struct drm_display_mode *mode = &amdgpu_crtc->base.mode; |
1100 | struct dce8_wm_params wm_low, wm_high; | 1087 | struct dce8_wm_params wm_low, wm_high; |
1101 | u32 pixel_period; | 1088 | u32 active_time; |
1102 | u32 line_time = 0; | 1089 | u32 line_time = 0; |
1103 | u32 latency_watermark_a = 0, latency_watermark_b = 0; | 1090 | u32 latency_watermark_a = 0, latency_watermark_b = 0; |
1104 | u32 tmp, wm_mask, lb_vblank_lead_lines = 0; | 1091 | u32 tmp, wm_mask, lb_vblank_lead_lines = 0; |
1105 | 1092 | ||
1106 | if (amdgpu_crtc->base.enabled && num_heads && mode) { | 1093 | if (amdgpu_crtc->base.enabled && num_heads && mode) { |
1107 | pixel_period = 1000000 / (u32)mode->clock; | 1094 | active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock; |
1108 | line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); | 1095 | line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535); |
1109 | 1096 | ||
1110 | /* watermark for high clocks */ | 1097 | /* watermark for high clocks */ |
1111 | if (adev->pm.dpm_enabled) { | 1098 | if (adev->pm.dpm_enabled) { |
@@ -1120,7 +1107,7 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev, | |||
1120 | 1107 | ||
1121 | wm_high.disp_clk = mode->clock; | 1108 | wm_high.disp_clk = mode->clock; |
1122 | wm_high.src_width = mode->crtc_hdisplay; | 1109 | wm_high.src_width = mode->crtc_hdisplay; |
1123 | wm_high.active_time = mode->crtc_hdisplay * pixel_period; | 1110 | wm_high.active_time = active_time; |
1124 | wm_high.blank_time = line_time - wm_high.active_time; | 1111 | wm_high.blank_time = line_time - wm_high.active_time; |
1125 | wm_high.interlaced = false; | 1112 | wm_high.interlaced = false; |
1126 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | 1113 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
@@ -1159,7 +1146,7 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev, | |||
1159 | 1146 | ||
1160 | wm_low.disp_clk = mode->clock; | 1147 | wm_low.disp_clk = mode->clock; |
1161 | wm_low.src_width = mode->crtc_hdisplay; | 1148 | wm_low.src_width = mode->crtc_hdisplay; |
1162 | wm_low.active_time = mode->crtc_hdisplay * pixel_period; | 1149 | wm_low.active_time = active_time; |
1163 | wm_low.blank_time = line_time - wm_low.active_time; | 1150 | wm_low.blank_time = line_time - wm_low.active_time; |
1164 | wm_low.interlaced = false; | 1151 | wm_low.interlaced = false; |
1165 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | 1152 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |