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-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c31
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_display.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_object.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c38
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v10_0.c29
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v11_0.c29
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v6_0.c29
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v8_0.c29
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c16
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h50
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c324
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.h28
-rw-r--r--drivers/gpu/drm/radeon/r100.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_cs.c10
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_gem.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon_prime.c6
27 files changed, 455 insertions, 220 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 9cd4e1e05b97..ec71b9320561 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1242,6 +1242,7 @@ static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1242 continue; 1242 continue;
1243 1243
1244 r = dma_fence_wait_timeout(fence, true, timeout); 1244 r = dma_fence_wait_timeout(fence, true, timeout);
1245 dma_fence_put(fence);
1245 if (r < 0) 1246 if (r < 0)
1246 return r; 1247 return r;
1247 1248
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 831c2bfd2072..483660742f75 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1040,35 +1040,31 @@ static bool amdgpu_check_pot_argument(int arg)
1040 return (arg & (arg - 1)) == 0; 1040 return (arg & (arg - 1)) == 0;
1041} 1041}
1042 1042
1043static void amdgpu_get_block_size(struct amdgpu_device *adev) 1043static void amdgpu_check_block_size(struct amdgpu_device *adev)
1044{ 1044{
1045 /* defines number of bits in page table versus page directory, 1045 /* defines number of bits in page table versus page directory,
1046 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the 1046 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1047 * page table and the remaining bits are in the page directory */ 1047 * page table and the remaining bits are in the page directory */
1048 if (amdgpu_vm_block_size == -1) { 1048 if (amdgpu_vm_block_size == -1)
1049 1049 return;
1050 /* Total bits covered by PD + PTs */
1051 unsigned bits = ilog2(amdgpu_vm_size) + 18;
1052
1053 /* Make sure the PD is 4K in size up to 8GB address space.
1054 Above that split equal between PD and PTs */
1055 if (amdgpu_vm_size <= 8)
1056 amdgpu_vm_block_size = bits - 9;
1057 else
1058 amdgpu_vm_block_size = (bits + 3) / 2;
1059 1050
1060 } else if (amdgpu_vm_block_size < 9) { 1051 if (amdgpu_vm_block_size < 9) {
1061 dev_warn(adev->dev, "VM page table size (%d) too small\n", 1052 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1062 amdgpu_vm_block_size); 1053 amdgpu_vm_block_size);
1063 amdgpu_vm_block_size = 9; 1054 goto def_value;
1064 } 1055 }
1065 1056
1066 if (amdgpu_vm_block_size > 24 || 1057 if (amdgpu_vm_block_size > 24 ||
1067 (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { 1058 (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1068 dev_warn(adev->dev, "VM page table size (%d) too large\n", 1059 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1069 amdgpu_vm_block_size); 1060 amdgpu_vm_block_size);
1070 amdgpu_vm_block_size = 9; 1061 goto def_value;
1071 } 1062 }
1063
1064 return;
1065
1066def_value:
1067 amdgpu_vm_block_size = -1;
1072} 1068}
1073 1069
1074static void amdgpu_check_vm_size(struct amdgpu_device *adev) 1070static void amdgpu_check_vm_size(struct amdgpu_device *adev)
@@ -1097,8 +1093,7 @@ static void amdgpu_check_vm_size(struct amdgpu_device *adev)
1097 return; 1093 return;
1098 1094
1099def_value: 1095def_value:
1100 amdgpu_vm_size = 8; 1096 amdgpu_vm_size = -1;
1101 dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size);
1102} 1097}
1103 1098
1104/** 1099/**
@@ -1132,7 +1127,7 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev)
1132 1127
1133 amdgpu_check_vm_size(adev); 1128 amdgpu_check_vm_size(adev);
1134 1129
1135 amdgpu_get_block_size(adev); 1130 amdgpu_check_block_size(adev);
1136 1131
1137 if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || 1132 if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
1138 !amdgpu_check_pot_argument(amdgpu_vram_page_split))) { 1133 !amdgpu_check_pot_argument(amdgpu_vram_page_split))) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index ce15721cadda..96926a221bd5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -614,6 +614,12 @@ amdgpu_user_framebuffer_create(struct drm_device *dev,
614 return ERR_PTR(-ENOENT); 614 return ERR_PTR(-ENOENT);
615 } 615 }
616 616
617 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
618 if (obj->import_attach) {
619 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
620 return ERR_PTR(-EINVAL);
621 }
622
617 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); 623 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
618 if (amdgpu_fb == NULL) { 624 if (amdgpu_fb == NULL) {
619 drm_gem_object_unreference_unlocked(obj); 625 drm_gem_object_unreference_unlocked(obj);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 400917fd7486..4e0f7d2d87f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -86,7 +86,7 @@ int amdgpu_runtime_pm = -1;
86unsigned amdgpu_ip_block_mask = 0xffffffff; 86unsigned amdgpu_ip_block_mask = 0xffffffff;
87int amdgpu_bapm = -1; 87int amdgpu_bapm = -1;
88int amdgpu_deep_color = 0; 88int amdgpu_deep_color = 0;
89int amdgpu_vm_size = 64; 89int amdgpu_vm_size = -1;
90int amdgpu_vm_block_size = -1; 90int amdgpu_vm_block_size = -1;
91int amdgpu_vm_fault_stop = 0; 91int amdgpu_vm_fault_stop = 0;
92int amdgpu_vm_debug = 0; 92int amdgpu_vm_debug = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index bb710e0ace01..03a9c5cad222 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -729,6 +729,11 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
729 break; 729 break;
730 } 730 }
731 case AMDGPU_GEM_OP_SET_PLACEMENT: 731 case AMDGPU_GEM_OP_SET_PLACEMENT:
732 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) {
733 r = -EINVAL;
734 amdgpu_bo_unreserve(robj);
735 break;
736 }
732 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 737 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
733 r = -EPERM; 738 r = -EPERM;
734 amdgpu_bo_unreserve(robj); 739 amdgpu_bo_unreserve(robj);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 758d8cf8fd17..cb89fff863c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -650,6 +650,10 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
650 if (WARN_ON_ONCE(min_offset > max_offset)) 650 if (WARN_ON_ONCE(min_offset > max_offset))
651 return -EINVAL; 651 return -EINVAL;
652 652
653 /* A shared bo cannot be migrated to VRAM */
654 if (bo->prime_shared_count && (domain == AMDGPU_GEM_DOMAIN_VRAM))
655 return -EINVAL;
656
653 if (bo->pin_count) { 657 if (bo->pin_count) {
654 uint32_t mem_type = bo->tbo.mem.mem_type; 658 uint32_t mem_type = bo->tbo.mem.mem_type;
655 659
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 7e993259c2e9..35d53a0d9ba6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -554,6 +554,7 @@ static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
554 uint64_t offset = page_offset; 554 uint64_t offset = page_offset;
555 555
556 page_offset = do_div(offset, size); 556 page_offset = do_div(offset, size);
557 mm += offset;
557 return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start + page_offset; 558 return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start + page_offset;
558} 559}
559 560
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 2895d9d86f29..7ed5302b511a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2064,6 +2064,44 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2064 } 2064 }
2065} 2065}
2066 2066
2067static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2068{
2069 /* Total bits covered by PD + PTs */
2070 unsigned bits = ilog2(vm_size) + 18;
2071
2072 /* Make sure the PD is 4K in size up to 8GB address space.
2073 Above that split equal between PD and PTs */
2074 if (vm_size <= 8)
2075 return (bits - 9);
2076 else
2077 return ((bits + 3) / 2);
2078}
2079
2080/**
2081 * amdgpu_vm_adjust_size - adjust vm size and block size
2082 *
2083 * @adev: amdgpu_device pointer
2084 * @vm_size: the default vm size if it's set auto
2085 */
2086void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size)
2087{
2088 /* adjust vm size firstly */
2089 if (amdgpu_vm_size == -1)
2090 adev->vm_manager.vm_size = vm_size;
2091 else
2092 adev->vm_manager.vm_size = amdgpu_vm_size;
2093
2094 /* block size depends on vm size */
2095 if (amdgpu_vm_block_size == -1)
2096 adev->vm_manager.block_size =
2097 amdgpu_vm_get_block_size(adev->vm_manager.vm_size);
2098 else
2099 adev->vm_manager.block_size = amdgpu_vm_block_size;
2100
2101 DRM_INFO("vm size is %llu GB, block size is %u-bit\n",
2102 adev->vm_manager.vm_size, adev->vm_manager.block_size);
2103}
2104
2067/** 2105/**
2068 * amdgpu_vm_init - initialize a vm instance 2106 * amdgpu_vm_init - initialize a vm instance
2069 * 2107 *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 02b0dd3b135f..d9e57290dc71 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -234,5 +234,6 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
234 uint64_t saddr, uint64_t size); 234 uint64_t saddr, uint64_t size);
235void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 235void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
236 struct amdgpu_bo_va *bo_va); 236 struct amdgpu_bo_va *bo_va);
237void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size);
237 238
238#endif 239#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index f525ae4e0576..2b78d58c9c35 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -1090,23 +1090,10 @@ static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
1090 a.full = dfixed_const(available_bandwidth); 1090 a.full = dfixed_const(available_bandwidth);
1091 b.full = dfixed_const(wm->num_heads); 1091 b.full = dfixed_const(wm->num_heads);
1092 a.full = dfixed_div(a, b); 1092 a.full = dfixed_div(a, b);
1093 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
1094 tmp = min(dfixed_trunc(a), tmp);
1093 1095
1094 b.full = dfixed_const(mc_latency + 512); 1096 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
1095 c.full = dfixed_const(wm->disp_clk);
1096 b.full = dfixed_div(b, c);
1097
1098 c.full = dfixed_const(dmif_size);
1099 b.full = dfixed_div(c, b);
1100
1101 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1102
1103 b.full = dfixed_const(1000);
1104 c.full = dfixed_const(wm->disp_clk);
1105 b.full = dfixed_div(c, b);
1106 c.full = dfixed_const(wm->bytes_per_pixel);
1107 b.full = dfixed_mul(b, c);
1108
1109 lb_fill_bw = min(tmp, dfixed_trunc(b));
1110 1097
1111 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 1098 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1112 b.full = dfixed_const(1000); 1099 b.full = dfixed_const(1000);
@@ -1214,14 +1201,14 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1214{ 1201{
1215 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1202 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1216 struct dce10_wm_params wm_low, wm_high; 1203 struct dce10_wm_params wm_low, wm_high;
1217 u32 pixel_period; 1204 u32 active_time;
1218 u32 line_time = 0; 1205 u32 line_time = 0;
1219 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1206 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1220 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1207 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1221 1208
1222 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1209 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1223 pixel_period = 1000000 / (u32)mode->clock; 1210 active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
1224 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 1211 line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
1225 1212
1226 /* watermark for high clocks */ 1213 /* watermark for high clocks */
1227 if (adev->pm.dpm_enabled) { 1214 if (adev->pm.dpm_enabled) {
@@ -1236,7 +1223,7 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1236 1223
1237 wm_high.disp_clk = mode->clock; 1224 wm_high.disp_clk = mode->clock;
1238 wm_high.src_width = mode->crtc_hdisplay; 1225 wm_high.src_width = mode->crtc_hdisplay;
1239 wm_high.active_time = mode->crtc_hdisplay * pixel_period; 1226 wm_high.active_time = active_time;
1240 wm_high.blank_time = line_time - wm_high.active_time; 1227 wm_high.blank_time = line_time - wm_high.active_time;
1241 wm_high.interlaced = false; 1228 wm_high.interlaced = false;
1242 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1229 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -1275,7 +1262,7 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1275 1262
1276 wm_low.disp_clk = mode->clock; 1263 wm_low.disp_clk = mode->clock;
1277 wm_low.src_width = mode->crtc_hdisplay; 1264 wm_low.src_width = mode->crtc_hdisplay;
1278 wm_low.active_time = mode->crtc_hdisplay * pixel_period; 1265 wm_low.active_time = active_time;
1279 wm_low.blank_time = line_time - wm_low.active_time; 1266 wm_low.blank_time = line_time - wm_low.active_time;
1280 wm_low.interlaced = false; 1267 wm_low.interlaced = false;
1281 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1268 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 3eac27f24d94..fec2a69f3ae2 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -1059,23 +1059,10 @@ static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
1059 a.full = dfixed_const(available_bandwidth); 1059 a.full = dfixed_const(available_bandwidth);
1060 b.full = dfixed_const(wm->num_heads); 1060 b.full = dfixed_const(wm->num_heads);
1061 a.full = dfixed_div(a, b); 1061 a.full = dfixed_div(a, b);
1062 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
1063 tmp = min(dfixed_trunc(a), tmp);
1062 1064
1063 b.full = dfixed_const(mc_latency + 512); 1065 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
1064 c.full = dfixed_const(wm->disp_clk);
1065 b.full = dfixed_div(b, c);
1066
1067 c.full = dfixed_const(dmif_size);
1068 b.full = dfixed_div(c, b);
1069
1070 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1071
1072 b.full = dfixed_const(1000);
1073 c.full = dfixed_const(wm->disp_clk);
1074 b.full = dfixed_div(c, b);
1075 c.full = dfixed_const(wm->bytes_per_pixel);
1076 b.full = dfixed_mul(b, c);
1077
1078 lb_fill_bw = min(tmp, dfixed_trunc(b));
1079 1066
1080 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 1067 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1081 b.full = dfixed_const(1000); 1068 b.full = dfixed_const(1000);
@@ -1183,14 +1170,14 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1183{ 1170{
1184 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1171 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1185 struct dce10_wm_params wm_low, wm_high; 1172 struct dce10_wm_params wm_low, wm_high;
1186 u32 pixel_period; 1173 u32 active_time;
1187 u32 line_time = 0; 1174 u32 line_time = 0;
1188 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1175 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1189 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1176 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1190 1177
1191 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1178 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1192 pixel_period = 1000000 / (u32)mode->clock; 1179 active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
1193 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 1180 line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
1194 1181
1195 /* watermark for high clocks */ 1182 /* watermark for high clocks */
1196 if (adev->pm.dpm_enabled) { 1183 if (adev->pm.dpm_enabled) {
@@ -1205,7 +1192,7 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1205 1192
1206 wm_high.disp_clk = mode->clock; 1193 wm_high.disp_clk = mode->clock;
1207 wm_high.src_width = mode->crtc_hdisplay; 1194 wm_high.src_width = mode->crtc_hdisplay;
1208 wm_high.active_time = mode->crtc_hdisplay * pixel_period; 1195 wm_high.active_time = active_time;
1209 wm_high.blank_time = line_time - wm_high.active_time; 1196 wm_high.blank_time = line_time - wm_high.active_time;
1210 wm_high.interlaced = false; 1197 wm_high.interlaced = false;
1211 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1198 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -1244,7 +1231,7 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1244 1231
1245 wm_low.disp_clk = mode->clock; 1232 wm_low.disp_clk = mode->clock;
1246 wm_low.src_width = mode->crtc_hdisplay; 1233 wm_low.src_width = mode->crtc_hdisplay;
1247 wm_low.active_time = mode->crtc_hdisplay * pixel_period; 1234 wm_low.active_time = active_time;
1248 wm_low.blank_time = line_time - wm_low.active_time; 1235 wm_low.blank_time = line_time - wm_low.active_time;
1249 wm_low.interlaced = false; 1236 wm_low.interlaced = false;
1250 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1237 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 838cf1a778f2..6604bcf783b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -861,23 +861,10 @@ static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm)
861 a.full = dfixed_const(available_bandwidth); 861 a.full = dfixed_const(available_bandwidth);
862 b.full = dfixed_const(wm->num_heads); 862 b.full = dfixed_const(wm->num_heads);
863 a.full = dfixed_div(a, b); 863 a.full = dfixed_div(a, b);
864 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
865 tmp = min(dfixed_trunc(a), tmp);
864 866
865 b.full = dfixed_const(mc_latency + 512); 867 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
866 c.full = dfixed_const(wm->disp_clk);
867 b.full = dfixed_div(b, c);
868
869 c.full = dfixed_const(dmif_size);
870 b.full = dfixed_div(c, b);
871
872 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
873
874 b.full = dfixed_const(1000);
875 c.full = dfixed_const(wm->disp_clk);
876 b.full = dfixed_div(c, b);
877 c.full = dfixed_const(wm->bytes_per_pixel);
878 b.full = dfixed_mul(b, c);
879
880 lb_fill_bw = min(tmp, dfixed_trunc(b));
881 868
882 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 869 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
883 b.full = dfixed_const(1000); 870 b.full = dfixed_const(1000);
@@ -986,7 +973,7 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
986 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 973 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
987 struct dce6_wm_params wm_low, wm_high; 974 struct dce6_wm_params wm_low, wm_high;
988 u32 dram_channels; 975 u32 dram_channels;
989 u32 pixel_period; 976 u32 active_time;
990 u32 line_time = 0; 977 u32 line_time = 0;
991 u32 latency_watermark_a = 0, latency_watermark_b = 0; 978 u32 latency_watermark_a = 0, latency_watermark_b = 0;
992 u32 priority_a_mark = 0, priority_b_mark = 0; 979 u32 priority_a_mark = 0, priority_b_mark = 0;
@@ -996,8 +983,8 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
996 fixed20_12 a, b, c; 983 fixed20_12 a, b, c;
997 984
998 if (amdgpu_crtc->base.enabled && num_heads && mode) { 985 if (amdgpu_crtc->base.enabled && num_heads && mode) {
999 pixel_period = 1000000 / (u32)mode->clock; 986 active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
1000 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 987 line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
1001 priority_a_cnt = 0; 988 priority_a_cnt = 0;
1002 priority_b_cnt = 0; 989 priority_b_cnt = 0;
1003 990
@@ -1016,7 +1003,7 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
1016 1003
1017 wm_high.disp_clk = mode->clock; 1004 wm_high.disp_clk = mode->clock;
1018 wm_high.src_width = mode->crtc_hdisplay; 1005 wm_high.src_width = mode->crtc_hdisplay;
1019 wm_high.active_time = mode->crtc_hdisplay * pixel_period; 1006 wm_high.active_time = active_time;
1020 wm_high.blank_time = line_time - wm_high.active_time; 1007 wm_high.blank_time = line_time - wm_high.active_time;
1021 wm_high.interlaced = false; 1008 wm_high.interlaced = false;
1022 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1009 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -1043,7 +1030,7 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
1043 1030
1044 wm_low.disp_clk = mode->clock; 1031 wm_low.disp_clk = mode->clock;
1045 wm_low.src_width = mode->crtc_hdisplay; 1032 wm_low.src_width = mode->crtc_hdisplay;
1046 wm_low.active_time = mode->crtc_hdisplay * pixel_period; 1033 wm_low.active_time = active_time;
1047 wm_low.blank_time = line_time - wm_low.active_time; 1034 wm_low.blank_time = line_time - wm_low.active_time;
1048 wm_low.interlaced = false; 1035 wm_low.interlaced = false;
1049 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1036 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 1b0717b11efe..e10c82f7a37a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -974,23 +974,10 @@ static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
974 a.full = dfixed_const(available_bandwidth); 974 a.full = dfixed_const(available_bandwidth);
975 b.full = dfixed_const(wm->num_heads); 975 b.full = dfixed_const(wm->num_heads);
976 a.full = dfixed_div(a, b); 976 a.full = dfixed_div(a, b);
977 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
978 tmp = min(dfixed_trunc(a), tmp);
977 979
978 b.full = dfixed_const(mc_latency + 512); 980 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
979 c.full = dfixed_const(wm->disp_clk);
980 b.full = dfixed_div(b, c);
981
982 c.full = dfixed_const(dmif_size);
983 b.full = dfixed_div(c, b);
984
985 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
986
987 b.full = dfixed_const(1000);
988 c.full = dfixed_const(wm->disp_clk);
989 b.full = dfixed_div(c, b);
990 c.full = dfixed_const(wm->bytes_per_pixel);
991 b.full = dfixed_mul(b, c);
992
993 lb_fill_bw = min(tmp, dfixed_trunc(b));
994 981
995 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 982 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
996 b.full = dfixed_const(1000); 983 b.full = dfixed_const(1000);
@@ -1098,14 +1085,14 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
1098{ 1085{
1099 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1086 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1100 struct dce8_wm_params wm_low, wm_high; 1087 struct dce8_wm_params wm_low, wm_high;
1101 u32 pixel_period; 1088 u32 active_time;
1102 u32 line_time = 0; 1089 u32 line_time = 0;
1103 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1090 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1104 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1091 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1105 1092
1106 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1093 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1107 pixel_period = 1000000 / (u32)mode->clock; 1094 active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
1108 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 1095 line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
1109 1096
1110 /* watermark for high clocks */ 1097 /* watermark for high clocks */
1111 if (adev->pm.dpm_enabled) { 1098 if (adev->pm.dpm_enabled) {
@@ -1120,7 +1107,7 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
1120 1107
1121 wm_high.disp_clk = mode->clock; 1108 wm_high.disp_clk = mode->clock;
1122 wm_high.src_width = mode->crtc_hdisplay; 1109 wm_high.src_width = mode->crtc_hdisplay;
1123 wm_high.active_time = mode->crtc_hdisplay * pixel_period; 1110 wm_high.active_time = active_time;
1124 wm_high.blank_time = line_time - wm_high.active_time; 1111 wm_high.blank_time = line_time - wm_high.active_time;
1125 wm_high.interlaced = false; 1112 wm_high.interlaced = false;
1126 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1113 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -1159,7 +1146,7 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
1159 1146
1160 wm_low.disp_clk = mode->clock; 1147 wm_low.disp_clk = mode->clock;
1161 wm_low.src_width = mode->crtc_hdisplay; 1148 wm_low.src_width = mode->crtc_hdisplay;
1162 wm_low.active_time = mode->crtc_hdisplay * pixel_period; 1149 wm_low.active_time = active_time;
1163 wm_low.blank_time = line_time - wm_low.active_time; 1150 wm_low.blank_time = line_time - wm_low.active_time;
1164 wm_low.interlaced = false; 1151 wm_low.interlaced = false;
1165 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1152 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 8f18d14f8eda..631aef38126d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -849,13 +849,9 @@ static int gmc_v6_0_sw_init(void *handle)
849 if (r) 849 if (r)
850 return r; 850 return r;
851 851
852 adev->vm_manager.vm_size = amdgpu_vm_size; 852 amdgpu_vm_adjust_size(adev, 64);
853 adev->vm_manager.block_size = amdgpu_vm_block_size;
854 adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; 853 adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
855 854
856 DRM_INFO("vm size is %llu GB, block size is %d-bit\n",
857 adev->vm_manager.vm_size, adev->vm_manager.block_size);
858
859 adev->mc.mc_mask = 0xffffffffffULL; 855 adev->mc.mc_mask = 0xffffffffffULL;
860 856
861 adev->need_dma32 = false; 857 adev->need_dma32 = false;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index b86b454197f8..92abe12d92bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -1003,13 +1003,9 @@ static int gmc_v7_0_sw_init(void *handle)
1003 * Currently set to 4GB ((1 << 20) 4k pages). 1003 * Currently set to 4GB ((1 << 20) 4k pages).
1004 * Max GPUVM size for cayman and SI is 40 bits. 1004 * Max GPUVM size for cayman and SI is 40 bits.
1005 */ 1005 */
1006 adev->vm_manager.vm_size = amdgpu_vm_size; 1006 amdgpu_vm_adjust_size(adev, 64);
1007 adev->vm_manager.block_size = amdgpu_vm_block_size;
1008 adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; 1007 adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
1009 1008
1010 DRM_INFO("vm size is %llu GB, block size is %d-bit\n",
1011 adev->vm_manager.vm_size, adev->vm_manager.block_size);
1012
1013 /* Set the internal MC address mask 1009 /* Set the internal MC address mask
1014 * This is the max address of the GPU's 1010 * This is the max address of the GPU's
1015 * internal address space. 1011 * internal address space.
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 108a20e832cf..f2ccefc66fd4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1087,13 +1087,9 @@ static int gmc_v8_0_sw_init(void *handle)
1087 * Currently set to 4GB ((1 << 20) 4k pages). 1087 * Currently set to 4GB ((1 << 20) 4k pages).
1088 * Max GPUVM size for cayman and SI is 40 bits. 1088 * Max GPUVM size for cayman and SI is 40 bits.
1089 */ 1089 */
1090 adev->vm_manager.vm_size = amdgpu_vm_size; 1090 amdgpu_vm_adjust_size(adev, 64);
1091 adev->vm_manager.block_size = amdgpu_vm_block_size;
1092 adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; 1091 adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
1093 1092
1094 DRM_INFO("vm size is %llu GB, block size is %d-bit\n",
1095 adev->vm_manager.vm_size, adev->vm_manager.block_size);
1096
1097 /* Set the internal MC address mask 1093 /* Set the internal MC address mask
1098 * This is the max address of the GPU's 1094 * This is the max address of the GPU's
1099 * internal address space. 1095 * internal address space.
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 6329be81f260..3b045e0b114e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -520,7 +520,12 @@ static int gmc_v9_0_vm_init(struct amdgpu_device *adev)
520 * amdkfd will use VMIDs 8-15 520 * amdkfd will use VMIDs 8-15
521 */ 521 */
522 adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS; 522 adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
523 adev->vm_manager.num_level = 3; 523
524 /* TODO: fix num_level for APU when updating vm size and block size */
525 if (adev->flags & AMD_IS_APU)
526 adev->vm_manager.num_level = 1;
527 else
528 adev->vm_manager.num_level = 3;
524 amdgpu_vm_manager_init(adev); 529 amdgpu_vm_manager_init(adev);
525 530
526 /* base offset of vram pages */ 531 /* base offset of vram pages */
@@ -552,8 +557,7 @@ static int gmc_v9_0_sw_init(void *handle)
552 557
553 if (adev->flags & AMD_IS_APU) { 558 if (adev->flags & AMD_IS_APU) {
554 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 559 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
555 adev->vm_manager.vm_size = amdgpu_vm_size; 560 amdgpu_vm_adjust_size(adev, 64);
556 adev->vm_manager.block_size = amdgpu_vm_block_size;
557 } else { 561 } else {
558 /* XXX Don't know how to get VRAM type yet. */ 562 /* XXX Don't know how to get VRAM type yet. */
559 adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM; 563 adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM;
@@ -564,11 +568,11 @@ static int gmc_v9_0_sw_init(void *handle)
564 */ 568 */
565 adev->vm_manager.vm_size = 1U << 18; 569 adev->vm_manager.vm_size = 1U << 18;
566 adev->vm_manager.block_size = 9; 570 adev->vm_manager.block_size = 9;
571 DRM_INFO("vm size is %llu GB, block size is %u-bit\n",
572 adev->vm_manager.vm_size,
573 adev->vm_manager.block_size);
567 } 574 }
568 575
569 DRM_INFO("vm size is %llu GB, block size is %d-bit\n",
570 adev->vm_manager.vm_size, adev->vm_manager.block_size);
571
572 /* This interrupt is VMC page fault.*/ 576 /* This interrupt is VMC page fault.*/
573 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0, 577 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
574 &adev->mc.vm_fault); 578 &adev->mc.vm_fault);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h
index 8e53d3a5e725..6a907c93fd9c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h
@@ -250,6 +250,29 @@ typedef struct _ATOM_Vega10_Fan_Table {
250 USHORT usFanStartTemperature; 250 USHORT usFanStartTemperature;
251} ATOM_Vega10_Fan_Table; 251} ATOM_Vega10_Fan_Table;
252 252
253typedef struct _ATOM_Vega10_Fan_Table_V2 {
254 UCHAR ucRevId;
255 USHORT usFanOutputSensitivity;
256 USHORT usFanAcousticLimitRpm;
257 USHORT usThrottlingRPM;
258 USHORT usTargetTemperature;
259 USHORT usMinimumPWMLimit;
260 USHORT usTargetGfxClk;
261 USHORT usFanGainEdge;
262 USHORT usFanGainHotspot;
263 USHORT usFanGainLiquid;
264 USHORT usFanGainVrVddc;
265 USHORT usFanGainVrMvdd;
266 USHORT usFanGainPlx;
267 USHORT usFanGainHbm;
268 UCHAR ucEnableZeroRPM;
269 USHORT usFanStopTemperature;
270 USHORT usFanStartTemperature;
271 UCHAR ucFanParameters;
272 UCHAR ucFanMinRPM;
273 UCHAR ucFanMaxRPM;
274} ATOM_Vega10_Fan_Table_V2;
275
253typedef struct _ATOM_Vega10_Thermal_Controller { 276typedef struct _ATOM_Vega10_Thermal_Controller {
254 UCHAR ucRevId; 277 UCHAR ucRevId;
255 UCHAR ucType; /* one of ATOM_VEGA10_PP_THERMALCONTROLLER_*/ 278 UCHAR ucType; /* one of ATOM_VEGA10_PP_THERMALCONTROLLER_*/
@@ -305,6 +328,33 @@ typedef struct _ATOM_Vega10_PowerTune_Table {
305 USHORT usTemperatureLimitTedge; 328 USHORT usTemperatureLimitTedge;
306} ATOM_Vega10_PowerTune_Table; 329} ATOM_Vega10_PowerTune_Table;
307 330
331typedef struct _ATOM_Vega10_PowerTune_Table_V2
332{
333 UCHAR ucRevId;
334 USHORT usSocketPowerLimit;
335 USHORT usBatteryPowerLimit;
336 USHORT usSmallPowerLimit;
337 USHORT usTdcLimit;
338 USHORT usEdcLimit;
339 USHORT usSoftwareShutdownTemp;
340 USHORT usTemperatureLimitHotSpot;
341 USHORT usTemperatureLimitLiquid1;
342 USHORT usTemperatureLimitLiquid2;
343 USHORT usTemperatureLimitHBM;
344 USHORT usTemperatureLimitVrSoc;
345 USHORT usTemperatureLimitVrMem;
346 USHORT usTemperatureLimitPlx;
347 USHORT usLoadLineResistance;
348 UCHAR ucLiquid1_I2C_address;
349 UCHAR ucLiquid2_I2C_address;
350 UCHAR ucLiquid_I2C_Line;
351 UCHAR ucVr_I2C_address;
352 UCHAR ucVr_I2C_Line;
353 UCHAR ucPlx_I2C_address;
354 UCHAR ucPlx_I2C_Line;
355 USHORT usTemperatureLimitTedge;
356} ATOM_Vega10_PowerTune_Table_V2;
357
308typedef struct _ATOM_Vega10_Hard_Limit_Record { 358typedef struct _ATOM_Vega10_Hard_Limit_Record {
309 ULONG ulSOCCLKLimit; 359 ULONG ulSOCCLKLimit;
310 ULONG ulGFXCLKLimit; 360 ULONG ulGFXCLKLimit;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
index 518634f995e7..8b55ae01132d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
@@ -116,14 +116,16 @@ static int init_thermal_controller(
116 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table) 116 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
117{ 117{
118 const ATOM_Vega10_Thermal_Controller *thermal_controller; 118 const ATOM_Vega10_Thermal_Controller *thermal_controller;
119 const ATOM_Vega10_Fan_Table *fan_table; 119 const Vega10_PPTable_Generic_SubTable_Header *header;
120 const ATOM_Vega10_Fan_Table *fan_table_v1;
121 const ATOM_Vega10_Fan_Table_V2 *fan_table_v2;
120 122
121 thermal_controller = (ATOM_Vega10_Thermal_Controller *) 123 thermal_controller = (ATOM_Vega10_Thermal_Controller *)
122 (((unsigned long)powerplay_table) + 124 (((unsigned long)powerplay_table) +
123 le16_to_cpu(powerplay_table->usThermalControllerOffset)); 125 le16_to_cpu(powerplay_table->usThermalControllerOffset));
124 126
125 PP_ASSERT_WITH_CODE((powerplay_table->usThermalControllerOffset != 0), 127 PP_ASSERT_WITH_CODE((powerplay_table->usThermalControllerOffset != 0),
126 "Thermal controller table not set!", return -1); 128 "Thermal controller table not set!", return -EINVAL);
127 129
128 hwmgr->thermal_controller.ucType = thermal_controller->ucType; 130 hwmgr->thermal_controller.ucType = thermal_controller->ucType;
129 hwmgr->thermal_controller.ucI2cLine = thermal_controller->ucI2cLine; 131 hwmgr->thermal_controller.ucI2cLine = thermal_controller->ucI2cLine;
@@ -142,6 +144,9 @@ static int init_thermal_controller(
142 hwmgr->thermal_controller.fanInfo.ulMaxRPM = 144 hwmgr->thermal_controller.fanInfo.ulMaxRPM =
143 thermal_controller->ucFanMaxRPM * 100UL; 145 thermal_controller->ucFanMaxRPM * 100UL;
144 146
147 hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay
148 = 100000;
149
145 set_hw_cap( 150 set_hw_cap(
146 hwmgr, 151 hwmgr,
147 ATOM_VEGA10_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType, 152 ATOM_VEGA10_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
@@ -150,54 +155,101 @@ static int init_thermal_controller(
150 if (!powerplay_table->usFanTableOffset) 155 if (!powerplay_table->usFanTableOffset)
151 return 0; 156 return 0;
152 157
153 fan_table = (const ATOM_Vega10_Fan_Table *) 158 header = (const Vega10_PPTable_Generic_SubTable_Header *)
154 (((unsigned long)powerplay_table) + 159 (((unsigned long)powerplay_table) +
155 le16_to_cpu(powerplay_table->usFanTableOffset)); 160 le16_to_cpu(powerplay_table->usFanTableOffset));
156 161
157 PP_ASSERT_WITH_CODE((fan_table->ucRevId >= 8), 162 if (header->ucRevId == 10) {
158 "Invalid Input Fan Table!", return -1); 163 fan_table_v1 = (ATOM_Vega10_Fan_Table *)header;
159 164
160 hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay 165 PP_ASSERT_WITH_CODE((fan_table_v1->ucRevId >= 8),
161 = 100000; 166 "Invalid Input Fan Table!", return -EINVAL);
162 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 167
163 PHM_PlatformCaps_MicrocodeFanControl); 168 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
164 169 PHM_PlatformCaps_MicrocodeFanControl);
165 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity = 170
166 le16_to_cpu(fan_table->usFanOutputSensitivity); 171 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
167 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = 172 le16_to_cpu(fan_table_v1->usFanOutputSensitivity);
168 le16_to_cpu(fan_table->usFanRPMMax); 173 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
169 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 174 le16_to_cpu(fan_table_v1->usFanRPMMax);
170 le16_to_cpu(fan_table->usThrottlingRPM); 175 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit =
171 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit = 176 le16_to_cpu(fan_table_v1->usThrottlingRPM);
172 le32_to_cpu((uint32_t)(fan_table->usFanAcousticLimit)); 177 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit =
173 hwmgr->thermal_controller.advanceFanControlParameters.usTMax = 178 le16_to_cpu(fan_table_v1->usFanAcousticLimit);
174 le16_to_cpu(fan_table->usTargetTemperature); 179 hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
175 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin = 180 le16_to_cpu(fan_table_v1->usTargetTemperature);
176 le16_to_cpu(fan_table->usMinimumPWMLimit); 181 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
177 hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk = 182 le16_to_cpu(fan_table_v1->usMinimumPWMLimit);
178 le32_to_cpu((uint32_t)(fan_table->usTargetGfxClk)); 183 hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk =
179 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge = 184 le16_to_cpu(fan_table_v1->usTargetGfxClk);
180 le16_to_cpu(fan_table->usFanGainEdge); 185 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge =
181 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot = 186 le16_to_cpu(fan_table_v1->usFanGainEdge);
182 le16_to_cpu(fan_table->usFanGainHotspot); 187 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot =
183 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid = 188 le16_to_cpu(fan_table_v1->usFanGainHotspot);
184 le16_to_cpu(fan_table->usFanGainLiquid); 189 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid =
185 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc = 190 le16_to_cpu(fan_table_v1->usFanGainLiquid);
186 le16_to_cpu(fan_table->usFanGainVrVddc); 191 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc =
187 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd = 192 le16_to_cpu(fan_table_v1->usFanGainVrVddc);
188 le16_to_cpu(fan_table->usFanGainVrMvdd); 193 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd =
189 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx = 194 le16_to_cpu(fan_table_v1->usFanGainVrMvdd);
190 le16_to_cpu(fan_table->usFanGainPlx); 195 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx =
191 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm = 196 le16_to_cpu(fan_table_v1->usFanGainPlx);
192 le16_to_cpu(fan_table->usFanGainHbm); 197 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm =
193 198 le16_to_cpu(fan_table_v1->usFanGainHbm);
194 hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM = 199
195 fan_table->ucEnableZeroRPM; 200 hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM =
196 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature = 201 fan_table_v1->ucEnableZeroRPM;
197 le16_to_cpu(fan_table->usFanStopTemperature); 202 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature =
198 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature = 203 le16_to_cpu(fan_table_v1->usFanStopTemperature);
199 le16_to_cpu(fan_table->usFanStartTemperature); 204 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature =
205 le16_to_cpu(fan_table_v1->usFanStartTemperature);
206 } else if (header->ucRevId > 10) {
207 fan_table_v2 = (ATOM_Vega10_Fan_Table_V2 *)header;
208
209 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
210 fan_table_v2->ucFanParameters & ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
211 hwmgr->thermal_controller.fanInfo.ulMinRPM = fan_table_v2->ucFanMinRPM * 100UL;
212 hwmgr->thermal_controller.fanInfo.ulMaxRPM = fan_table_v2->ucFanMaxRPM * 100UL;
200 213
214 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
215 PHM_PlatformCaps_MicrocodeFanControl);
216
217 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
218 le16_to_cpu(fan_table_v2->usFanOutputSensitivity);
219 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
220 fan_table_v2->ucFanMaxRPM * 100UL;
221 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit =
222 le16_to_cpu(fan_table_v2->usThrottlingRPM);
223 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit =
224 le16_to_cpu(fan_table_v2->usFanAcousticLimitRpm);
225 hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
226 le16_to_cpu(fan_table_v2->usTargetTemperature);
227 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
228 le16_to_cpu(fan_table_v2->usMinimumPWMLimit);
229 hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk =
230 le16_to_cpu(fan_table_v2->usTargetGfxClk);
231 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge =
232 le16_to_cpu(fan_table_v2->usFanGainEdge);
233 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot =
234 le16_to_cpu(fan_table_v2->usFanGainHotspot);
235 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid =
236 le16_to_cpu(fan_table_v2->usFanGainLiquid);
237 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc =
238 le16_to_cpu(fan_table_v2->usFanGainVrVddc);
239 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd =
240 le16_to_cpu(fan_table_v2->usFanGainVrMvdd);
241 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx =
242 le16_to_cpu(fan_table_v2->usFanGainPlx);
243 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm =
244 le16_to_cpu(fan_table_v2->usFanGainHbm);
245
246 hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM =
247 fan_table_v2->ucEnableZeroRPM;
248 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature =
249 le16_to_cpu(fan_table_v2->usFanStopTemperature);
250 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature =
251 le16_to_cpu(fan_table_v2->usFanStartTemperature);
252 }
201 return 0; 253 return 0;
202} 254}
203 255
@@ -261,6 +313,48 @@ static int get_mm_clock_voltage_table(
261 return 0; 313 return 0;
262} 314}
263 315
316static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t* sda)
317{
318 switch(line){
319 case Vega10_I2CLineID_DDC1:
320 *scl = Vega10_I2C_DDC1CLK;
321 *sda = Vega10_I2C_DDC1DATA;
322 break;
323 case Vega10_I2CLineID_DDC2:
324 *scl = Vega10_I2C_DDC2CLK;
325 *sda = Vega10_I2C_DDC2DATA;
326 break;
327 case Vega10_I2CLineID_DDC3:
328 *scl = Vega10_I2C_DDC3CLK;
329 *sda = Vega10_I2C_DDC3DATA;
330 break;
331 case Vega10_I2CLineID_DDC4:
332 *scl = Vega10_I2C_DDC4CLK;
333 *sda = Vega10_I2C_DDC4DATA;
334 break;
335 case Vega10_I2CLineID_DDC5:
336 *scl = Vega10_I2C_DDC5CLK;
337 *sda = Vega10_I2C_DDC5DATA;
338 break;
339 case Vega10_I2CLineID_DDC6:
340 *scl = Vega10_I2C_DDC6CLK;
341 *sda = Vega10_I2C_DDC6DATA;
342 break;
343 case Vega10_I2CLineID_SCLSDA:
344 *scl = Vega10_I2C_SCL;
345 *sda = Vega10_I2C_SDA;
346 break;
347 case Vega10_I2CLineID_DDCVGA:
348 *scl = Vega10_I2C_DDCVGACLK;
349 *sda = Vega10_I2C_DDCVGADATA;
350 break;
351 default:
352 *scl = 0;
353 *sda = 0;
354 break;
355 }
356}
357
264static int get_tdp_table( 358static int get_tdp_table(
265 struct pp_hwmgr *hwmgr, 359 struct pp_hwmgr *hwmgr,
266 struct phm_tdp_table **info_tdp_table, 360 struct phm_tdp_table **info_tdp_table,
@@ -268,59 +362,99 @@ static int get_tdp_table(
268{ 362{
269 uint32_t table_size; 363 uint32_t table_size;
270 struct phm_tdp_table *tdp_table; 364 struct phm_tdp_table *tdp_table;
271 365 uint8_t scl;
272 const ATOM_Vega10_PowerTune_Table *power_tune_table = 366 uint8_t sda;
273 (ATOM_Vega10_PowerTune_Table *)table; 367 const ATOM_Vega10_PowerTune_Table *power_tune_table;
274 368 const ATOM_Vega10_PowerTune_Table_V2 *power_tune_table_v2;
275 table_size = sizeof(uint32_t) + sizeof(struct phm_cac_tdp_table);
276 hwmgr->dyn_state.cac_dtp_table = (struct phm_cac_tdp_table *)
277 kzalloc(table_size, GFP_KERNEL);
278
279 if (!hwmgr->dyn_state.cac_dtp_table)
280 return -ENOMEM;
281 369
282 table_size = sizeof(uint32_t) + sizeof(struct phm_tdp_table); 370 table_size = sizeof(uint32_t) + sizeof(struct phm_tdp_table);
371
283 tdp_table = kzalloc(table_size, GFP_KERNEL); 372 tdp_table = kzalloc(table_size, GFP_KERNEL);
284 373
285 if (!tdp_table) { 374 if (!tdp_table)
286 kfree(hwmgr->dyn_state.cac_dtp_table);
287 hwmgr->dyn_state.cac_dtp_table = NULL;
288 return -ENOMEM; 375 return -ENOMEM;
289 }
290 376
291 tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table->usSocketPowerLimit); 377 if (table->ucRevId == 5) {
292 tdp_table->usTDC = le16_to_cpu(power_tune_table->usTdcLimit); 378 power_tune_table = (ATOM_Vega10_PowerTune_Table *)table;
293 tdp_table->usEDCLimit = le16_to_cpu(power_tune_table->usEdcLimit); 379 tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table->usSocketPowerLimit);
294 tdp_table->usSoftwareShutdownTemp = 380 tdp_table->usTDC = le16_to_cpu(power_tune_table->usTdcLimit);
295 le16_to_cpu(power_tune_table->usSoftwareShutdownTemp); 381 tdp_table->usEDCLimit = le16_to_cpu(power_tune_table->usEdcLimit);
296 tdp_table->usTemperatureLimitTedge = 382 tdp_table->usSoftwareShutdownTemp =
297 le16_to_cpu(power_tune_table->usTemperatureLimitTedge); 383 le16_to_cpu(power_tune_table->usSoftwareShutdownTemp);
298 tdp_table->usTemperatureLimitHotspot = 384 tdp_table->usTemperatureLimitTedge =
299 le16_to_cpu(power_tune_table->usTemperatureLimitHotSpot); 385 le16_to_cpu(power_tune_table->usTemperatureLimitTedge);
300 tdp_table->usTemperatureLimitLiquid1 = 386 tdp_table->usTemperatureLimitHotspot =
301 le16_to_cpu(power_tune_table->usTemperatureLimitLiquid1); 387 le16_to_cpu(power_tune_table->usTemperatureLimitHotSpot);
302 tdp_table->usTemperatureLimitLiquid2 = 388 tdp_table->usTemperatureLimitLiquid1 =
303 le16_to_cpu(power_tune_table->usTemperatureLimitLiquid2); 389 le16_to_cpu(power_tune_table->usTemperatureLimitLiquid1);
304 tdp_table->usTemperatureLimitHBM = 390 tdp_table->usTemperatureLimitLiquid2 =
305 le16_to_cpu(power_tune_table->usTemperatureLimitHBM); 391 le16_to_cpu(power_tune_table->usTemperatureLimitLiquid2);
306 tdp_table->usTemperatureLimitVrVddc = 392 tdp_table->usTemperatureLimitHBM =
307 le16_to_cpu(power_tune_table->usTemperatureLimitVrSoc); 393 le16_to_cpu(power_tune_table->usTemperatureLimitHBM);
308 tdp_table->usTemperatureLimitVrMvdd = 394 tdp_table->usTemperatureLimitVrVddc =
309 le16_to_cpu(power_tune_table->usTemperatureLimitVrMem); 395 le16_to_cpu(power_tune_table->usTemperatureLimitVrSoc);
310 tdp_table->usTemperatureLimitPlx = 396 tdp_table->usTemperatureLimitVrMvdd =
311 le16_to_cpu(power_tune_table->usTemperatureLimitPlx); 397 le16_to_cpu(power_tune_table->usTemperatureLimitVrMem);
312 tdp_table->ucLiquid1_I2C_address = power_tune_table->ucLiquid1_I2C_address; 398 tdp_table->usTemperatureLimitPlx =
313 tdp_table->ucLiquid2_I2C_address = power_tune_table->ucLiquid2_I2C_address; 399 le16_to_cpu(power_tune_table->usTemperatureLimitPlx);
314 tdp_table->ucLiquid_I2C_Line = power_tune_table->ucLiquid_I2C_LineSCL; 400 tdp_table->ucLiquid1_I2C_address = power_tune_table->ucLiquid1_I2C_address;
315 tdp_table->ucLiquid_I2C_LineSDA = power_tune_table->ucLiquid_I2C_LineSDA; 401 tdp_table->ucLiquid2_I2C_address = power_tune_table->ucLiquid2_I2C_address;
316 tdp_table->ucVr_I2C_address = power_tune_table->ucVr_I2C_address; 402 tdp_table->ucLiquid_I2C_Line = power_tune_table->ucLiquid_I2C_LineSCL;
317 tdp_table->ucVr_I2C_Line = power_tune_table->ucVr_I2C_LineSCL; 403 tdp_table->ucLiquid_I2C_LineSDA = power_tune_table->ucLiquid_I2C_LineSDA;
318 tdp_table->ucVr_I2C_LineSDA = power_tune_table->ucVr_I2C_LineSDA; 404 tdp_table->ucVr_I2C_address = power_tune_table->ucVr_I2C_address;
319 tdp_table->ucPlx_I2C_address = power_tune_table->ucPlx_I2C_address; 405 tdp_table->ucVr_I2C_Line = power_tune_table->ucVr_I2C_LineSCL;
320 tdp_table->ucPlx_I2C_Line = power_tune_table->ucPlx_I2C_LineSCL; 406 tdp_table->ucVr_I2C_LineSDA = power_tune_table->ucVr_I2C_LineSDA;
321 tdp_table->ucPlx_I2C_LineSDA = power_tune_table->ucPlx_I2C_LineSDA; 407 tdp_table->ucPlx_I2C_address = power_tune_table->ucPlx_I2C_address;
322 408 tdp_table->ucPlx_I2C_Line = power_tune_table->ucPlx_I2C_LineSCL;
323 hwmgr->platform_descriptor.LoadLineSlope = power_tune_table->usLoadLineResistance; 409 tdp_table->ucPlx_I2C_LineSDA = power_tune_table->ucPlx_I2C_LineSDA;
410 hwmgr->platform_descriptor.LoadLineSlope = power_tune_table->usLoadLineResistance;
411 } else {
412 power_tune_table_v2 = (ATOM_Vega10_PowerTune_Table_V2 *)table;
413 tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table_v2->usSocketPowerLimit);
414 tdp_table->usTDC = le16_to_cpu(power_tune_table_v2->usTdcLimit);
415 tdp_table->usEDCLimit = le16_to_cpu(power_tune_table_v2->usEdcLimit);
416 tdp_table->usSoftwareShutdownTemp =
417 le16_to_cpu(power_tune_table_v2->usSoftwareShutdownTemp);
418 tdp_table->usTemperatureLimitTedge =
419 le16_to_cpu(power_tune_table_v2->usTemperatureLimitTedge);
420 tdp_table->usTemperatureLimitHotspot =
421 le16_to_cpu(power_tune_table_v2->usTemperatureLimitHotSpot);
422 tdp_table->usTemperatureLimitLiquid1 =
423 le16_to_cpu(power_tune_table_v2->usTemperatureLimitLiquid1);
424 tdp_table->usTemperatureLimitLiquid2 =
425 le16_to_cpu(power_tune_table_v2->usTemperatureLimitLiquid2);
426 tdp_table->usTemperatureLimitHBM =
427 le16_to_cpu(power_tune_table_v2->usTemperatureLimitHBM);
428 tdp_table->usTemperatureLimitVrVddc =
429 le16_to_cpu(power_tune_table_v2->usTemperatureLimitVrSoc);
430 tdp_table->usTemperatureLimitVrMvdd =
431 le16_to_cpu(power_tune_table_v2->usTemperatureLimitVrMem);
432 tdp_table->usTemperatureLimitPlx =
433 le16_to_cpu(power_tune_table_v2->usTemperatureLimitPlx);
434 tdp_table->ucLiquid1_I2C_address = power_tune_table_v2->ucLiquid1_I2C_address;
435 tdp_table->ucLiquid2_I2C_address = power_tune_table_v2->ucLiquid2_I2C_address;
436
437 get_scl_sda_value(power_tune_table_v2->ucLiquid_I2C_Line, &scl, &sda);
438
439 tdp_table->ucLiquid_I2C_Line = scl;
440 tdp_table->ucLiquid_I2C_LineSDA = sda;
441
442 tdp_table->ucVr_I2C_address = power_tune_table_v2->ucVr_I2C_address;
443
444 get_scl_sda_value(power_tune_table_v2->ucVr_I2C_Line, &scl, &sda);
445
446 tdp_table->ucVr_I2C_Line = scl;
447 tdp_table->ucVr_I2C_LineSDA = sda;
448 tdp_table->ucPlx_I2C_address = power_tune_table_v2->ucPlx_I2C_address;
449
450 get_scl_sda_value(power_tune_table_v2->ucPlx_I2C_Line, &scl, &sda);
451
452 tdp_table->ucPlx_I2C_Line = scl;
453 tdp_table->ucPlx_I2C_LineSDA = sda;
454
455 hwmgr->platform_descriptor.LoadLineSlope =
456 power_tune_table_v2->usLoadLineResistance;
457 }
324 458
325 *info_tdp_table = tdp_table; 459 *info_tdp_table = tdp_table;
326 460
@@ -836,7 +970,7 @@ static int init_dpm_2_parameters(
836 (((unsigned long)powerplay_table) + 970 (((unsigned long)powerplay_table) +
837 le16_to_cpu(powerplay_table->usVddcLookupTableOffset)); 971 le16_to_cpu(powerplay_table->usVddcLookupTableOffset));
838 result = get_vddc_lookup_table(hwmgr, 972 result = get_vddc_lookup_table(hwmgr,
839 &pp_table_info->vddc_lookup_table, vddc_table, 16); 973 &pp_table_info->vddc_lookup_table, vddc_table, 8);
840 } 974 }
841 975
842 if (powerplay_table->usVddmemLookupTableOffset) { 976 if (powerplay_table->usVddmemLookupTableOffset) {
@@ -845,7 +979,7 @@ static int init_dpm_2_parameters(
845 (((unsigned long)powerplay_table) + 979 (((unsigned long)powerplay_table) +
846 le16_to_cpu(powerplay_table->usVddmemLookupTableOffset)); 980 le16_to_cpu(powerplay_table->usVddmemLookupTableOffset));
847 result = get_vddc_lookup_table(hwmgr, 981 result = get_vddc_lookup_table(hwmgr,
848 &pp_table_info->vddmem_lookup_table, vdd_mem_table, 16); 982 &pp_table_info->vddmem_lookup_table, vdd_mem_table, 4);
849 } 983 }
850 984
851 if (powerplay_table->usVddciLookupTableOffset) { 985 if (powerplay_table->usVddciLookupTableOffset) {
@@ -854,7 +988,7 @@ static int init_dpm_2_parameters(
854 (((unsigned long)powerplay_table) + 988 (((unsigned long)powerplay_table) +
855 le16_to_cpu(powerplay_table->usVddciLookupTableOffset)); 989 le16_to_cpu(powerplay_table->usVddciLookupTableOffset));
856 result = get_vddc_lookup_table(hwmgr, 990 result = get_vddc_lookup_table(hwmgr,
857 &pp_table_info->vddci_lookup_table, vddci_table, 16); 991 &pp_table_info->vddci_lookup_table, vddci_table, 4);
858 } 992 }
859 993
860 return result; 994 return result;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.h
index 995d133ba6aa..d83ed2af7aa3 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.h
@@ -26,6 +26,34 @@
26 26
27#include "hwmgr.h" 27#include "hwmgr.h"
28 28
29enum Vega10_I2CLineID {
30 Vega10_I2CLineID_DDC1 = 0x90,
31 Vega10_I2CLineID_DDC2 = 0x91,
32 Vega10_I2CLineID_DDC3 = 0x92,
33 Vega10_I2CLineID_DDC4 = 0x93,
34 Vega10_I2CLineID_DDC5 = 0x94,
35 Vega10_I2CLineID_DDC6 = 0x95,
36 Vega10_I2CLineID_SCLSDA = 0x96,
37 Vega10_I2CLineID_DDCVGA = 0x97
38};
39
40#define Vega10_I2C_DDC1DATA 0
41#define Vega10_I2C_DDC1CLK 1
42#define Vega10_I2C_DDC2DATA 2
43#define Vega10_I2C_DDC2CLK 3
44#define Vega10_I2C_DDC3DATA 4
45#define Vega10_I2C_DDC3CLK 5
46#define Vega10_I2C_SDA 40
47#define Vega10_I2C_SCL 41
48#define Vega10_I2C_DDC4DATA 65
49#define Vega10_I2C_DDC4CLK 66
50#define Vega10_I2C_DDC5DATA 0x48
51#define Vega10_I2C_DDC5CLK 0x49
52#define Vega10_I2C_DDC6DATA 0x4a
53#define Vega10_I2C_DDC6CLK 0x4b
54#define Vega10_I2C_DDCVGADATA 0x4c
55#define Vega10_I2C_DDCVGACLK 0x4d
56
29extern const struct pp_table_func vega10_pptable_funcs; 57extern const struct pp_table_func vega10_pptable_funcs;
30extern int vega10_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr); 58extern int vega10_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr);
31extern int vega10_get_powerplay_table_entry(struct pp_hwmgr *hwmgr, uint32_t entry_index, 59extern int vega10_get_powerplay_table_entry(struct pp_hwmgr *hwmgr, uint32_t entry_index,
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index aefca0b03f38..c31e660e35db 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -3295,7 +3295,7 @@ void r100_bandwidth_update(struct radeon_device *rdev)
3295 mem_trp = ((temp >> 8) & 0x7) + 1; 3295 mem_trp = ((temp >> 8) & 0x7) + 1;
3296 mem_tras = ((temp >> 11) & 0xf) + 4; 3296 mem_tras = ((temp >> 11) & 0xf) + 4;
3297 } else if (rdev->family == CHIP_RV350 || 3297 } else if (rdev->family == CHIP_RV350 ||
3298 rdev->family <= CHIP_RV380) { 3298 rdev->family == CHIP_RV380) {
3299 /* rv3x0 */ 3299 /* rv3x0 */
3300 mem_trcd = (temp & 0x7) + 3; 3300 mem_trcd = (temp & 0x7) + 3;
3301 mem_trp = ((temp >> 8) & 0x7) + 3; 3301 mem_trp = ((temp >> 8) & 0x7) + 3;
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 2e400dc414e3..c1c8e2208a21 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -499,6 +499,7 @@ struct radeon_bo {
499 u32 tiling_flags; 499 u32 tiling_flags;
500 u32 pitch; 500 u32 pitch;
501 int surface_reg; 501 int surface_reg;
502 unsigned prime_shared_count;
502 /* list of all virtual address to which this bo 503 /* list of all virtual address to which this bo
503 * is associated to 504 * is associated to
504 */ 505 */
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index a8442f7196d6..df6b58c08544 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -164,6 +164,16 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
164 p->relocs[i].allowed_domains = domain; 164 p->relocs[i].allowed_domains = domain;
165 } 165 }
166 166
167 /* Objects shared as dma-bufs cannot be moved to VRAM */
168 if (p->relocs[i].robj->prime_shared_count) {
169 p->relocs[i].allowed_domains &= ~RADEON_GEM_DOMAIN_VRAM;
170 if (!p->relocs[i].allowed_domains) {
171 DRM_ERROR("BO associated with dma-buf cannot "
172 "be moved to VRAM\n");
173 return -EINVAL;
174 }
175 }
176
167 p->relocs[i].tv.bo = &p->relocs[i].robj->tbo; 177 p->relocs[i].tv.bo = &p->relocs[i].robj->tbo;
168 p->relocs[i].tv.shared = !r->write_domain; 178 p->relocs[i].tv.shared = !r->write_domain;
169 179
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 146297a702ab..e765a638f90c 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -1354,6 +1354,12 @@ radeon_user_framebuffer_create(struct drm_device *dev,
1354 return ERR_PTR(-ENOENT); 1354 return ERR_PTR(-ENOENT);
1355 } 1355 }
1356 1356
1357 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1358 if (obj->import_attach) {
1359 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
1360 return ERR_PTR(-EINVAL);
1361 }
1362
1357 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); 1363 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1358 if (radeon_fb == NULL) { 1364 if (radeon_fb == NULL) {
1359 drm_gem_object_unreference_unlocked(obj); 1365 drm_gem_object_unreference_unlocked(obj);
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index 9b0b123ce079..dddb372de2b9 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -120,6 +120,10 @@ static int radeon_gem_set_domain(struct drm_gem_object *gobj,
120 return r; 120 return r;
121 } 121 }
122 } 122 }
123 if (domain == RADEON_GEM_DOMAIN_VRAM && robj->prime_shared_count) {
124 /* A BO that is associated with a dma-buf cannot be sensibly migrated to VRAM */
125 return -EINVAL;
126 }
123 return 0; 127 return 0;
124} 128}
125 129
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 74b276060c20..bec2ec056de4 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -352,6 +352,11 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
352 352
353 return 0; 353 return 0;
354 } 354 }
355 if (bo->prime_shared_count && domain == RADEON_GEM_DOMAIN_VRAM) {
356 /* A BO shared as a dma-buf cannot be sensibly migrated to VRAM */
357 return -EINVAL;
358 }
359
355 radeon_ttm_placement_from_domain(bo, domain); 360 radeon_ttm_placement_from_domain(bo, domain);
356 for (i = 0; i < bo->placement.num_placement; i++) { 361 for (i = 0; i < bo->placement.num_placement; i++) {
357 /* force to pin into visible video ram */ 362 /* force to pin into visible video ram */
diff --git a/drivers/gpu/drm/radeon/radeon_prime.c b/drivers/gpu/drm/radeon/radeon_prime.c
index f3609c97496b..7110d403322c 100644
--- a/drivers/gpu/drm/radeon/radeon_prime.c
+++ b/drivers/gpu/drm/radeon/radeon_prime.c
@@ -77,6 +77,7 @@ struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
77 list_add_tail(&bo->list, &rdev->gem.objects); 77 list_add_tail(&bo->list, &rdev->gem.objects);
78 mutex_unlock(&rdev->gem.mutex); 78 mutex_unlock(&rdev->gem.mutex);
79 79
80 bo->prime_shared_count = 1;
80 return &bo->gem_base; 81 return &bo->gem_base;
81} 82}
82 83
@@ -91,6 +92,9 @@ int radeon_gem_prime_pin(struct drm_gem_object *obj)
91 92
92 /* pin buffer into GTT */ 93 /* pin buffer into GTT */
93 ret = radeon_bo_pin(bo, RADEON_GEM_DOMAIN_GTT, NULL); 94 ret = radeon_bo_pin(bo, RADEON_GEM_DOMAIN_GTT, NULL);
95 if (likely(ret == 0))
96 bo->prime_shared_count++;
97
94 radeon_bo_unreserve(bo); 98 radeon_bo_unreserve(bo);
95 return ret; 99 return ret;
96} 100}
@@ -105,6 +109,8 @@ void radeon_gem_prime_unpin(struct drm_gem_object *obj)
105 return; 109 return;
106 110
107 radeon_bo_unpin(bo); 111 radeon_bo_unpin(bo);
112 if (bo->prime_shared_count)
113 bo->prime_shared_count--;
108 radeon_bo_unreserve(bo); 114 radeon_bo_unreserve(bo);
109} 115}
110 116
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-31 14:00:12 -0400