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authorAlex Xie <AlexBin.Xie@amd.com>2016-06-06 18:21:09 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-07-07 14:51:27 -0400
commit21718497687c054ed4f936c1ef306b3acf69a626 (patch)
treed08a0dbe97c90e5a7d1fe201b8a74dc7d16fa19e /drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
parent3a6f8e0c7294ce1c0bdeaa778df1095197b4cf6a (diff)
drm/amdgpu: Initialize the variables in a straight-forward way
Initialize the variable in a straight-forward way instead of hiding the initialization inside the loop. This can also reduce one function call. Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c34
1 files changed, 28 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 8dafbd3c427f..2c22ec040a16 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -762,15 +762,36 @@ static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
762{ 762{
763 const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; 763 const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
764 764
765 uint64_t cur_pe_start = ~0, cur_pe_end = ~0, cur_dst = ~0; 765 uint64_t cur_pe_start, cur_pe_end, cur_dst;
766 uint64_t addr; /* next GPU address to be updated */ 766 uint64_t addr; /* next GPU address to be updated */
767 uint64_t pt_idx;
768 struct amdgpu_bo *pt;
769 unsigned nptes; /* next number of ptes to be updated */
770 uint64_t next_pe_start;
771
772 /* initialize the variables */
773 addr = start;
774 pt_idx = addr >> amdgpu_vm_block_size;
775 pt = vm->page_tables[pt_idx].entry.robj;
776
777 if ((addr & ~mask) == (end & ~mask))
778 nptes = end - addr;
779 else
780 nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
781
782 cur_pe_start = amdgpu_bo_gpu_offset(pt);
783 cur_pe_start += (addr & mask) * 8;
784 cur_pe_end = cur_pe_start + 8 * nptes;
785 cur_dst = dst;
786
787 /* for next ptb*/
788 addr += nptes;
789 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
767 790
768 /* walk over the address space and update the page tables */ 791 /* walk over the address space and update the page tables */
769 for (addr = start; addr < end; ) { 792 while (addr < end) {
770 uint64_t pt_idx = addr >> amdgpu_vm_block_size; 793 pt_idx = addr >> amdgpu_vm_block_size;
771 struct amdgpu_bo *pt = vm->page_tables[pt_idx].entry.robj; 794 pt = vm->page_tables[pt_idx].entry.robj;
772 unsigned nptes; /* next number of ptes to be updated */
773 uint64_t next_pe_start;
774 795
775 if ((addr & ~mask) == (end & ~mask)) 796 if ((addr & ~mask) == (end & ~mask))
776 nptes = end - addr; 797 nptes = end - addr;
@@ -796,6 +817,7 @@ static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
796 cur_dst = dst; 817 cur_dst = dst;
797 } 818 }
798 819
820 /* for next ptb*/
799 addr += nptes; 821 addr += nptes;
800 dst += nptes * AMDGPU_GPU_PAGE_SIZE; 822 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
801 } 823 }