drm/amdgpu: introduce AMDGPU_GEM_CREATE_EXPLICIT_SYNC v2

Introduce a flag to signal that access to a BO will be synchronized
through an external mechanism.

Currently all buffers shared between contexts are subject to implicit
synchronization. However, this is only required for protocols that
currently don't support an explicit synchronization mechanism (DRI2/3).

This patch introduces the AMDGPU_GEM_CREATE_EXPLICIT_SYNC, so that
users can specify when it is safe to disable implicit sync.

v2: only disable explicit sync in amdgpu_cs_ioctl

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 4 insertions, 4 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index eb4a01c14eee..c559d76ff695 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1035,7 +1035,7 @@ static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm,
         int r;
 
         amdgpu_sync_create(&sync);
-        amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner);
+        amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, false);
         r = amdgpu_sync_wait(&sync, true);
         amdgpu_sync_free(&sync);
 
@@ -1176,11 +1176,11 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev,
                         amdgpu_ring_pad_ib(ring, params.ib);
                         amdgpu_sync_resv(adev, &job->sync,
                                          parent->base.bo->tbo.resv,
-                                         AMDGPU_FENCE_OWNER_VM);
+                                         AMDGPU_FENCE_OWNER_VM, false);
                         if (shadow)
                                 amdgpu_sync_resv(adev, &job->sync,
                                                  shadow->tbo.resv,
-                                                 AMDGPU_FENCE_OWNER_VM);
+                                                 AMDGPU_FENCE_OWNER_VM, false);
 
                         WARN_ON(params.ib->length_dw > ndw);
                         r = amdgpu_job_submit(job, ring, &vm->entity,
@@ -1644,7 +1644,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
                 goto error_free;
 
         r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv,
-                             owner);
+                             owner, false);
         if (r)
                 goto error_free;