diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2017-12-15 16:18:00 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-12-18 10:59:40 -0500 |
| commit | 2990a1fc012e1bb4523a54d2c27eebc21a2c7e7e (patch) | |
| tree | e07272cef54677f36064067882d5135ce5c69422 /drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | |
| parent | f5ec697e37023ce60dc1c38bf6b2bf32de767376 (diff) | |
drm/amdgpu: rename ip block helper functions
add device to the name for consistency.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 641deb0527ae..9857d482c942 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | |||
| @@ -311,10 +311,10 @@ static void amdgpu_vce_idle_work_handler(struct work_struct *work) | |||
| 311 | amdgpu_dpm_enable_vce(adev, false); | 311 | amdgpu_dpm_enable_vce(adev, false); |
| 312 | } else { | 312 | } else { |
| 313 | amdgpu_asic_set_vce_clocks(adev, 0, 0); | 313 | amdgpu_asic_set_vce_clocks(adev, 0, 0); |
| 314 | amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, | 314 | amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, |
| 315 | AMD_PG_STATE_GATE); | 315 | AMD_PG_STATE_GATE); |
| 316 | amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, | 316 | amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, |
| 317 | AMD_CG_STATE_GATE); | 317 | AMD_CG_STATE_GATE); |
| 318 | } | 318 | } |
| 319 | } else { | 319 | } else { |
| 320 | schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT); | 320 | schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT); |
| @@ -343,10 +343,10 @@ void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring) | |||
| 343 | amdgpu_dpm_enable_vce(adev, true); | 343 | amdgpu_dpm_enable_vce(adev, true); |
| 344 | } else { | 344 | } else { |
| 345 | amdgpu_asic_set_vce_clocks(adev, 53300, 40000); | 345 | amdgpu_asic_set_vce_clocks(adev, 53300, 40000); |
| 346 | amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, | 346 | amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, |
| 347 | AMD_CG_STATE_UNGATE); | 347 | AMD_CG_STATE_UNGATE); |
| 348 | amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, | 348 | amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, |
| 349 | AMD_PG_STATE_UNGATE); | 349 | AMD_PG_STATE_UNGATE); |
| 350 | 350 | ||
| 351 | } | 351 | } |
| 352 | } | 352 | } |