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authorAlex Deucher <alexander.deucher@amd.com>2017-12-15 16:18:00 -0500
committerAlex Deucher <alexander.deucher@amd.com>2017-12-18 10:59:40 -0500
commit2990a1fc012e1bb4523a54d2c27eebc21a2c7e7e (patch)
treee07272cef54677f36064067882d5135ce5c69422
parentf5ec697e37023ce60dc1c38bf6b2bf32de767376 (diff)
drm/amdgpu: rename ip block helper functions
add device to the name for consistency. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h38
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c50
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c16
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/ci_dpm.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik.c88
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/kv_dpm.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si.c54
-rw-r--r--drivers/gpu/drm/amd/amdgpu/soc15.c46
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c132
14 files changed, 252 insertions, 246 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a8390abe13a6..5c016b3d494d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -224,17 +224,18 @@ enum amdgpu_kiq_irq {
224 AMDGPU_CP_KIQ_IRQ_LAST 224 AMDGPU_CP_KIQ_IRQ_LAST
225}; 225};
226 226
227int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 227int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,
228 enum amd_ip_block_type block_type, 228 enum amd_ip_block_type block_type,
229 enum amd_clockgating_state state); 229 enum amd_clockgating_state state);
230int amdgpu_set_powergating_state(struct amdgpu_device *adev, 230int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,
231 enum amd_ip_block_type block_type, 231 enum amd_ip_block_type block_type,
232 enum amd_powergating_state state); 232 enum amd_powergating_state state);
233void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags); 233void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
234int amdgpu_wait_for_idle(struct amdgpu_device *adev, 234 u32 *flags);
235 enum amd_ip_block_type block_type); 235int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
236bool amdgpu_is_idle(struct amdgpu_device *adev, 236 enum amd_ip_block_type block_type);
237 enum amd_ip_block_type block_type); 237bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
238 enum amd_ip_block_type block_type);
238 239
239#define AMDGPU_MAX_IP_NUM 16 240#define AMDGPU_MAX_IP_NUM 16
240 241
@@ -259,15 +260,16 @@ struct amdgpu_ip_block {
259 const struct amdgpu_ip_block_version *version; 260 const struct amdgpu_ip_block_version *version;
260}; 261};
261 262
262int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 263int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
263 enum amd_ip_block_type type, 264 enum amd_ip_block_type type,
264 u32 major, u32 minor); 265 u32 major, u32 minor);
265 266
266struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, 267struct amdgpu_ip_block *
267 enum amd_ip_block_type type); 268amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
269 enum amd_ip_block_type type);
268 270
269int amdgpu_ip_block_add(struct amdgpu_device *adev, 271int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
270 const struct amdgpu_ip_block_version *ip_block_version); 272 const struct amdgpu_ip_block_version *ip_block_version);
271 273
272/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 274/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
273struct amdgpu_buffer_funcs { 275struct amdgpu_buffer_funcs {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index c04f44a90392..a29362f9ef41 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -277,7 +277,7 @@ static int acp_hw_init(void *handle)
277 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 277 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
278 278
279 const struct amdgpu_ip_block *ip_block = 279 const struct amdgpu_ip_block *ip_block =
280 amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP); 280 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP);
281 281
282 if (!ip_block) 282 if (!ip_block)
283 return -EINVAL; 283 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3135287c0f5b..38e14525721c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -937,9 +937,9 @@ static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
937 .can_switch = amdgpu_switcheroo_can_switch, 937 .can_switch = amdgpu_switcheroo_can_switch,
938}; 938};
939 939
940int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 940int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,
941 enum amd_ip_block_type block_type, 941 enum amd_ip_block_type block_type,
942 enum amd_clockgating_state state) 942 enum amd_clockgating_state state)
943{ 943{
944 int i, r = 0; 944 int i, r = 0;
945 945
@@ -959,9 +959,9 @@ int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
959 return r; 959 return r;
960} 960}
961 961
962int amdgpu_set_powergating_state(struct amdgpu_device *adev, 962int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,
963 enum amd_ip_block_type block_type, 963 enum amd_ip_block_type block_type,
964 enum amd_powergating_state state) 964 enum amd_powergating_state state)
965{ 965{
966 int i, r = 0; 966 int i, r = 0;
967 967
@@ -981,7 +981,8 @@ int amdgpu_set_powergating_state(struct amdgpu_device *adev,
981 return r; 981 return r;
982} 982}
983 983
984void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) 984void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
985 u32 *flags)
985{ 986{
986 int i; 987 int i;
987 988
@@ -993,8 +994,8 @@ void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
993 } 994 }
994} 995}
995 996
996int amdgpu_wait_for_idle(struct amdgpu_device *adev, 997int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
997 enum amd_ip_block_type block_type) 998 enum amd_ip_block_type block_type)
998{ 999{
999 int i, r; 1000 int i, r;
1000 1001
@@ -1012,8 +1013,8 @@ int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1012 1013
1013} 1014}
1014 1015
1015bool amdgpu_is_idle(struct amdgpu_device *adev, 1016bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1016 enum amd_ip_block_type block_type) 1017 enum amd_ip_block_type block_type)
1017{ 1018{
1018 int i; 1019 int i;
1019 1020
@@ -1027,8 +1028,9 @@ bool amdgpu_is_idle(struct amdgpu_device *adev,
1027 1028
1028} 1029}
1029 1030
1030struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, 1031struct amdgpu_ip_block *
1031 enum amd_ip_block_type type) 1032amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1033 enum amd_ip_block_type type)
1032{ 1034{
1033 int i; 1035 int i;
1034 1036
@@ -1040,7 +1042,7 @@ struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
1040} 1042}
1041 1043
1042/** 1044/**
1043 * amdgpu_ip_block_version_cmp 1045 * amdgpu_device_ip_block_version_cmp
1044 * 1046 *
1045 * @adev: amdgpu_device pointer 1047 * @adev: amdgpu_device pointer
1046 * @type: enum amd_ip_block_type 1048 * @type: enum amd_ip_block_type
@@ -1050,11 +1052,11 @@ struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
1050 * return 0 if equal or greater 1052 * return 0 if equal or greater
1051 * return 1 if smaller or the ip_block doesn't exist 1053 * return 1 if smaller or the ip_block doesn't exist
1052 */ 1054 */
1053int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 1055int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1054 enum amd_ip_block_type type, 1056 enum amd_ip_block_type type,
1055 u32 major, u32 minor) 1057 u32 major, u32 minor)
1056{ 1058{
1057 struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type); 1059 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1058 1060
1059 if (ip_block && ((ip_block->version->major > major) || 1061 if (ip_block && ((ip_block->version->major > major) ||
1060 ((ip_block->version->major == major) && 1062 ((ip_block->version->major == major) &&
@@ -1065,7 +1067,7 @@ int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1065} 1067}
1066 1068
1067/** 1069/**
1068 * amdgpu_ip_block_add 1070 * amdgpu_device_ip_block_add
1069 * 1071 *
1070 * @adev: amdgpu_device pointer 1072 * @adev: amdgpu_device pointer
1071 * @ip_block_version: pointer to the IP to add 1073 * @ip_block_version: pointer to the IP to add
@@ -1073,8 +1075,8 @@ int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1073 * Adds the IP block driver information to the collection of IPs 1075 * Adds the IP block driver information to the collection of IPs
1074 * on the asic. 1076 * on the asic.
1075 */ 1077 */
1076int amdgpu_ip_block_add(struct amdgpu_device *adev, 1078int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1077 const struct amdgpu_ip_block_version *ip_block_version) 1079 const struct amdgpu_ip_block_version *ip_block_version)
1078{ 1080{
1079 if (!ip_block_version) 1081 if (!ip_block_version)
1080 return -EINVAL; 1082 return -EINVAL;
@@ -1569,10 +1571,10 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
1569 amdgpu_virt_request_full_gpu(adev, false); 1571 amdgpu_virt_request_full_gpu(adev, false);
1570 1572
1571 /* ungate SMC block first */ 1573 /* ungate SMC block first */
1572 r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, 1574 r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1573 AMD_CG_STATE_UNGATE); 1575 AMD_CG_STATE_UNGATE);
1574 if (r) { 1576 if (r) {
1575 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r); 1577 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r);
1576 } 1578 }
1577 1579
1578 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 1580 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 83205b93e62d..01a996c6b802 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1278,16 +1278,16 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1278 /* XXX select vce level based on ring/task */ 1278 /* XXX select vce level based on ring/task */
1279 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; 1279 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
1280 mutex_unlock(&adev->pm.mutex); 1280 mutex_unlock(&adev->pm.mutex);
1281 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 1281 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1282 AMD_CG_STATE_UNGATE); 1282 AMD_CG_STATE_UNGATE);
1283 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 1283 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1284 AMD_PG_STATE_UNGATE); 1284 AMD_PG_STATE_UNGATE);
1285 amdgpu_pm_compute_clocks(adev); 1285 amdgpu_pm_compute_clocks(adev);
1286 } else { 1286 } else {
1287 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 1287 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1288 AMD_PG_STATE_GATE); 1288 AMD_PG_STATE_GATE);
1289 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 1289 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1290 AMD_CG_STATE_GATE); 1290 AMD_CG_STATE_GATE);
1291 mutex_lock(&adev->pm.mutex); 1291 mutex_lock(&adev->pm.mutex);
1292 adev->pm.dpm.vce_active = false; 1292 adev->pm.dpm.vce_active = false;
1293 mutex_unlock(&adev->pm.mutex); 1293 mutex_unlock(&adev->pm.mutex);
@@ -1584,7 +1584,7 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1584 struct drm_device *ddev = adev->ddev; 1584 struct drm_device *ddev = adev->ddev;
1585 u32 flags = 0; 1585 u32 flags = 0;
1586 1586
1587 amdgpu_get_clockgating_state(adev, &flags); 1587 amdgpu_device_ip_get_clockgating_state(adev, &flags);
1588 seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags); 1588 seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
1589 amdgpu_parse_cg_state(m, flags); 1589 amdgpu_parse_cg_state(m, flags);
1590 seq_printf(m, "\n"); 1590 seq_printf(m, "\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 916e51670bfd..bd6d3a1c1d65 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -244,7 +244,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
244 } 244 }
245 245
246 /* from uvd v5.0 HW addressing capacity increased to 64 bits */ 246 /* from uvd v5.0 HW addressing capacity increased to 64 bits */
247 if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) 247 if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
248 adev->uvd.address_64_bit = true; 248 adev->uvd.address_64_bit = true;
249 249
250 switch (adev->asic_type) { 250 switch (adev->asic_type) {
@@ -1153,10 +1153,10 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1153 } else { 1153 } else {
1154 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1154 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1155 /* shutdown the UVD block */ 1155 /* shutdown the UVD block */
1156 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1156 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1157 AMD_PG_STATE_GATE); 1157 AMD_PG_STATE_GATE);
1158 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1158 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1159 AMD_CG_STATE_GATE); 1159 AMD_CG_STATE_GATE);
1160 } 1160 }
1161 } else { 1161 } else {
1162 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1162 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
@@ -1176,10 +1176,10 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
1176 amdgpu_dpm_enable_uvd(adev, true); 1176 amdgpu_dpm_enable_uvd(adev, true);
1177 } else { 1177 } else {
1178 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1178 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1179 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1179 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1180 AMD_CG_STATE_UNGATE); 1180 AMD_CG_STATE_UNGATE);
1181 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1181 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1182 AMD_PG_STATE_UNGATE); 1182 AMD_PG_STATE_UNGATE);
1183 } 1183 }
1184 } 1184 }
1185} 1185}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 641deb0527ae..9857d482c942 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -311,10 +311,10 @@ static void amdgpu_vce_idle_work_handler(struct work_struct *work)
311 amdgpu_dpm_enable_vce(adev, false); 311 amdgpu_dpm_enable_vce(adev, false);
312 } else { 312 } else {
313 amdgpu_asic_set_vce_clocks(adev, 0, 0); 313 amdgpu_asic_set_vce_clocks(adev, 0, 0);
314 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 314 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
315 AMD_PG_STATE_GATE); 315 AMD_PG_STATE_GATE);
316 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 316 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
317 AMD_CG_STATE_GATE); 317 AMD_CG_STATE_GATE);
318 } 318 }
319 } else { 319 } else {
320 schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT); 320 schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT);
@@ -343,10 +343,10 @@ void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring)
343 amdgpu_dpm_enable_vce(adev, true); 343 amdgpu_dpm_enable_vce(adev, true);
344 } else { 344 } else {
345 amdgpu_asic_set_vce_clocks(adev, 53300, 40000); 345 amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
346 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 346 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
347 AMD_CG_STATE_UNGATE); 347 AMD_CG_STATE_UNGATE);
348 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 348 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
349 AMD_PG_STATE_UNGATE); 349 AMD_PG_STATE_UNGATE);
350 350
351 } 351 }
352 } 352 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 564e1b1962f1..398abbcbf029 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -741,7 +741,7 @@ void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
741 741
742 has_compute_vm_bug = false; 742 has_compute_vm_bug = false;
743 743
744 ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); 744 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
745 if (ip_block) { 745 if (ip_block) {
746 /* Compute has a VM bug for GFX version < 7. 746 /* Compute has a VM bug for GFX version < 7.
747 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/ 747 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index f11c0aacf19f..a0943aa8d1d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -891,12 +891,12 @@ static void ci_dpm_powergate_uvd(void *handle, bool gate)
891 891
892 if (gate) { 892 if (gate) {
893 /* stop the UVD block */ 893 /* stop the UVD block */
894 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 894 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
895 AMD_PG_STATE_GATE); 895 AMD_PG_STATE_GATE);
896 ci_update_uvd_dpm(adev, gate); 896 ci_update_uvd_dpm(adev, gate);
897 } else { 897 } else {
898 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 898 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
899 AMD_PG_STATE_UNGATE); 899 AMD_PG_STATE_UNGATE);
900 ci_update_uvd_dpm(adev, gate); 900 ci_update_uvd_dpm(adev, gate);
901 } 901 }
902} 902}
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 132ba226f289..6a92abc736e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1974,77 +1974,77 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
1974 1974
1975 switch (adev->asic_type) { 1975 switch (adev->asic_type) {
1976 case CHIP_BONAIRE: 1976 case CHIP_BONAIRE:
1977 amdgpu_ip_block_add(adev, &cik_common_ip_block); 1977 amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
1978 amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block); 1978 amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
1979 amdgpu_ip_block_add(adev, &cik_ih_ip_block); 1979 amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
1980 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1980 amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
1981 if (adev->enable_virtual_display) 1981 if (adev->enable_virtual_display)
1982 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 1982 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1983#if defined(CONFIG_DRM_AMD_DC) 1983#if defined(CONFIG_DRM_AMD_DC)
1984 else if (amdgpu_device_has_dc_support(adev)) 1984 else if (amdgpu_device_has_dc_support(adev))
1985 amdgpu_ip_block_add(adev, &dm_ip_block); 1985 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1986#endif 1986#endif
1987 else 1987 else
1988 amdgpu_ip_block_add(adev, &dce_v8_2_ip_block); 1988 amdgpu_device_ip_block_add(adev, &dce_v8_2_ip_block);
1989 amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block); 1989 amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);
1990 amdgpu_ip_block_add(adev, &cik_sdma_ip_block); 1990 amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
1991 amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block); 1991 amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
1992 amdgpu_ip_block_add(adev, &vce_v2_0_ip_block); 1992 amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
1993 break; 1993 break;
1994 case CHIP_HAWAII: 1994 case CHIP_HAWAII:
1995 amdgpu_ip_block_add(adev, &cik_common_ip_block); 1995 amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
1996 amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block); 1996 amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
1997 amdgpu_ip_block_add(adev, &cik_ih_ip_block); 1997 amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
1998 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1998 amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
1999 if (adev->enable_virtual_display) 1999 if (adev->enable_virtual_display)
2000 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 2000 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
2001#if defined(CONFIG_DRM_AMD_DC) 2001#if defined(CONFIG_DRM_AMD_DC)
2002 else if (amdgpu_device_has_dc_support(adev)) 2002 else if (amdgpu_device_has_dc_support(adev))
2003 amdgpu_ip_block_add(adev, &dm_ip_block); 2003 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2004#endif 2004#endif
2005 else 2005 else
2006 amdgpu_ip_block_add(adev, &dce_v8_5_ip_block); 2006 amdgpu_device_ip_block_add(adev, &dce_v8_5_ip_block);
2007 amdgpu_ip_block_add(adev, &gfx_v7_3_ip_block); 2007 amdgpu_device_ip_block_add(adev, &gfx_v7_3_ip_block);
2008 amdgpu_ip_block_add(adev, &cik_sdma_ip_block); 2008 amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
2009 amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block); 2009 amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
2010 amdgpu_ip_block_add(adev, &vce_v2_0_ip_block); 2010 amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
2011 break; 2011 break;
2012 case CHIP_KAVERI: 2012 case CHIP_KAVERI:
2013 amdgpu_ip_block_add(adev, &cik_common_ip_block); 2013 amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
2014 amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block); 2014 amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
2015 amdgpu_ip_block_add(adev, &cik_ih_ip_block); 2015 amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
2016 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 2016 amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
2017 if (adev->enable_virtual_display) 2017 if (adev->enable_virtual_display)
2018 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 2018 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
2019#if defined(CONFIG_DRM_AMD_DC) 2019#if defined(CONFIG_DRM_AMD_DC)
2020 else if (amdgpu_device_has_dc_support(adev)) 2020 else if (amdgpu_device_has_dc_support(adev))
2021 amdgpu_ip_block_add(adev, &dm_ip_block); 2021 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2022#endif 2022#endif
2023 else 2023 else
2024 amdgpu_ip_block_add(adev, &dce_v8_1_ip_block); 2024 amdgpu_device_ip_block_add(adev, &dce_v8_1_ip_block);
2025 amdgpu_ip_block_add(adev, &gfx_v7_1_ip_block); 2025 amdgpu_device_ip_block_add(adev, &gfx_v7_1_ip_block);
2026 amdgpu_ip_block_add(adev, &cik_sdma_ip_block); 2026 amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
2027 amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block); 2027 amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
2028 amdgpu_ip_block_add(adev, &vce_v2_0_ip_block); 2028 amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
2029 break; 2029 break;
2030 case CHIP_KABINI: 2030 case CHIP_KABINI:
2031 case CHIP_MULLINS: 2031 case CHIP_MULLINS:
2032 amdgpu_ip_block_add(adev, &cik_common_ip_block); 2032 amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
2033 amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block); 2033 amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
2034 amdgpu_ip_block_add(adev, &cik_ih_ip_block); 2034 amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
2035 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 2035 amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
2036 if (adev->enable_virtual_display) 2036 if (adev->enable_virtual_display)
2037 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 2037 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
2038#if defined(CONFIG_DRM_AMD_DC) 2038#if defined(CONFIG_DRM_AMD_DC)
2039 else if (amdgpu_device_has_dc_support(adev)) 2039 else if (amdgpu_device_has_dc_support(adev))
2040 amdgpu_ip_block_add(adev, &dm_ip_block); 2040 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2041#endif 2041#endif
2042 else 2042 else
2043 amdgpu_ip_block_add(adev, &dce_v8_3_ip_block); 2043 amdgpu_device_ip_block_add(adev, &dce_v8_3_ip_block);
2044 amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block); 2044 amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);
2045 amdgpu_ip_block_add(adev, &cik_sdma_ip_block); 2045 amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
2046 amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block); 2046 amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
2047 amdgpu_ip_block_add(adev, &vce_v2_0_ip_block); 2047 amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
2048 break; 2048 break;
2049 default: 2049 default:
2050 /* FIXME: not supported yet */ 2050 /* FIXME: not supported yet */
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 4a9c28cd144d..46550b588982 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5062,8 +5062,9 @@ static int gfx_v8_0_hw_fini(void *handle)
5062 gfx_v8_0_cp_enable(adev, false); 5062 gfx_v8_0_cp_enable(adev, false);
5063 gfx_v8_0_rlc_stop(adev); 5063 gfx_v8_0_rlc_stop(adev);
5064 5064
5065 amdgpu_set_powergating_state(adev, 5065 amdgpu_device_ip_set_powergating_state(adev,
5066 AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_UNGATE); 5066 AMD_IP_BLOCK_TYPE_GFX,
5067 AMD_PG_STATE_UNGATE);
5067 5068
5068 return 0; 5069 return 0;
5069} 5070}
@@ -5480,8 +5481,9 @@ static int gfx_v8_0_late_init(void *handle)
5480 if (r) 5481 if (r)
5481 return r; 5482 return r;
5482 5483
5483 amdgpu_set_powergating_state(adev, 5484 amdgpu_device_ip_set_powergating_state(adev,
5484 AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_GATE); 5485 AMD_IP_BLOCK_TYPE_GFX,
5486 AMD_PG_STATE_GATE);
5485 5487
5486 return 0; 5488 return 0;
5487} 5489}
@@ -5492,10 +5494,10 @@ static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *ade
5492 if ((adev->asic_type == CHIP_POLARIS11) || 5494 if ((adev->asic_type == CHIP_POLARIS11) ||
5493 (adev->asic_type == CHIP_POLARIS12)) 5495 (adev->asic_type == CHIP_POLARIS12))
5494 /* Send msg to SMU via Powerplay */ 5496 /* Send msg to SMU via Powerplay */
5495 amdgpu_set_powergating_state(adev, 5497 amdgpu_device_ip_set_powergating_state(adev,
5496 AMD_IP_BLOCK_TYPE_SMC, 5498 AMD_IP_BLOCK_TYPE_SMC,
5497 enable ? 5499 enable ?
5498 AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE); 5500 AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE);
5499 5501
5500 WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0); 5502 WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
5501} 5503}
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index f33d1ffdb20b..d9e9e52a0def 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -1682,8 +1682,8 @@ static void kv_dpm_powergate_uvd(void *handle, bool gate)
1682 1682
1683 if (gate) { 1683 if (gate) {
1684 /* stop the UVD block */ 1684 /* stop the UVD block */
1685 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1685 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1686 AMD_PG_STATE_GATE); 1686 AMD_PG_STATE_GATE);
1687 kv_update_uvd_dpm(adev, gate); 1687 kv_update_uvd_dpm(adev, gate);
1688 if (pi->caps_uvd_pg) 1688 if (pi->caps_uvd_pg)
1689 /* power off the UVD block */ 1689 /* power off the UVD block */
@@ -1695,8 +1695,8 @@ static void kv_dpm_powergate_uvd(void *handle, bool gate)
1695 /* re-init the UVD block */ 1695 /* re-init the UVD block */
1696 kv_update_uvd_dpm(adev, gate); 1696 kv_update_uvd_dpm(adev, gate);
1697 1697
1698 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1698 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1699 AMD_PG_STATE_UNGATE); 1699 AMD_PG_STATE_UNGATE);
1700 } 1700 }
1701} 1701}
1702 1702
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 78baddb5d300..543101d5a5ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1959,42 +1959,42 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
1959 case CHIP_VERDE: 1959 case CHIP_VERDE:
1960 case CHIP_TAHITI: 1960 case CHIP_TAHITI:
1961 case CHIP_PITCAIRN: 1961 case CHIP_PITCAIRN:
1962 amdgpu_ip_block_add(adev, &si_common_ip_block); 1962 amdgpu_device_ip_block_add(adev, &si_common_ip_block);
1963 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block); 1963 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
1964 amdgpu_ip_block_add(adev, &si_ih_ip_block); 1964 amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
1965 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1965 amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
1966 if (adev->enable_virtual_display) 1966 if (adev->enable_virtual_display)
1967 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 1967 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1968 else 1968 else
1969 amdgpu_ip_block_add(adev, &dce_v6_0_ip_block); 1969 amdgpu_device_ip_block_add(adev, &dce_v6_0_ip_block);
1970 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block); 1970 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
1971 amdgpu_ip_block_add(adev, &si_dma_ip_block); 1971 amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
1972 /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */ 1972 /* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */
1973 /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */ 1973 /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */
1974 break; 1974 break;
1975 case CHIP_OLAND: 1975 case CHIP_OLAND:
1976 amdgpu_ip_block_add(adev, &si_common_ip_block); 1976 amdgpu_device_ip_block_add(adev, &si_common_ip_block);
1977 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block); 1977 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
1978 amdgpu_ip_block_add(adev, &si_ih_ip_block); 1978 amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
1979 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1979 amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
1980 if (adev->enable_virtual_display) 1980 if (adev->enable_virtual_display)
1981 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 1981 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1982 else 1982 else
1983 amdgpu_ip_block_add(adev, &dce_v6_4_ip_block); 1983 amdgpu_device_ip_block_add(adev, &dce_v6_4_ip_block);
1984 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block); 1984 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
1985 amdgpu_ip_block_add(adev, &si_dma_ip_block); 1985 amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
1986 /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */ 1986 /* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */
1987 /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */ 1987 /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */
1988 break; 1988 break;
1989 case CHIP_HAINAN: 1989 case CHIP_HAINAN:
1990 amdgpu_ip_block_add(adev, &si_common_ip_block); 1990 amdgpu_device_ip_block_add(adev, &si_common_ip_block);
1991 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block); 1991 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
1992 amdgpu_ip_block_add(adev, &si_ih_ip_block); 1992 amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
1993 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1993 amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
1994 if (adev->enable_virtual_display) 1994 if (adev->enable_virtual_display)
1995 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 1995 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1996 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block); 1996 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
1997 amdgpu_ip_block_add(adev, &si_dma_ip_block); 1997 amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
1998 break; 1998 break;
1999 default: 1999 default:
2000 BUG(); 2000 BUG();
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 49ff552cd6fe..f0fb4161e866 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -533,43 +533,43 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
533 533
534 switch (adev->asic_type) { 534 switch (adev->asic_type) {
535 case CHIP_VEGA10: 535 case CHIP_VEGA10:
536 amdgpu_ip_block_add(adev, &vega10_common_ip_block); 536 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
537 amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block); 537 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
538 amdgpu_ip_block_add(adev, &vega10_ih_ip_block); 538 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
539 if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1) 539 if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1)
540 amdgpu_ip_block_add(adev, &psp_v3_1_ip_block); 540 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
541 if (!amdgpu_sriov_vf(adev)) 541 if (!amdgpu_sriov_vf(adev))
542 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 542 amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
543 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 543 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
544 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 544 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
545#if defined(CONFIG_DRM_AMD_DC) 545#if defined(CONFIG_DRM_AMD_DC)
546 else if (amdgpu_device_has_dc_support(adev)) 546 else if (amdgpu_device_has_dc_support(adev))
547 amdgpu_ip_block_add(adev, &dm_ip_block); 547 amdgpu_device_ip_block_add(adev, &dm_ip_block);
548#else 548#else
549# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15." 549# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
550#endif 550#endif
551 amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block); 551 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
552 amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block); 552 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
553 amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block); 553 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
554 amdgpu_ip_block_add(adev, &vce_v4_0_ip_block); 554 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
555 break; 555 break;
556 case CHIP_RAVEN: 556 case CHIP_RAVEN:
557 amdgpu_ip_block_add(adev, &vega10_common_ip_block); 557 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
558 amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block); 558 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
559 amdgpu_ip_block_add(adev, &vega10_ih_ip_block); 559 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
560 amdgpu_ip_block_add(adev, &psp_v10_0_ip_block); 560 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
561 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 561 amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
562 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 562 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
563 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 563 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
564#if defined(CONFIG_DRM_AMD_DC) 564#if defined(CONFIG_DRM_AMD_DC)
565 else if (amdgpu_device_has_dc_support(adev)) 565 else if (amdgpu_device_has_dc_support(adev))
566 amdgpu_ip_block_add(adev, &dm_ip_block); 566 amdgpu_device_ip_block_add(adev, &dm_ip_block);
567#else 567#else
568# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15." 568# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
569#endif 569#endif
570 amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block); 570 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
571 amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block); 571 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
572 amdgpu_ip_block_add(adev, &vcn_v1_0_ip_block); 572 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
573 break; 573 break;
574 default: 574 default:
575 return -EINVAL; 575 return -EINVAL;
@@ -616,8 +616,8 @@ static int soc15_common_early_init(void *handle)
616 616
617 adev->asic_funcs = &soc15_asic_funcs; 617 adev->asic_funcs = &soc15_asic_funcs;
618 618
619 if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) && 619 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) &&
620 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP))) 620 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP)))
621 psp_enabled = true; 621 psp_enabled = true;
622 622
623 adev->rev_id = soc15_get_rev_id(adev); 623 adev->rev_id = soc15_get_rev_id(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 0e1202914fa8..66072063bc7c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -891,8 +891,8 @@ static int vi_common_early_init(void *handle)
891 891
892 adev->asic_funcs = &vi_asic_funcs; 892 adev->asic_funcs = &vi_asic_funcs;
893 893
894 if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) && 894 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) &&
895 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC))) 895 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
896 smc_enabled = true; 896 smc_enabled = true;
897 897
898 adev->rev_id = vi_get_rev_id(adev); 898 adev->rev_id = vi_get_rev_id(adev);
@@ -1487,115 +1487,115 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
1487 switch (adev->asic_type) { 1487 switch (adev->asic_type) {
1488 case CHIP_TOPAZ: 1488 case CHIP_TOPAZ:
1489 /* topaz has no DCE, UVD, VCE */ 1489 /* topaz has no DCE, UVD, VCE */
1490 amdgpu_ip_block_add(adev, &vi_common_ip_block); 1490 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1491 amdgpu_ip_block_add(adev, &gmc_v7_4_ip_block); 1491 amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block);
1492 amdgpu_ip_block_add(adev, &iceland_ih_ip_block); 1492 amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block);
1493 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1493 amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
1494 if (adev->enable_virtual_display) 1494 if (adev->enable_virtual_display)
1495 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 1495 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1496 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); 1496 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1497 amdgpu_ip_block_add(adev, &sdma_v2_4_ip_block); 1497 amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block);
1498 break; 1498 break;
1499 case CHIP_FIJI: 1499 case CHIP_FIJI:
1500 amdgpu_ip_block_add(adev, &vi_common_ip_block); 1500 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1501 amdgpu_ip_block_add(adev, &gmc_v8_5_ip_block); 1501 amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block);
1502 amdgpu_ip_block_add(adev, &tonga_ih_ip_block); 1502 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1503 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1503 amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
1504 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 1504 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1505 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 1505 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1506#if defined(CONFIG_DRM_AMD_DC) 1506#if defined(CONFIG_DRM_AMD_DC)
1507 else if (amdgpu_device_has_dc_support(adev)) 1507 else if (amdgpu_device_has_dc_support(adev))
1508 amdgpu_ip_block_add(adev, &dm_ip_block); 1508 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1509#endif 1509#endif
1510 else 1510 else
1511 amdgpu_ip_block_add(adev, &dce_v10_1_ip_block); 1511 amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block);
1512 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); 1512 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1513 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); 1513 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1514 if (!amdgpu_sriov_vf(adev)) { 1514 if (!amdgpu_sriov_vf(adev)) {
1515 amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block); 1515 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
1516 amdgpu_ip_block_add(adev, &vce_v3_0_ip_block); 1516 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
1517 } 1517 }
1518 break; 1518 break;
1519 case CHIP_TONGA: 1519 case CHIP_TONGA:
1520 amdgpu_ip_block_add(adev, &vi_common_ip_block); 1520 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1521 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block); 1521 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1522 amdgpu_ip_block_add(adev, &tonga_ih_ip_block); 1522 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1523 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1523 amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
1524 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 1524 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1525 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 1525 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1526#if defined(CONFIG_DRM_AMD_DC) 1526#if defined(CONFIG_DRM_AMD_DC)
1527 else if (amdgpu_device_has_dc_support(adev)) 1527 else if (amdgpu_device_has_dc_support(adev))
1528 amdgpu_ip_block_add(adev, &dm_ip_block); 1528 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1529#endif 1529#endif
1530 else 1530 else
1531 amdgpu_ip_block_add(adev, &dce_v10_0_ip_block); 1531 amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block);
1532 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); 1532 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1533 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); 1533 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1534 if (!amdgpu_sriov_vf(adev)) { 1534 if (!amdgpu_sriov_vf(adev)) {
1535 amdgpu_ip_block_add(adev, &uvd_v5_0_ip_block); 1535 amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block);
1536 amdgpu_ip_block_add(adev, &vce_v3_0_ip_block); 1536 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
1537 } 1537 }
1538 break; 1538 break;
1539 case CHIP_POLARIS11: 1539 case CHIP_POLARIS11:
1540 case CHIP_POLARIS10: 1540 case CHIP_POLARIS10:
1541 case CHIP_POLARIS12: 1541 case CHIP_POLARIS12:
1542 amdgpu_ip_block_add(adev, &vi_common_ip_block); 1542 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1543 amdgpu_ip_block_add(adev, &gmc_v8_1_ip_block); 1543 amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);
1544 amdgpu_ip_block_add(adev, &tonga_ih_ip_block); 1544 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1545 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1545 amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
1546 if (adev->enable_virtual_display) 1546 if (adev->enable_virtual_display)
1547 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 1547 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1548#if defined(CONFIG_DRM_AMD_DC) 1548#if defined(CONFIG_DRM_AMD_DC)
1549 else if (amdgpu_device_has_dc_support(adev)) 1549 else if (amdgpu_device_has_dc_support(adev))
1550 amdgpu_ip_block_add(adev, &dm_ip_block); 1550 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1551#endif 1551#endif
1552 else 1552 else
1553 amdgpu_ip_block_add(adev, &dce_v11_2_ip_block); 1553 amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block);
1554 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); 1554 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1555 amdgpu_ip_block_add(adev, &sdma_v3_1_ip_block); 1555 amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block);
1556 amdgpu_ip_block_add(adev, &uvd_v6_3_ip_block); 1556 amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block);
1557 amdgpu_ip_block_add(adev, &vce_v3_4_ip_block); 1557 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
1558 break; 1558 break;
1559 case CHIP_CARRIZO: 1559 case CHIP_CARRIZO:
1560 amdgpu_ip_block_add(adev, &vi_common_ip_block); 1560 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1561 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block); 1561 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1562 amdgpu_ip_block_add(adev, &cz_ih_ip_block); 1562 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
1563 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1563 amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
1564 if (adev->enable_virtual_display) 1564 if (adev->enable_virtual_display)
1565 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 1565 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1566#if defined(CONFIG_DRM_AMD_DC) 1566#if defined(CONFIG_DRM_AMD_DC)
1567 else if (amdgpu_device_has_dc_support(adev)) 1567 else if (amdgpu_device_has_dc_support(adev))
1568 amdgpu_ip_block_add(adev, &dm_ip_block); 1568 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1569#endif 1569#endif
1570 else 1570 else
1571 amdgpu_ip_block_add(adev, &dce_v11_0_ip_block); 1571 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
1572 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); 1572 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1573 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); 1573 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1574 amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block); 1574 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
1575 amdgpu_ip_block_add(adev, &vce_v3_1_ip_block); 1575 amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block);
1576#if defined(CONFIG_DRM_AMD_ACP) 1576#if defined(CONFIG_DRM_AMD_ACP)
1577 amdgpu_ip_block_add(adev, &acp_ip_block); 1577 amdgpu_device_ip_block_add(adev, &acp_ip_block);
1578#endif 1578#endif
1579 break; 1579 break;
1580 case CHIP_STONEY: 1580 case CHIP_STONEY:
1581 amdgpu_ip_block_add(adev, &vi_common_ip_block); 1581 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1582 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block); 1582 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1583 amdgpu_ip_block_add(adev, &cz_ih_ip_block); 1583 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
1584 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1584 amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
1585 if (adev->enable_virtual_display) 1585 if (adev->enable_virtual_display)
1586 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 1586 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1587#if defined(CONFIG_DRM_AMD_DC) 1587#if defined(CONFIG_DRM_AMD_DC)
1588 else if (amdgpu_device_has_dc_support(adev)) 1588 else if (amdgpu_device_has_dc_support(adev))
1589 amdgpu_ip_block_add(adev, &dm_ip_block); 1589 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1590#endif 1590#endif
1591 else 1591 else
1592 amdgpu_ip_block_add(adev, &dce_v11_0_ip_block); 1592 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
1593 amdgpu_ip_block_add(adev, &gfx_v8_1_ip_block); 1593 amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block);
1594 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); 1594 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1595 amdgpu_ip_block_add(adev, &uvd_v6_2_ip_block); 1595 amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block);
1596 amdgpu_ip_block_add(adev, &vce_v3_4_ip_block); 1596 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
1597#if defined(CONFIG_DRM_AMD_ACP) 1597#if defined(CONFIG_DRM_AMD_ACP)
1598 amdgpu_ip_block_add(adev, &acp_ip_block); 1598 amdgpu_device_ip_block_add(adev, &acp_ip_block);
1599#endif 1599#endif
1600 break; 1600 break;
1601 default: 1601 default:
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-13 05:42:14 -0400