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path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 83205b93e62d..01a996c6b802 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1278,16 +1278,16 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1278 /* XXX select vce level based on ring/task */ 1278 /* XXX select vce level based on ring/task */
1279 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; 1279 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
1280 mutex_unlock(&adev->pm.mutex); 1280 mutex_unlock(&adev->pm.mutex);
1281 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 1281 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1282 AMD_CG_STATE_UNGATE); 1282 AMD_CG_STATE_UNGATE);
1283 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 1283 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1284 AMD_PG_STATE_UNGATE); 1284 AMD_PG_STATE_UNGATE);
1285 amdgpu_pm_compute_clocks(adev); 1285 amdgpu_pm_compute_clocks(adev);
1286 } else { 1286 } else {
1287 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 1287 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1288 AMD_PG_STATE_GATE); 1288 AMD_PG_STATE_GATE);
1289 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 1289 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1290 AMD_CG_STATE_GATE); 1290 AMD_CG_STATE_GATE);
1291 mutex_lock(&adev->pm.mutex); 1291 mutex_lock(&adev->pm.mutex);
1292 adev->pm.dpm.vce_active = false; 1292 adev->pm.dpm.vce_active = false;
1293 mutex_unlock(&adev->pm.mutex); 1293 mutex_unlock(&adev->pm.mutex);
@@ -1584,7 +1584,7 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1584 struct drm_device *ddev = adev->ddev; 1584 struct drm_device *ddev = adev->ddev;
1585 u32 flags = 0; 1585 u32 flags = 0;
1586 1586
1587 amdgpu_get_clockgating_state(adev, &flags); 1587 amdgpu_device_ip_get_clockgating_state(adev, &flags);
1588 seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags); 1588 seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
1589 amdgpu_parse_cg_state(m, flags); 1589 amdgpu_parse_cg_state(m, flags);
1590 seq_printf(m, "\n"); 1590 seq_printf(m, "\n");