drm/amdgpu: rename ip block helper functions

add device to the name for consistency.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 9 insertions, 9 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 916e51670bfd..bd6d3a1c1d65 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -244,7 +244,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
         }
 
         /* from uvd v5.0 HW addressing capacity increased to 64 bits */
-        if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
+        if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
                 adev->uvd.address_64_bit = true;
 
         switch (adev->asic_type) {
@@ -1153,10 +1153,10 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
                 } else {
                         amdgpu_asic_set_uvd_clocks(adev, 0, 0);
                         /* shutdown the UVD block */
-                        amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
-                                                            AMD_PG_STATE_GATE);
-                        amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
-                                                            AMD_CG_STATE_GATE);
+                        amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+                                                               AMD_PG_STATE_GATE);
+                        amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+                                                               AMD_CG_STATE_GATE);
                 }
         } else {
                 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
@@ -1176,10 +1176,10 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
                         amdgpu_dpm_enable_uvd(adev, true);
                 } else {
                         amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
-                        amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
-                                                            AMD_CG_STATE_UNGATE);
-                        amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
-                                                            AMD_PG_STATE_UNGATE);
+                        amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+                                                               AMD_CG_STATE_UNGATE);
+                        amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+                                                               AMD_PG_STATE_UNGATE);
                 }
         }
 }