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authorChristian König <christian.koenig@amd.com>2015-07-21 12:02:21 -0400
committerAlex Deucher <alexander.deucher@amd.com>2015-08-17 16:50:18 -0400
commit5430a3ffb0b1902e8aea4ed2ba256b1263126e8d (patch)
treec73e8f31dc1ef2f698c5f16fb8bc2c8e4d047b12 /drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
parent5ceb54c68a28fc8af5cf8d32c4fde29c97dd3c18 (diff)
drm/amdgpu: fix UVD/VCE fence handling
We need to return the sequence number to userspace even when we don't use user fences. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index f3ac9d8a5691..42d6298eb9d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -88,6 +88,7 @@ int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
88 ib->fence = NULL; 88 ib->fence = NULL;
89 ib->user = NULL; 89 ib->user = NULL;
90 ib->vm = vm; 90 ib->vm = vm;
91 ib->ctx = NULL;
91 ib->gds_base = 0; 92 ib->gds_base = 0;
92 ib->gds_size = 0; 93 ib->gds_size = 0;
93 ib->gws_base = 0; 94 ib->gws_base = 0;
@@ -214,13 +215,15 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
214 return r; 215 return r;
215 } 216 }
216 217
218 if (ib->ctx)
219 ib->sequence = amdgpu_ctx_add_fence(ib->ctx, ring,
220 &ib->fence->base);
221
217 /* wrap the last IB with fence */ 222 /* wrap the last IB with fence */
218 if (ib->user) { 223 if (ib->user) {
219 uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo); 224 uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo);
220 ib->user->sequence = amdgpu_ctx_add_fence(ib->ctx, ring,
221 &ib->fence->base);
222 addr += ib->user->offset; 225 addr += ib->user->offset;
223 amdgpu_ring_emit_fence(ring, addr, ib->user->sequence, 226 amdgpu_ring_emit_fence(ring, addr, ib->sequence,
224 AMDGPU_FENCE_FLAG_64BIT); 227 AMDGPU_FENCE_FLAG_64BIT);
225 } 228 }
226 229