drm/amdgpu: fix UVD/VCE fence handling

We need to return the sequence number to userspace
even when we don't use user fences.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

3 files changed, 9 insertions, 6 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 551143287698..e6c26c1716b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -414,8 +414,6 @@ struct amdgpu_user_fence {
         struct amdgpu_bo        *bo;
         /* write-back address offset to bo start */
         uint32_t                offset;
-        /* resulting sequence number */
-        uint64_t                sequence;
 };
 
 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
@@ -847,6 +845,8 @@ struct amdgpu_ib {
         uint32_t                        gws_base, gws_size;
         uint32_t                        oa_base, oa_size;
         uint32_t                        flags;
+        /* resulting sequence number */
+        uint64_t                        sequence;
 };
 
 enum amdgpu_ring_type {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index cef8360698be..4794e14976ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -794,7 +794,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
                 goto out;
         }
 
-        cs->out.handle = parser.uf.sequence;
+        cs->out.handle = parser.ibs[parser.num_ibs - 1].sequence;
 out:
         amdgpu_cs_parser_fini(&parser, r, true);
         up_read(&adev->exclusive_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index f3ac9d8a5691..42d6298eb9d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -88,6 +88,7 @@ int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
         ib->fence = NULL;
         ib->user = NULL;
         ib->vm = vm;
+        ib->ctx = NULL;
         ib->gds_base = 0;
         ib->gds_size = 0;
         ib->gws_base = 0;
@@ -214,13 +215,15 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
                 return r;
         }
 
+        if (ib->ctx)
+                ib->sequence = amdgpu_ctx_add_fence(ib->ctx, ring,
+                                                    &ib->fence->base);
+
         /* wrap the last IB with fence */
         if (ib->user) {
                 uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo);
-                ib->user->sequence = amdgpu_ctx_add_fence(ib->ctx, ring,
-                                                          &ib->fence->base);
                 addr += ib->user->offset;
-                amdgpu_ring_emit_fence(ring, addr, ib->user->sequence,
+                amdgpu_ring_emit_fence(ring, addr, ib->sequence,
                                        AMDGPU_FENCE_FLAG_64BIT);
         }