aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
diff options
context:
space:
mode:
authorJames Zhu <James.Zhu@amd.com>2018-05-15 15:31:24 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-05-18 17:08:12 -0400
commit10dd74eac4dba963bfa97f5092040aa75ff742d6 (patch)
treeb93a33adbbe061247ae98fb024b6100ad86407d9 /drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
parent2bb795f5ba9cd676536858a978b9df06f473af88 (diff)
drm/amdgpu/vg20:Restruct uvd.inst to support multiple instances
Vega20 has dual-UVD. Need add multiple instances support for uvd. Restruct uvd.inst, using uvd.inst[0] to replace uvd.inst->. Repurpose amdgpu_ring::me for instance index, and initialize to 0. There are no any logical changes here. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 1070f4042cbb..39ec6b8890a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -376,14 +376,14 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
376 struct amdgpu_device *adev = ring->adev; 376 struct amdgpu_device *adev = ring->adev;
377 uint64_t index; 377 uint64_t index;
378 378
379 if (ring != &adev->uvd.inst->ring) { 379 if (ring != &adev->uvd.inst[ring->me].ring) {
380 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs]; 380 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
381 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4); 381 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
382 } else { 382 } else {
383 /* put fence directly behind firmware */ 383 /* put fence directly behind firmware */
384 index = ALIGN(adev->uvd.fw->size, 8); 384 index = ALIGN(adev->uvd.fw->size, 8);
385 ring->fence_drv.cpu_addr = adev->uvd.inst->cpu_addr + index; 385 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index;
386 ring->fence_drv.gpu_addr = adev->uvd.inst->gpu_addr + index; 386 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index;
387 } 387 }
388 amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq)); 388 amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
389 amdgpu_irq_get(adev, irq_src, irq_type); 389 amdgpu_irq_get(adev, irq_src, irq_type);