diff options
author | James Zhu <James.Zhu@amd.com> | 2018-05-15 15:25:46 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2018-05-18 17:08:12 -0400 |
commit | 2bb795f5ba9cd676536858a978b9df06f473af88 (patch) | |
tree | 1fbbc0d1e3e62668a925273db2139e31f4ed381c /drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | |
parent | 602ed6c69b128b77050e178aca9e945d969f3aa8 (diff) |
drm/amdgpu/vg20:Restruct uvd to support multiple uvds
Vega20 has dual-UVD. Need Restruct amdgpu_device::uvd to support
multiple uvds. There are no any logical changes here.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index d09fcab2398f..1070f4042cbb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | |||
@@ -376,14 +376,14 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, | |||
376 | struct amdgpu_device *adev = ring->adev; | 376 | struct amdgpu_device *adev = ring->adev; |
377 | uint64_t index; | 377 | uint64_t index; |
378 | 378 | ||
379 | if (ring != &adev->uvd.ring) { | 379 | if (ring != &adev->uvd.inst->ring) { |
380 | ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs]; | 380 | ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs]; |
381 | ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4); | 381 | ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4); |
382 | } else { | 382 | } else { |
383 | /* put fence directly behind firmware */ | 383 | /* put fence directly behind firmware */ |
384 | index = ALIGN(adev->uvd.fw->size, 8); | 384 | index = ALIGN(adev->uvd.fw->size, 8); |
385 | ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index; | 385 | ring->fence_drv.cpu_addr = adev->uvd.inst->cpu_addr + index; |
386 | ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index; | 386 | ring->fence_drv.gpu_addr = adev->uvd.inst->gpu_addr + index; |
387 | } | 387 | } |
388 | amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq)); | 388 | amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq)); |
389 | amdgpu_irq_get(adev, irq_src, irq_type); | 389 | amdgpu_irq_get(adev, irq_src, irq_type); |