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authorAlex Deucher <alexander.deucher@amd.com>2019-07-25 12:44:59 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-07-31 00:24:44 -0400
commita3a09142f43c456fff7ddbc0ac867af8979a368c (patch)
treeb1d57ef098667061c24fb2c26e0bf667a3d5df9a /drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
parent1c074a63834e7414031f33c23efd87bbb8c25cea (diff)
drm/amdgpu: put the SMC into the proper state on reset/unload
When doing a GPU reset or unloading the driver, we need to put the SMU into the apprpriate state for the re-init after the reset or unload to reliably work. I don't think this is necessary for BACO because the SMU actually controls the BACO state to it needs to be active. For suspend (S3), the asic is put into D3 so the SMU would be powered down so I don't think we need to put the SMU into any special state. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_device.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c27
1 files changed, 27 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 14a9169446f5..2081649f49ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2175,6 +2175,21 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2175 DRM_ERROR("suspend of IP block <%s> failed %d\n", 2175 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2176 adev->ip_blocks[i].version->funcs->name, r); 2176 adev->ip_blocks[i].version->funcs->name, r);
2177 } 2177 }
2178 /* handle putting the SMC in the appropriate state */
2179 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2180 if (is_support_sw_smu(adev)) {
2181 /* todo */
2182 } else if (adev->powerplay.pp_funcs &&
2183 adev->powerplay.pp_funcs->set_mp1_state) {
2184 r = adev->powerplay.pp_funcs->set_mp1_state(
2185 adev->powerplay.pp_handle,
2186 adev->mp1_state);
2187 if (r) {
2188 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
2189 adev->mp1_state, r);
2190 }
2191 }
2192 }
2178 } 2193 }
2179 2194
2180 return 0; 2195 return 0;
@@ -3640,6 +3655,17 @@ static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, bool trylock)
3640 3655
3641 atomic_inc(&adev->gpu_reset_counter); 3656 atomic_inc(&adev->gpu_reset_counter);
3642 adev->in_gpu_reset = 1; 3657 adev->in_gpu_reset = 1;
3658 switch (amdgpu_asic_reset_method(adev)) {
3659 case AMD_RESET_METHOD_MODE1:
3660 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
3661 break;
3662 case AMD_RESET_METHOD_MODE2:
3663 adev->mp1_state = PP_MP1_STATE_RESET;
3664 break;
3665 default:
3666 adev->mp1_state = PP_MP1_STATE_NONE;
3667 break;
3668 }
3643 /* Block kfd: SRIOV would do it separately */ 3669 /* Block kfd: SRIOV would do it separately */
3644 if (!amdgpu_sriov_vf(adev)) 3670 if (!amdgpu_sriov_vf(adev))
3645 amdgpu_amdkfd_pre_reset(adev); 3671 amdgpu_amdkfd_pre_reset(adev);
@@ -3653,6 +3679,7 @@ static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
3653 if (!amdgpu_sriov_vf(adev)) 3679 if (!amdgpu_sriov_vf(adev))
3654 amdgpu_amdkfd_post_reset(adev); 3680 amdgpu_amdkfd_post_reset(adev);
3655 amdgpu_vf_error_trans_all(adev); 3681 amdgpu_vf_error_trans_all(adev);
3682 adev->mp1_state = PP_MP1_STATE_NONE;
3656 adev->in_gpu_reset = 0; 3683 adev->in_gpu_reset = 0;
3657 mutex_unlock(&adev->lock_reset); 3684 mutex_unlock(&adev->lock_reset);
3658} 3685}