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authorChristian König <christian.koenig@amd.com>2017-04-27 11:13:39 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-04-28 17:33:12 -0400
commit2c55b16bf0e1492ba662d884c81d324538cafce1 (patch)
tree30a13041e7b6258e3a06a1c3856f0894bba4d8a2 /drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
parent00c4855ef874e41d6b9f9b19d1d1e04bc70f0b31 (diff)
drm/amdgpu: remove unused and mostly unimplemented CGS functions v2
Those functions are all unused and some not even implemented. v2: keep cgs_get_pci_resource, it is used by the ACP driver. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c198
1 files changed, 0 insertions, 198 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 013f5f14dd75..c6dba1eaefbd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -42,82 +42,6 @@ struct amdgpu_cgs_device {
42 struct amdgpu_device *adev = \ 42 struct amdgpu_device *adev = \
43 ((struct amdgpu_cgs_device *)cgs_device)->adev 43 ((struct amdgpu_cgs_device *)cgs_device)->adev
44 44
45static int amdgpu_cgs_gpu_mem_info(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
46 uint64_t *mc_start, uint64_t *mc_size,
47 uint64_t *mem_size)
48{
49 CGS_FUNC_ADEV;
50 switch(type) {
51 case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
52 case CGS_GPU_MEM_TYPE__VISIBLE_FB:
53 *mc_start = 0;
54 *mc_size = adev->mc.visible_vram_size;
55 *mem_size = adev->mc.visible_vram_size - adev->vram_pin_size;
56 break;
57 case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
58 case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
59 *mc_start = adev->mc.visible_vram_size;
60 *mc_size = adev->mc.real_vram_size - adev->mc.visible_vram_size;
61 *mem_size = *mc_size;
62 break;
63 case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
64 case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
65 *mc_start = adev->mc.gtt_start;
66 *mc_size = adev->mc.gtt_size;
67 *mem_size = adev->mc.gtt_size - adev->gart_pin_size;
68 break;
69 default:
70 return -EINVAL;
71 }
72
73 return 0;
74}
75
76static int amdgpu_cgs_gmap_kmem(struct cgs_device *cgs_device, void *kmem,
77 uint64_t size,
78 uint64_t min_offset, uint64_t max_offset,
79 cgs_handle_t *kmem_handle, uint64_t *mcaddr)
80{
81 CGS_FUNC_ADEV;
82 int ret;
83 struct amdgpu_bo *bo;
84 struct page *kmem_page = vmalloc_to_page(kmem);
85 int npages = ALIGN(size, PAGE_SIZE) >> PAGE_SHIFT;
86
87 struct sg_table *sg = drm_prime_pages_to_sg(&kmem_page, npages);
88 ret = amdgpu_bo_create(adev, size, PAGE_SIZE, false,
89 AMDGPU_GEM_DOMAIN_GTT, 0, sg, NULL, &bo);
90 if (ret)
91 return ret;
92 ret = amdgpu_bo_reserve(bo, true);
93 if (unlikely(ret != 0))
94 return ret;
95
96 /* pin buffer into GTT */
97 ret = amdgpu_bo_pin_restricted(bo, AMDGPU_GEM_DOMAIN_GTT,
98 min_offset, max_offset, mcaddr);
99 amdgpu_bo_unreserve(bo);
100
101 *kmem_handle = (cgs_handle_t)bo;
102 return ret;
103}
104
105static int amdgpu_cgs_gunmap_kmem(struct cgs_device *cgs_device, cgs_handle_t kmem_handle)
106{
107 struct amdgpu_bo *obj = (struct amdgpu_bo *)kmem_handle;
108
109 if (obj) {
110 int r = amdgpu_bo_reserve(obj, true);
111 if (likely(r == 0)) {
112 amdgpu_bo_unpin(obj);
113 amdgpu_bo_unreserve(obj);
114 }
115 amdgpu_bo_unref(&obj);
116
117 }
118 return 0;
119}
120
121static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device, 45static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device,
122 enum cgs_gpu_mem_type type, 46 enum cgs_gpu_mem_type type,
123 uint64_t size, uint64_t align, 47 uint64_t size, uint64_t align,
@@ -349,62 +273,6 @@ static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
349 WARN(1, "Invalid indirect register space"); 273 WARN(1, "Invalid indirect register space");
350} 274}
351 275
352static uint8_t amdgpu_cgs_read_pci_config_byte(struct cgs_device *cgs_device, unsigned addr)
353{
354 CGS_FUNC_ADEV;
355 uint8_t val;
356 int ret = pci_read_config_byte(adev->pdev, addr, &val);
357 if (WARN(ret, "pci_read_config_byte error"))
358 return 0;
359 return val;
360}
361
362static uint16_t amdgpu_cgs_read_pci_config_word(struct cgs_device *cgs_device, unsigned addr)
363{
364 CGS_FUNC_ADEV;
365 uint16_t val;
366 int ret = pci_read_config_word(adev->pdev, addr, &val);
367 if (WARN(ret, "pci_read_config_word error"))
368 return 0;
369 return val;
370}
371
372static uint32_t amdgpu_cgs_read_pci_config_dword(struct cgs_device *cgs_device,
373 unsigned addr)
374{
375 CGS_FUNC_ADEV;
376 uint32_t val;
377 int ret = pci_read_config_dword(adev->pdev, addr, &val);
378 if (WARN(ret, "pci_read_config_dword error"))
379 return 0;
380 return val;
381}
382
383static void amdgpu_cgs_write_pci_config_byte(struct cgs_device *cgs_device, unsigned addr,
384 uint8_t value)
385{
386 CGS_FUNC_ADEV;
387 int ret = pci_write_config_byte(adev->pdev, addr, value);
388 WARN(ret, "pci_write_config_byte error");
389}
390
391static void amdgpu_cgs_write_pci_config_word(struct cgs_device *cgs_device, unsigned addr,
392 uint16_t value)
393{
394 CGS_FUNC_ADEV;
395 int ret = pci_write_config_word(adev->pdev, addr, value);
396 WARN(ret, "pci_write_config_word error");
397}
398
399static void amdgpu_cgs_write_pci_config_dword(struct cgs_device *cgs_device, unsigned addr,
400 uint32_t value)
401{
402 CGS_FUNC_ADEV;
403 int ret = pci_write_config_dword(adev->pdev, addr, value);
404 WARN(ret, "pci_write_config_dword error");
405}
406
407
408static int amdgpu_cgs_get_pci_resource(struct cgs_device *cgs_device, 276static int amdgpu_cgs_get_pci_resource(struct cgs_device *cgs_device,
409 enum cgs_resource_type resource_type, 277 enum cgs_resource_type resource_type,
410 uint64_t size, 278 uint64_t size,
@@ -477,56 +345,6 @@ static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigne
477 adev->mode_info.atom_context, table, args); 345 adev->mode_info.atom_context, table, args);
478} 346}
479 347
480static int amdgpu_cgs_create_pm_request(struct cgs_device *cgs_device, cgs_handle_t *request)
481{
482 /* TODO */
483 return 0;
484}
485
486static int amdgpu_cgs_destroy_pm_request(struct cgs_device *cgs_device, cgs_handle_t request)
487{
488 /* TODO */
489 return 0;
490}
491
492static int amdgpu_cgs_set_pm_request(struct cgs_device *cgs_device, cgs_handle_t request,
493 int active)
494{
495 /* TODO */
496 return 0;
497}
498
499static int amdgpu_cgs_pm_request_clock(struct cgs_device *cgs_device, cgs_handle_t request,
500 enum cgs_clock clock, unsigned freq)
501{
502 /* TODO */
503 return 0;
504}
505
506static int amdgpu_cgs_pm_request_engine(struct cgs_device *cgs_device, cgs_handle_t request,
507 enum cgs_engine engine, int powered)
508{
509 /* TODO */
510 return 0;
511}
512
513
514
515static int amdgpu_cgs_pm_query_clock_limits(struct cgs_device *cgs_device,
516 enum cgs_clock clock,
517 struct cgs_clock_limits *limits)
518{
519 /* TODO */
520 return 0;
521}
522
523static int amdgpu_cgs_set_camera_voltages(struct cgs_device *cgs_device, uint32_t mask,
524 const uint32_t *voltages)
525{
526 DRM_ERROR("not implemented");
527 return -EPERM;
528}
529
530struct cgs_irq_params { 348struct cgs_irq_params {
531 unsigned src_id; 349 unsigned src_id;
532 cgs_irq_source_set_func_t set; 350 cgs_irq_source_set_func_t set;
@@ -1269,9 +1087,6 @@ static int amdgpu_cgs_call_acpi_method(struct cgs_device *cgs_device,
1269} 1087}
1270 1088
1271static const struct cgs_ops amdgpu_cgs_ops = { 1089static const struct cgs_ops amdgpu_cgs_ops = {
1272 .gpu_mem_info = amdgpu_cgs_gpu_mem_info,
1273 .gmap_kmem = amdgpu_cgs_gmap_kmem,
1274 .gunmap_kmem = amdgpu_cgs_gunmap_kmem,
1275 .alloc_gpu_mem = amdgpu_cgs_alloc_gpu_mem, 1090 .alloc_gpu_mem = amdgpu_cgs_alloc_gpu_mem,
1276 .free_gpu_mem = amdgpu_cgs_free_gpu_mem, 1091 .free_gpu_mem = amdgpu_cgs_free_gpu_mem,
1277 .gmap_gpu_mem = amdgpu_cgs_gmap_gpu_mem, 1092 .gmap_gpu_mem = amdgpu_cgs_gmap_gpu_mem,
@@ -1282,23 +1097,10 @@ static const struct cgs_ops amdgpu_cgs_ops = {
1282 .write_register = amdgpu_cgs_write_register, 1097 .write_register = amdgpu_cgs_write_register,
1283 .read_ind_register = amdgpu_cgs_read_ind_register, 1098 .read_ind_register = amdgpu_cgs_read_ind_register,
1284 .write_ind_register = amdgpu_cgs_write_ind_register, 1099 .write_ind_register = amdgpu_cgs_write_ind_register,
1285 .read_pci_config_byte = amdgpu_cgs_read_pci_config_byte,
1286 .read_pci_config_word = amdgpu_cgs_read_pci_config_word,
1287 .read_pci_config_dword = amdgpu_cgs_read_pci_config_dword,
1288 .write_pci_config_byte = amdgpu_cgs_write_pci_config_byte,
1289 .write_pci_config_word = amdgpu_cgs_write_pci_config_word,
1290 .write_pci_config_dword = amdgpu_cgs_write_pci_config_dword,
1291 .get_pci_resource = amdgpu_cgs_get_pci_resource, 1100 .get_pci_resource = amdgpu_cgs_get_pci_resource,
1292 .atom_get_data_table = amdgpu_cgs_atom_get_data_table, 1101 .atom_get_data_table = amdgpu_cgs_atom_get_data_table,
1293 .atom_get_cmd_table_revs = amdgpu_cgs_atom_get_cmd_table_revs, 1102 .atom_get_cmd_table_revs = amdgpu_cgs_atom_get_cmd_table_revs,
1294 .atom_exec_cmd_table = amdgpu_cgs_atom_exec_cmd_table, 1103 .atom_exec_cmd_table = amdgpu_cgs_atom_exec_cmd_table,
1295 .create_pm_request = amdgpu_cgs_create_pm_request,
1296 .destroy_pm_request = amdgpu_cgs_destroy_pm_request,
1297 .set_pm_request = amdgpu_cgs_set_pm_request,
1298 .pm_request_clock = amdgpu_cgs_pm_request_clock,
1299 .pm_request_engine = amdgpu_cgs_pm_request_engine,
1300 .pm_query_clock_limits = amdgpu_cgs_pm_query_clock_limits,
1301 .set_camera_voltages = amdgpu_cgs_set_camera_voltages,
1302 .get_firmware_info = amdgpu_cgs_get_firmware_info, 1104 .get_firmware_info = amdgpu_cgs_get_firmware_info,
1303 .rel_firmware = amdgpu_cgs_rel_firmware, 1105 .rel_firmware = amdgpu_cgs_rel_firmware,
1304 .set_powergating_state = amdgpu_cgs_set_powergating_state, 1106 .set_powergating_state = amdgpu_cgs_set_powergating_state,