aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu
diff options
context:
space:
mode:
authorChristian König <christian.koenig@amd.com>2017-04-27 11:13:39 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-04-28 17:33:12 -0400
commit2c55b16bf0e1492ba662d884c81d324538cafce1 (patch)
tree30a13041e7b6258e3a06a1c3856f0894bba4d8a2 /drivers/gpu
parent00c4855ef874e41d6b9f9b19d1d1e04bc70f0b31 (diff)
drm/amdgpu: remove unused and mostly unimplemented CGS functions v2
Those functions are all unused and some not even implemented. v2: keep cgs_get_pci_resource, it is used by the ACP driver. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c198
-rw-r--r--drivers/gpu/drm/amd/include/cgs_common.h270
2 files changed, 0 insertions, 468 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 013f5f14dd75..c6dba1eaefbd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -42,82 +42,6 @@ struct amdgpu_cgs_device {
42 struct amdgpu_device *adev = \ 42 struct amdgpu_device *adev = \
43 ((struct amdgpu_cgs_device *)cgs_device)->adev 43 ((struct amdgpu_cgs_device *)cgs_device)->adev
44 44
45static int amdgpu_cgs_gpu_mem_info(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
46 uint64_t *mc_start, uint64_t *mc_size,
47 uint64_t *mem_size)
48{
49 CGS_FUNC_ADEV;
50 switch(type) {
51 case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
52 case CGS_GPU_MEM_TYPE__VISIBLE_FB:
53 *mc_start = 0;
54 *mc_size = adev->mc.visible_vram_size;
55 *mem_size = adev->mc.visible_vram_size - adev->vram_pin_size;
56 break;
57 case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
58 case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
59 *mc_start = adev->mc.visible_vram_size;
60 *mc_size = adev->mc.real_vram_size - adev->mc.visible_vram_size;
61 *mem_size = *mc_size;
62 break;
63 case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
64 case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
65 *mc_start = adev->mc.gtt_start;
66 *mc_size = adev->mc.gtt_size;
67 *mem_size = adev->mc.gtt_size - adev->gart_pin_size;
68 break;
69 default:
70 return -EINVAL;
71 }
72
73 return 0;
74}
75
76static int amdgpu_cgs_gmap_kmem(struct cgs_device *cgs_device, void *kmem,
77 uint64_t size,
78 uint64_t min_offset, uint64_t max_offset,
79 cgs_handle_t *kmem_handle, uint64_t *mcaddr)
80{
81 CGS_FUNC_ADEV;
82 int ret;
83 struct amdgpu_bo *bo;
84 struct page *kmem_page = vmalloc_to_page(kmem);
85 int npages = ALIGN(size, PAGE_SIZE) >> PAGE_SHIFT;
86
87 struct sg_table *sg = drm_prime_pages_to_sg(&kmem_page, npages);
88 ret = amdgpu_bo_create(adev, size, PAGE_SIZE, false,
89 AMDGPU_GEM_DOMAIN_GTT, 0, sg, NULL, &bo);
90 if (ret)
91 return ret;
92 ret = amdgpu_bo_reserve(bo, true);
93 if (unlikely(ret != 0))
94 return ret;
95
96 /* pin buffer into GTT */
97 ret = amdgpu_bo_pin_restricted(bo, AMDGPU_GEM_DOMAIN_GTT,
98 min_offset, max_offset, mcaddr);
99 amdgpu_bo_unreserve(bo);
100
101 *kmem_handle = (cgs_handle_t)bo;
102 return ret;
103}
104
105static int amdgpu_cgs_gunmap_kmem(struct cgs_device *cgs_device, cgs_handle_t kmem_handle)
106{
107 struct amdgpu_bo *obj = (struct amdgpu_bo *)kmem_handle;
108
109 if (obj) {
110 int r = amdgpu_bo_reserve(obj, true);
111 if (likely(r == 0)) {
112 amdgpu_bo_unpin(obj);
113 amdgpu_bo_unreserve(obj);
114 }
115 amdgpu_bo_unref(&obj);
116
117 }
118 return 0;
119}
120
121static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device, 45static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device,
122 enum cgs_gpu_mem_type type, 46 enum cgs_gpu_mem_type type,
123 uint64_t size, uint64_t align, 47 uint64_t size, uint64_t align,
@@ -349,62 +273,6 @@ static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
349 WARN(1, "Invalid indirect register space"); 273 WARN(1, "Invalid indirect register space");
350} 274}
351 275
352static uint8_t amdgpu_cgs_read_pci_config_byte(struct cgs_device *cgs_device, unsigned addr)
353{
354 CGS_FUNC_ADEV;
355 uint8_t val;
356 int ret = pci_read_config_byte(adev->pdev, addr, &val);
357 if (WARN(ret, "pci_read_config_byte error"))
358 return 0;
359 return val;
360}
361
362static uint16_t amdgpu_cgs_read_pci_config_word(struct cgs_device *cgs_device, unsigned addr)
363{
364 CGS_FUNC_ADEV;
365 uint16_t val;
366 int ret = pci_read_config_word(adev->pdev, addr, &val);
367 if (WARN(ret, "pci_read_config_word error"))
368 return 0;
369 return val;
370}
371
372static uint32_t amdgpu_cgs_read_pci_config_dword(struct cgs_device *cgs_device,
373 unsigned addr)
374{
375 CGS_FUNC_ADEV;
376 uint32_t val;
377 int ret = pci_read_config_dword(adev->pdev, addr, &val);
378 if (WARN(ret, "pci_read_config_dword error"))
379 return 0;
380 return val;
381}
382
383static void amdgpu_cgs_write_pci_config_byte(struct cgs_device *cgs_device, unsigned addr,
384 uint8_t value)
385{
386 CGS_FUNC_ADEV;
387 int ret = pci_write_config_byte(adev->pdev, addr, value);
388 WARN(ret, "pci_write_config_byte error");
389}
390
391static void amdgpu_cgs_write_pci_config_word(struct cgs_device *cgs_device, unsigned addr,
392 uint16_t value)
393{
394 CGS_FUNC_ADEV;
395 int ret = pci_write_config_word(adev->pdev, addr, value);
396 WARN(ret, "pci_write_config_word error");
397}
398
399static void amdgpu_cgs_write_pci_config_dword(struct cgs_device *cgs_device, unsigned addr,
400 uint32_t value)
401{
402 CGS_FUNC_ADEV;
403 int ret = pci_write_config_dword(adev->pdev, addr, value);
404 WARN(ret, "pci_write_config_dword error");
405}
406
407
408static int amdgpu_cgs_get_pci_resource(struct cgs_device *cgs_device, 276static int amdgpu_cgs_get_pci_resource(struct cgs_device *cgs_device,
409 enum cgs_resource_type resource_type, 277 enum cgs_resource_type resource_type,
410 uint64_t size, 278 uint64_t size,
@@ -477,56 +345,6 @@ static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigne
477 adev->mode_info.atom_context, table, args); 345 adev->mode_info.atom_context, table, args);
478} 346}
479 347
480static int amdgpu_cgs_create_pm_request(struct cgs_device *cgs_device, cgs_handle_t *request)
481{
482 /* TODO */
483 return 0;
484}
485
486static int amdgpu_cgs_destroy_pm_request(struct cgs_device *cgs_device, cgs_handle_t request)
487{
488 /* TODO */
489 return 0;
490}
491
492static int amdgpu_cgs_set_pm_request(struct cgs_device *cgs_device, cgs_handle_t request,
493 int active)
494{
495 /* TODO */
496 return 0;
497}
498
499static int amdgpu_cgs_pm_request_clock(struct cgs_device *cgs_device, cgs_handle_t request,
500 enum cgs_clock clock, unsigned freq)
501{
502 /* TODO */
503 return 0;
504}
505
506static int amdgpu_cgs_pm_request_engine(struct cgs_device *cgs_device, cgs_handle_t request,
507 enum cgs_engine engine, int powered)
508{
509 /* TODO */
510 return 0;
511}
512
513
514
515static int amdgpu_cgs_pm_query_clock_limits(struct cgs_device *cgs_device,
516 enum cgs_clock clock,
517 struct cgs_clock_limits *limits)
518{
519 /* TODO */
520 return 0;
521}
522
523static int amdgpu_cgs_set_camera_voltages(struct cgs_device *cgs_device, uint32_t mask,
524 const uint32_t *voltages)
525{
526 DRM_ERROR("not implemented");
527 return -EPERM;
528}
529
530struct cgs_irq_params { 348struct cgs_irq_params {
531 unsigned src_id; 349 unsigned src_id;
532 cgs_irq_source_set_func_t set; 350 cgs_irq_source_set_func_t set;
@@ -1269,9 +1087,6 @@ static int amdgpu_cgs_call_acpi_method(struct cgs_device *cgs_device,
1269} 1087}
1270 1088
1271static const struct cgs_ops amdgpu_cgs_ops = { 1089static const struct cgs_ops amdgpu_cgs_ops = {
1272 .gpu_mem_info = amdgpu_cgs_gpu_mem_info,
1273 .gmap_kmem = amdgpu_cgs_gmap_kmem,
1274 .gunmap_kmem = amdgpu_cgs_gunmap_kmem,
1275 .alloc_gpu_mem = amdgpu_cgs_alloc_gpu_mem, 1090 .alloc_gpu_mem = amdgpu_cgs_alloc_gpu_mem,
1276 .free_gpu_mem = amdgpu_cgs_free_gpu_mem, 1091 .free_gpu_mem = amdgpu_cgs_free_gpu_mem,
1277 .gmap_gpu_mem = amdgpu_cgs_gmap_gpu_mem, 1092 .gmap_gpu_mem = amdgpu_cgs_gmap_gpu_mem,
@@ -1282,23 +1097,10 @@ static const struct cgs_ops amdgpu_cgs_ops = {
1282 .write_register = amdgpu_cgs_write_register, 1097 .write_register = amdgpu_cgs_write_register,
1283 .read_ind_register = amdgpu_cgs_read_ind_register, 1098 .read_ind_register = amdgpu_cgs_read_ind_register,
1284 .write_ind_register = amdgpu_cgs_write_ind_register, 1099 .write_ind_register = amdgpu_cgs_write_ind_register,
1285 .read_pci_config_byte = amdgpu_cgs_read_pci_config_byte,
1286 .read_pci_config_word = amdgpu_cgs_read_pci_config_word,
1287 .read_pci_config_dword = amdgpu_cgs_read_pci_config_dword,
1288 .write_pci_config_byte = amdgpu_cgs_write_pci_config_byte,
1289 .write_pci_config_word = amdgpu_cgs_write_pci_config_word,
1290 .write_pci_config_dword = amdgpu_cgs_write_pci_config_dword,
1291 .get_pci_resource = amdgpu_cgs_get_pci_resource, 1100 .get_pci_resource = amdgpu_cgs_get_pci_resource,
1292 .atom_get_data_table = amdgpu_cgs_atom_get_data_table, 1101 .atom_get_data_table = amdgpu_cgs_atom_get_data_table,
1293 .atom_get_cmd_table_revs = amdgpu_cgs_atom_get_cmd_table_revs, 1102 .atom_get_cmd_table_revs = amdgpu_cgs_atom_get_cmd_table_revs,
1294 .atom_exec_cmd_table = amdgpu_cgs_atom_exec_cmd_table, 1103 .atom_exec_cmd_table = amdgpu_cgs_atom_exec_cmd_table,
1295 .create_pm_request = amdgpu_cgs_create_pm_request,
1296 .destroy_pm_request = amdgpu_cgs_destroy_pm_request,
1297 .set_pm_request = amdgpu_cgs_set_pm_request,
1298 .pm_request_clock = amdgpu_cgs_pm_request_clock,
1299 .pm_request_engine = amdgpu_cgs_pm_request_engine,
1300 .pm_query_clock_limits = amdgpu_cgs_pm_query_clock_limits,
1301 .set_camera_voltages = amdgpu_cgs_set_camera_voltages,
1302 .get_firmware_info = amdgpu_cgs_get_firmware_info, 1104 .get_firmware_info = amdgpu_cgs_get_firmware_info,
1303 .rel_firmware = amdgpu_cgs_rel_firmware, 1105 .rel_firmware = amdgpu_cgs_rel_firmware,
1304 .set_powergating_state = amdgpu_cgs_set_powergating_state, 1106 .set_powergating_state = amdgpu_cgs_set_powergating_state,
diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
index 17b9d41f3e87..0a94f749e3c0 100644
--- a/drivers/gpu/drm/amd/include/cgs_common.h
+++ b/drivers/gpu/drm/amd/include/cgs_common.h
@@ -54,20 +54,6 @@ enum cgs_ind_reg {
54}; 54};
55 55
56/** 56/**
57 * enum cgs_clock - Clocks controlled by the SMU
58 */
59enum cgs_clock {
60 CGS_CLOCK__SCLK,
61 CGS_CLOCK__MCLK,
62 CGS_CLOCK__VCLK,
63 CGS_CLOCK__DCLK,
64 CGS_CLOCK__ECLK,
65 CGS_CLOCK__ACLK,
66 CGS_CLOCK__ICLK,
67 /* ... */
68};
69
70/**
71 * enum cgs_engine - Engines that can be statically power-gated 57 * enum cgs_engine - Engines that can be statically power-gated
72 */ 58 */
73enum cgs_engine { 59enum cgs_engine {
@@ -81,15 +67,6 @@ enum cgs_engine {
81 /* ... */ 67 /* ... */
82}; 68};
83 69
84/**
85 * enum cgs_voltage_planes - Voltage planes for external camera HW
86 */
87enum cgs_voltage_planes {
88 CGS_VOLTAGE_PLANE__SENSOR0,
89 CGS_VOLTAGE_PLANE__SENSOR1,
90 /* ... */
91};
92
93/* 70/*
94 * enum cgs_ucode_id - Firmware types for different IPs 71 * enum cgs_ucode_id - Firmware types for different IPs
95 */ 72 */
@@ -147,17 +124,6 @@ enum cgs_resource_type {
147}; 124};
148 125
149/** 126/**
150 * struct cgs_clock_limits - Clock limits
151 *
152 * Clocks are specified in 10KHz units.
153 */
154struct cgs_clock_limits {
155 unsigned min; /**< Minimum supported frequency */
156 unsigned max; /**< Maxumim supported frequency */
157 unsigned sustainable; /**< Thermally sustainable frequency */
158};
159
160/**
161 * struct cgs_firmware_info - Firmware information 127 * struct cgs_firmware_info - Firmware information
162 */ 128 */
163struct cgs_firmware_info { 129struct cgs_firmware_info {
@@ -221,54 +187,6 @@ struct cgs_acpi_method_info {
221}; 187};
222 188
223/** 189/**
224 * cgs_gpu_mem_info() - Return information about memory heaps
225 * @cgs_device: opaque device handle
226 * @type: memory type
227 * @mc_start: Start MC address of the heap (output)
228 * @mc_size: MC address space size (output)
229 * @mem_size: maximum amount of memory available for allocation (output)
230 *
231 * This function returns information about memory heaps. The type
232 * parameter is used to select the memory heap. The mc_start and
233 * mc_size for GART heaps may be bigger than the memory available for
234 * allocation.
235 *
236 * mc_start and mc_size are undefined for non-contiguous FB memory
237 * types, since buffers allocated with these types may or may not be
238 * GART mapped.
239 *
240 * Return: 0 on success, -errno otherwise
241 */
242typedef int (*cgs_gpu_mem_info_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
243 uint64_t *mc_start, uint64_t *mc_size,
244 uint64_t *mem_size);
245
246/**
247 * cgs_gmap_kmem() - map kernel memory to GART aperture
248 * @cgs_device: opaque device handle
249 * @kmem: pointer to kernel memory
250 * @size: size to map
251 * @min_offset: minimum offset from start of GART aperture
252 * @max_offset: maximum offset from start of GART aperture
253 * @kmem_handle: kernel memory handle (output)
254 * @mcaddr: MC address (output)
255 *
256 * Return: 0 on success, -errno otherwise
257 */
258typedef int (*cgs_gmap_kmem_t)(struct cgs_device *cgs_device, void *kmem, uint64_t size,
259 uint64_t min_offset, uint64_t max_offset,
260 cgs_handle_t *kmem_handle, uint64_t *mcaddr);
261
262/**
263 * cgs_gunmap_kmem() - unmap kernel memory
264 * @cgs_device: opaque device handle
265 * @kmem_handle: kernel memory handle returned by gmap_kmem
266 *
267 * Return: 0 on success, -errno otherwise
268 */
269typedef int (*cgs_gunmap_kmem_t)(struct cgs_device *cgs_device, cgs_handle_t kmem_handle);
270
271/**
272 * cgs_alloc_gpu_mem() - Allocate GPU memory 190 * cgs_alloc_gpu_mem() - Allocate GPU memory
273 * @cgs_device: opaque device handle 191 * @cgs_device: opaque device handle
274 * @type: memory type 192 * @type: memory type
@@ -392,62 +310,6 @@ typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs
392 unsigned index, uint32_t value); 310 unsigned index, uint32_t value);
393 311
394/** 312/**
395 * cgs_read_pci_config_byte() - Read byte from PCI configuration space
396 * @cgs_device: opaque device handle
397 * @addr: address
398 *
399 * Return: Value read
400 */
401typedef uint8_t (*cgs_read_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr);
402
403/**
404 * cgs_read_pci_config_word() - Read word from PCI configuration space
405 * @cgs_device: opaque device handle
406 * @addr: address, must be word-aligned
407 *
408 * Return: Value read
409 */
410typedef uint16_t (*cgs_read_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr);
411
412/**
413 * cgs_read_pci_config_dword() - Read dword from PCI configuration space
414 * @cgs_device: opaque device handle
415 * @addr: address, must be dword-aligned
416 *
417 * Return: Value read
418 */
419typedef uint32_t (*cgs_read_pci_config_dword_t)(struct cgs_device *cgs_device,
420 unsigned addr);
421
422/**
423 * cgs_write_pci_config_byte() - Write byte to PCI configuration space
424 * @cgs_device: opaque device handle
425 * @addr: address
426 * @value: value to write
427 */
428typedef void (*cgs_write_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr,
429 uint8_t value);
430
431/**
432 * cgs_write_pci_config_word() - Write byte to PCI configuration space
433 * @cgs_device: opaque device handle
434 * @addr: address, must be word-aligned
435 * @value: value to write
436 */
437typedef void (*cgs_write_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr,
438 uint16_t value);
439
440/**
441 * cgs_write_pci_config_dword() - Write byte to PCI configuration space
442 * @cgs_device: opaque device handle
443 * @addr: address, must be dword-aligned
444 * @value: value to write
445 */
446typedef void (*cgs_write_pci_config_dword_t)(struct cgs_device *cgs_device, unsigned addr,
447 uint32_t value);
448
449
450/**
451 * cgs_get_pci_resource() - provide access to a device resource (PCI BAR) 313 * cgs_get_pci_resource() - provide access to a device resource (PCI BAR)
452 * @cgs_device: opaque device handle 314 * @cgs_device: opaque device handle
453 * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL) 315 * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL)
@@ -501,87 +363,6 @@ typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device,
501 unsigned table, void *args); 363 unsigned table, void *args);
502 364
503/** 365/**
504 * cgs_create_pm_request() - Create a power management request
505 * @cgs_device: opaque device handle
506 * @request: handle of created PM request (output)
507 *
508 * Return: 0 on success, -errno otherwise
509 */
510typedef int (*cgs_create_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t *request);
511
512/**
513 * cgs_destroy_pm_request() - Destroy a power management request
514 * @cgs_device: opaque device handle
515 * @request: handle of created PM request
516 *
517 * Return: 0 on success, -errno otherwise
518 */
519typedef int (*cgs_destroy_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request);
520
521/**
522 * cgs_set_pm_request() - Activate or deactiveate a PM request
523 * @cgs_device: opaque device handle
524 * @request: PM request handle
525 * @active: 0 = deactivate, non-0 = activate
526 *
527 * While a PM request is active, its minimum clock requests are taken
528 * into account as the requested engines are powered up. When the
529 * request is inactive, the engines may be powered down and clocks may
530 * be lower, depending on other PM requests by other driver
531 * components.
532 *
533 * Return: 0 on success, -errno otherwise
534 */
535typedef int (*cgs_set_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request,
536 int active);
537
538/**
539 * cgs_pm_request_clock() - Request a minimum frequency for a specific clock
540 * @cgs_device: opaque device handle
541 * @request: PM request handle
542 * @clock: which clock?
543 * @freq: requested min. frequency in 10KHz units (0 to clear request)
544 *
545 * Return: 0 on success, -errno otherwise
546 */
547typedef int (*cgs_pm_request_clock_t)(struct cgs_device *cgs_device, cgs_handle_t request,
548 enum cgs_clock clock, unsigned freq);
549
550/**
551 * cgs_pm_request_engine() - Request an engine to be powered up
552 * @cgs_device: opaque device handle
553 * @request: PM request handle
554 * @engine: which engine?
555 * @powered: 0 = powered down, non-0 = powered up
556 *
557 * Return: 0 on success, -errno otherwise
558 */
559typedef int (*cgs_pm_request_engine_t)(struct cgs_device *cgs_device, cgs_handle_t request,
560 enum cgs_engine engine, int powered);
561
562/**
563 * cgs_pm_query_clock_limits() - Query clock frequency limits
564 * @cgs_device: opaque device handle
565 * @clock: which clock?
566 * @limits: clock limits
567 *
568 * Return: 0 on success, -errno otherwise
569 */
570typedef int (*cgs_pm_query_clock_limits_t)(struct cgs_device *cgs_device,
571 enum cgs_clock clock,
572 struct cgs_clock_limits *limits);
573
574/**
575 * cgs_set_camera_voltages() - Apply specific voltages to PMIC voltage planes
576 * @cgs_device: opaque device handle
577 * @mask: bitmask of voltages to change (1<<CGS_VOLTAGE_PLANE__xyz|...)
578 * @voltages: pointer to array of voltage values in 1mV units
579 *
580 * Return: 0 on success, -errno otherwise
581 */
582typedef int (*cgs_set_camera_voltages_t)(struct cgs_device *cgs_device, uint32_t mask,
583 const uint32_t *voltages);
584/**
585 * cgs_get_firmware_info - Get the firmware information from core driver 366 * cgs_get_firmware_info - Get the firmware information from core driver
586 * @cgs_device: opaque device handle 367 * @cgs_device: opaque device handle
587 * @type: the firmware type 368 * @type: the firmware type
@@ -627,9 +408,6 @@ typedef int (*cgs_enter_safe_mode)(struct cgs_device *cgs_device, bool en);
627 408
628struct cgs_ops { 409struct cgs_ops {
629 /* memory management calls (similar to KFD interface) */ 410 /* memory management calls (similar to KFD interface) */
630 cgs_gpu_mem_info_t gpu_mem_info;
631 cgs_gmap_kmem_t gmap_kmem;
632 cgs_gunmap_kmem_t gunmap_kmem;
633 cgs_alloc_gpu_mem_t alloc_gpu_mem; 411 cgs_alloc_gpu_mem_t alloc_gpu_mem;
634 cgs_free_gpu_mem_t free_gpu_mem; 412 cgs_free_gpu_mem_t free_gpu_mem;
635 cgs_gmap_gpu_mem_t gmap_gpu_mem; 413 cgs_gmap_gpu_mem_t gmap_gpu_mem;
@@ -641,27 +419,12 @@ struct cgs_ops {
641 cgs_write_register_t write_register; 419 cgs_write_register_t write_register;
642 cgs_read_ind_register_t read_ind_register; 420 cgs_read_ind_register_t read_ind_register;
643 cgs_write_ind_register_t write_ind_register; 421 cgs_write_ind_register_t write_ind_register;
644 /* PCI configuration space access */
645 cgs_read_pci_config_byte_t read_pci_config_byte;
646 cgs_read_pci_config_word_t read_pci_config_word;
647 cgs_read_pci_config_dword_t read_pci_config_dword;
648 cgs_write_pci_config_byte_t write_pci_config_byte;
649 cgs_write_pci_config_word_t write_pci_config_word;
650 cgs_write_pci_config_dword_t write_pci_config_dword;
651 /* PCI resources */ 422 /* PCI resources */
652 cgs_get_pci_resource_t get_pci_resource; 423 cgs_get_pci_resource_t get_pci_resource;
653 /* ATOM BIOS */ 424 /* ATOM BIOS */
654 cgs_atom_get_data_table_t atom_get_data_table; 425 cgs_atom_get_data_table_t atom_get_data_table;
655 cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs; 426 cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs;
656 cgs_atom_exec_cmd_table_t atom_exec_cmd_table; 427 cgs_atom_exec_cmd_table_t atom_exec_cmd_table;
657 /* Power management */
658 cgs_create_pm_request_t create_pm_request;
659 cgs_destroy_pm_request_t destroy_pm_request;
660 cgs_set_pm_request_t set_pm_request;
661 cgs_pm_request_clock_t pm_request_clock;
662 cgs_pm_request_engine_t pm_request_engine;
663 cgs_pm_query_clock_limits_t pm_query_clock_limits;
664 cgs_set_camera_voltages_t set_camera_voltages;
665 /* Firmware Info */ 428 /* Firmware Info */
666 cgs_get_firmware_info get_firmware_info; 429 cgs_get_firmware_info get_firmware_info;
667 cgs_rel_firmware rel_firmware; 430 cgs_rel_firmware rel_firmware;
@@ -696,12 +459,6 @@ struct cgs_device
696#define CGS_OS_CALL(func,dev,...) \ 459#define CGS_OS_CALL(func,dev,...) \
697 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__)) 460 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
698 461
699#define cgs_gpu_mem_info(dev,type,mc_start,mc_size,mem_size) \
700 CGS_CALL(gpu_mem_info,dev,type,mc_start,mc_size,mem_size)
701#define cgs_gmap_kmem(dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) \
702 CGS_CALL(gmap_kmem,dev,kmem,size,min_off,max_off,kmem_handle,mcaddr)
703#define cgs_gunmap_kmem(dev,kmem_handle) \
704 CGS_CALL(gunmap_kmem,dev,keme_handle)
705#define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) \ 462#define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) \
706 CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle) 463 CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle)
707#define cgs_free_gpu_mem(dev,handle) \ 464#define cgs_free_gpu_mem(dev,handle) \
@@ -724,19 +481,6 @@ struct cgs_device
724#define cgs_write_ind_register(dev,space,index,value) \ 481#define cgs_write_ind_register(dev,space,index,value) \
725 CGS_CALL(write_ind_register,dev,space,index,value) 482 CGS_CALL(write_ind_register,dev,space,index,value)
726 483
727#define cgs_read_pci_config_byte(dev,addr) \
728 CGS_CALL(read_pci_config_byte,dev,addr)
729#define cgs_read_pci_config_word(dev,addr) \
730 CGS_CALL(read_pci_config_word,dev,addr)
731#define cgs_read_pci_config_dword(dev,addr) \
732 CGS_CALL(read_pci_config_dword,dev,addr)
733#define cgs_write_pci_config_byte(dev,addr,value) \
734 CGS_CALL(write_pci_config_byte,dev,addr,value)
735#define cgs_write_pci_config_word(dev,addr,value) \
736 CGS_CALL(write_pci_config_word,dev,addr,value)
737#define cgs_write_pci_config_dword(dev,addr,value) \
738 CGS_CALL(write_pci_config_dword,dev,addr,value)
739
740#define cgs_atom_get_data_table(dev,table,size,frev,crev) \ 484#define cgs_atom_get_data_table(dev,table,size,frev,crev) \
741 CGS_CALL(atom_get_data_table,dev,table,size,frev,crev) 485 CGS_CALL(atom_get_data_table,dev,table,size,frev,crev)
742#define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \ 486#define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \
@@ -744,20 +488,6 @@ struct cgs_device
744#define cgs_atom_exec_cmd_table(dev,table,args) \ 488#define cgs_atom_exec_cmd_table(dev,table,args) \
745 CGS_CALL(atom_exec_cmd_table,dev,table,args) 489 CGS_CALL(atom_exec_cmd_table,dev,table,args)
746 490
747#define cgs_create_pm_request(dev,request) \
748 CGS_CALL(create_pm_request,dev,request)
749#define cgs_destroy_pm_request(dev,request) \
750 CGS_CALL(destroy_pm_request,dev,request)
751#define cgs_set_pm_request(dev,request,active) \
752 CGS_CALL(set_pm_request,dev,request,active)
753#define cgs_pm_request_clock(dev,request,clock,freq) \
754 CGS_CALL(pm_request_clock,dev,request,clock,freq)
755#define cgs_pm_request_engine(dev,request,engine,powered) \
756 CGS_CALL(pm_request_engine,dev,request,engine,powered)
757#define cgs_pm_query_clock_limits(dev,clock,limits) \
758 CGS_CALL(pm_query_clock_limits,dev,clock,limits)
759#define cgs_set_camera_voltages(dev,mask,voltages) \
760 CGS_CALL(set_camera_voltages,dev,mask,voltages)
761#define cgs_get_firmware_info(dev, type, info) \ 491#define cgs_get_firmware_info(dev, type, info) \
762 CGS_CALL(get_firmware_info, dev, type, info) 492 CGS_CALL(get_firmware_info, dev, type, info)
763#define cgs_rel_firmware(dev, type) \ 493#define cgs_rel_firmware(dev, type) \
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-29 03:17:09 -0400