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authorThierry Reding <treding@nvidia.com>2015-11-18 08:04:20 -0500
committerThierry Reding <treding@nvidia.com>2015-11-18 09:54:11 -0500
commite52d7c04bb3911d4ce98bd237f69f5246d9c7083 (patch)
treefc1af5cb677bf3350fdd74e420082bdeb84a6040 /drivers/clk/tegra/clk-tegra114.c
parentc4947e364b5096f00f3cfc0a7af2a4f688ffb919 (diff)
clk: tegra: Miscellaneous coding style cleanups
Use unsigned int for loop variables that can never become negative and remove a couple of gratuitous blank lines. Also use single spaces around operators and use a single space instead of a tab to separate comments from code. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra114.c')
-rw-r--r--drivers/clk/tegra/clk-tegra114.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 9a50471009d8..8668ecd0046c 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -215,7 +215,7 @@ static struct tegra_clk_pll_params pll_c_params = {
215 .input_min = 12000000, 215 .input_min = 12000000,
216 .input_max = 800000000, 216 .input_max = 800000000,
217 .cf_min = 12000000, 217 .cf_min = 12000000,
218 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 218 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
219 .vco_min = 600000000, 219 .vco_min = 600000000,
220 .vco_max = 1400000000, 220 .vco_max = 1400000000,
221 .base_reg = PLLC_BASE, 221 .base_reg = PLLC_BASE,
@@ -337,7 +337,7 @@ static struct tegra_clk_pll_params pll_m_params = {
337 .input_min = 12000000, 337 .input_min = 12000000,
338 .input_max = 500000000, 338 .input_max = 500000000,
339 .cf_min = 12000000, 339 .cf_min = 12000000,
340 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 340 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
341 .vco_min = 400000000, 341 .vco_min = 400000000,
342 .vco_max = 1066000000, 342 .vco_max = 1066000000,
343 .base_reg = PLLM_BASE, 343 .base_reg = PLLM_BASE,
@@ -534,7 +534,7 @@ static struct tegra_clk_pll_params pll_x_params = {
534 .input_min = 12000000, 534 .input_min = 12000000,
535 .input_max = 800000000, 535 .input_max = 800000000,
536 .cf_min = 12000000, 536 .cf_min = 12000000,
537 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 537 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
538 .vco_min = 700000000, 538 .vco_min = 700000000,
539 .vco_max = 2400000000U, 539 .vco_max = 2400000000U,
540 .base_reg = PLLX_BASE, 540 .base_reg = PLLX_BASE,
@@ -965,8 +965,8 @@ static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
965 965
966static __init void tegra114_utmi_param_configure(void __iomem *clk_base) 966static __init void tegra114_utmi_param_configure(void __iomem *clk_base)
967{ 967{
968 unsigned int i;
968 u32 reg; 969 u32 reg;
969 int i;
970 970
971 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 971 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
972 if (osc_freq == utmi_parameters[i].osc_frequency) 972 if (osc_freq == utmi_parameters[i].osc_frequency)
@@ -1173,7 +1173,7 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1173{ 1173{
1174 struct clk *clk; 1174 struct clk *clk;
1175 struct tegra_periph_init_data *data; 1175 struct tegra_periph_init_data *data;
1176 int i; 1176 unsigned int i;
1177 1177
1178 /* xusb_ss_div2 */ 1178 /* xusb_ss_div2 */
1179 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, 1179 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
@@ -1278,7 +1278,7 @@ static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
1278 1278
1279static const struct of_device_id pmc_match[] __initconst = { 1279static const struct of_device_id pmc_match[] __initconst = {
1280 { .compatible = "nvidia,tegra114-pmc" }, 1280 { .compatible = "nvidia,tegra114-pmc" },
1281 {}, 1281 { },
1282}; 1282};
1283 1283
1284/* 1284/*