clk: tegra: Miscellaneous coding style cleanups

Use unsigned int for loop variables that can never become negative and
remove a couple of gratuitous blank lines. Also use single spaces around
operators and use a single space instead of a tab to separate comments
from code.

Signed-off-by: Thierry Reding <treding@nvidia.com>

5 files changed, 19 insertions, 25 deletions

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index d6d4ecb88e94..c72340830521 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -439,7 +439,7 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
                 /*
                  * PLL_P_OUT1 rate is not listed in PLLA table
                  */
-                cfreq = parent_rate/(parent_rate/1000000);
+                cfreq = parent_rate / (parent_rate / 1000000);
                 break;
         default:
                 pr_err("%s Unexpected reference rate %lu\n",
@@ -936,8 +936,8 @@ static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
         p_div = _p_div_to_hw(hw, p);
         if (p_div < 0)
                 return p_div;
-        else
-                cfg->p = p_div;
+
+        cfg->p = p_div;
 
         if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
                 return -EINVAL;
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 9a50471009d8..8668ecd0046c 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -215,7 +215,7 @@ static struct tegra_clk_pll_params pll_c_params = {
         .input_min = 12000000,
         .input_max = 800000000,
         .cf_min = 12000000,
-        .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
+        .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
         .vco_min = 600000000,
         .vco_max = 1400000000,
         .base_reg = PLLC_BASE,
@@ -337,7 +337,7 @@ static struct tegra_clk_pll_params pll_m_params = {
         .input_min = 12000000,
         .input_max = 500000000,
         .cf_min = 12000000,
-        .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
+        .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
         .vco_min = 400000000,
         .vco_max = 1066000000,
         .base_reg = PLLM_BASE,
@@ -534,7 +534,7 @@ static struct tegra_clk_pll_params pll_x_params = {
         .input_min = 12000000,
         .input_max = 800000000,
         .cf_min = 12000000,
-        .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
+        .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
         .vco_min = 700000000,
         .vco_max = 2400000000U,
         .base_reg = PLLX_BASE,
@@ -965,8 +965,8 @@ static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
 
 static __init void tegra114_utmi_param_configure(void __iomem *clk_base)
 {
+        unsigned int i;
         u32 reg;
-        int i;
 
         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
                 if (osc_freq == utmi_parameters[i].osc_frequency)
@@ -1173,7 +1173,7 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
 {
         struct clk *clk;
         struct tegra_periph_init_data *data;
-        int i;
+        unsigned int i;
 
         /* xusb_ss_div2 */
         clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
@@ -1278,7 +1278,7 @@ static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
 
 static const struct of_device_id pmc_match[] __initconst = {
         { .compatible = "nvidia,tegra114-pmc" },
-        {},
+        { },
 };
 
 /*
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 9b78e1c77f77..b58f58576e77 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -235,7 +235,7 @@ static struct tegra_clk_pll_params pll_c_params = {
         .input_min = 12000000,
         .input_max = 800000000,
         .cf_min = 12000000,
-        .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
+        .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
         .vco_min = 600000000,
         .vco_max = 1400000000,
         .base_reg = PLLC_BASE,
@@ -1024,8 +1024,8 @@ static struct clk **clks;
 
 static void tegra124_utmi_param_configure(void __iomem *clk_base)
 {
+        unsigned int i;
         u32 reg;
-        int i;
 
         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
                 if (osc_freq == utmi_parameters[i].osc_frequency)
@@ -1356,7 +1356,7 @@ static struct tegra_cpu_car_ops tegra124_cpu_car_ops = {
 
 static const struct of_device_id pmc_match[] __initconst = {
         { .compatible = "nvidia,tegra124-pmc" },
-        {},
+        { },
 };
 
 static struct tegra_clk_init_table common_init_table[] __initdata = {
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index bf004f0e4f65..319e80ef69e1 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -759,7 +759,6 @@ static void __init tegra20_audio_clk_init(void)
                                     CLK_SET_RATE_PARENT, 89,
                                     periph_clk_enb_refcnt);
         clks[TEGRA20_CLK_AUDIO_2X] = clk;
-
 }
 
 static const char *i2s1_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
@@ -802,7 +801,7 @@ static void __init tegra20_periph_clk_init(void)
 {
         struct tegra_periph_init_data *data;
         struct clk *clk;
-        int i;
+        unsigned int i;
 
         /* ac97 */
         clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
@@ -1085,7 +1084,7 @@ static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
 
 static const struct of_device_id pmc_match[] __initconst = {
         { .compatible = "nvidia,tegra20-pmc" },
-        {},
+        { },
 };
 
 static void __init tegra20_clock_init(struct device_node *np)
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index c1d065d61156..b670e315be4d 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -505,7 +505,6 @@ static struct tegra_clk_pll_params pll_d_params = {
         .freq_table = pll_d_freq_table,
         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
                  TEGRA_PLL_USE_LOCK,
-
 };
 
 static struct tegra_clk_pll_params pll_d2_params = {
@@ -861,13 +860,12 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
         [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true },
         [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
         [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
-
 };
 
 static void tegra30_utmi_param_configure(void)
 {
+        unsigned int i;
         u32 reg;
-        int i;
 
         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
                 if (input_freq == utmi_parameters[i].osc_frequency)
@@ -925,7 +923,7 @@ static void __init tegra30_pll_init(void)
 
         /* PLLC */
         clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
-                                &pll_c_params, NULL);
+                                     &pll_c_params, NULL);
         clks[TEGRA30_CLK_PLL_C] = clk;
 
         /* PLLC_OUT1 */
@@ -1135,7 +1133,7 @@ static void __init tegra30_periph_clk_init(void)
 {
         struct tegra_periph_init_data *data;
         struct clk *clk;
-        int i;
+        unsigned int i;
 
         /* dsia */
         clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
@@ -1224,7 +1222,6 @@ static void tegra30_cpu_out_of_reset(u32 cpu)
         wmb();
 }
 
-
 static void tegra30_enable_cpu_clock(u32 cpu)
 {
         unsigned int reg;
@@ -1237,7 +1234,6 @@ static void tegra30_enable_cpu_clock(u32 cpu)
 
 static void tegra30_disable_cpu_clock(u32 cpu)
 {
-
         unsigned int reg;
 
         reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
@@ -1268,7 +1264,7 @@ static void tegra30_cpu_clock_suspend(void)
         /* switch coresite to clk_m, save off original source */
         tegra30_cpu_clk_sctx.clk_csite_src =
                                 readl(clk_base + CLK_RESET_SOURCE_CSITE);
-        writel(3<<30, clk_base + CLK_RESET_SOURCE_CSITE);
+        writel(3 << 30, clk_base + CLK_RESET_SOURCE_CSITE);
 
         tegra30_cpu_clk_sctx.cpu_burst =
                                 readl(clk_base + CLK_RESET_CCLK_BURST);
@@ -1402,7 +1398,7 @@ static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
 
 static const struct of_device_id pmc_match[] __initconst = {
         { .compatible = "nvidia,tegra30-pmc" },
-        {},
+        { },
 };
 
 static struct tegra_audio_clk_info tegra30_audio_plls[] = {
@@ -1441,7 +1437,6 @@ static void __init tegra30_clock_init(struct device_node *np)
                                NULL) < 0)
                 return;
 
-
         tegra_fixed_clk_init(tegra30_clks);
         tegra30_pll_init();
         tegra30_super_clk_init();