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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2016-06-20 11:25:44 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2016-06-20 11:25:44 -0400
commitaf52739b922f656eb1f39016fabaabe4baeda2e2 (patch)
tree79a7aa810d0493cd0cf4adebac26d37f12e8b545 /arch
parent25ed6a5e97809129a1bc852b6b5c7d03baa112c4 (diff)
parent33688abb2802ff3a230bd2441f765477b94cc89e (diff)
Merge 4.7-rc4 into staging-next
We want the fixes in here, and we can resolve a merge issue in drivers/iio/industrialio-trigger.c Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/Kconfig3
-rw-r--r--arch/arc/Kconfig31
-rw-r--r--arch/arc/Makefile2
-rw-r--r--arch/arc/boot/dts/abilis_tb100.dtsi2
-rw-r--r--arch/arc/boot/dts/abilis_tb101.dtsi2
-rw-r--r--arch/arc/boot/dts/axc001.dtsi1
-rw-r--r--arch/arc/boot/dts/axc003.dtsi1
-rw-r--r--arch/arc/boot/dts/axc003_idu.dtsi1
-rw-r--r--arch/arc/boot/dts/eznps.dts1
-rw-r--r--arch/arc/boot/dts/nsim_700.dts1
-rw-r--r--arch/arc/boot/dts/nsimosci.dts1
-rw-r--r--arch/arc/boot/dts/nsimosci_hs.dts1
-rw-r--r--arch/arc/boot/dts/nsimosci_hs_idu.dts1
-rw-r--r--arch/arc/boot/dts/skeleton.dtsi1
-rw-r--r--arch/arc/boot/dts/skeleton_hs.dtsi1
-rw-r--r--arch/arc/boot/dts/skeleton_hs_idu.dtsi1
-rw-r--r--arch/arc/boot/dts/vdk_axc003.dtsi1
-rw-r--r--arch/arc/boot/dts/vdk_axc003_idu.dtsi1
-rw-r--r--arch/arc/include/asm/atomic.h45
-rw-r--r--arch/arc/include/asm/entry-compact.h4
-rw-r--r--arch/arc/include/asm/mmu_context.h2
-rw-r--r--arch/arc/include/asm/pgtable.h2
-rw-r--r--arch/arc/include/asm/processor.h2
-rw-r--r--arch/arc/include/asm/smp.h2
-rw-r--r--arch/arc/include/asm/spinlock.h292
-rw-r--r--arch/arc/include/asm/thread_info.h2
-rw-r--r--arch/arc/include/asm/uaccess.h2
-rw-r--r--arch/arc/include/uapi/asm/swab.h2
-rw-r--r--arch/arc/kernel/entry-compact.S18
-rw-r--r--arch/arc/kernel/intc-compact.c6
-rw-r--r--arch/arc/kernel/perf_event.c2
-rw-r--r--arch/arc/kernel/setup.c2
-rw-r--r--arch/arc/kernel/signal.c2
-rw-r--r--arch/arc/kernel/troubleshoot.c2
-rw-r--r--arch/arc/mm/cache.c6
-rw-r--r--arch/arc/mm/dma.c2
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/am437x-sk-evm.dts2
-rw-r--r--arch/arm/boot/dts/am57xx-idk-common.dtsi32
-rw-r--r--arch/arm/boot/dts/dm8148-evm.dts8
-rw-r--r--arch/arm/boot/dts/dm8148-t410.dts9
-rw-r--r--arch/arm/boot/dts/dra7.dtsi2
-rw-r--r--arch/arm/boot/dts/dra74x.dtsi4
-rw-r--r--arch/arm/boot/dts/exynos5250-snow-common.dtsi13
-rw-r--r--arch/arm/boot/dts/exynos5420-peach-pit.dts13
-rw-r--r--arch/arm/boot/dts/omap3-evm-37xx.dts2
-rw-r--r--arch/arm/boot/dts/omap3-igep.dtsi1
-rw-r--r--arch/arm/boot/dts/omap3-igep0020-common.dtsi11
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts4
-rw-r--r--arch/arm/boot/dts/omap3-n950-n9.dtsi6
-rw-r--r--arch/arm/boot/dts/omap3-zoom3.dts6
-rw-r--r--arch/arm/boot/dts/omap5-board-common.dtsi48
-rw-r--r--arch/arm/boot/dts/omap5-igep0050.dts26
-rw-r--r--arch/arm/boot/dts/omap5-uevm.dts10
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts1
-rw-r--r--arch/arm/boot/dts/stih407-family.dtsi3
-rw-r--r--arch/arm/boot/dts/sun6i-a31s-primo81.dts2
-rw-r--r--arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts2
-rw-r--r--arch/arm/configs/exynos_defconfig1
-rw-r--r--arch/arm/configs/multi_v7_defconfig1
-rw-r--r--arch/arm/include/asm/pgtable-2level.h1
-rw-r--r--arch/arm/include/asm/pgtable-3level.h5
-rw-r--r--arch/arm/include/asm/pgtable.h1
-rw-r--r--arch/arm/kernel/smp.c2
-rw-r--r--arch/arm/mach-exynos/Kconfig1
-rw-r--r--arch/arm/mach-imx/mach-imx6ul.c2
-rw-r--r--arch/arm/mach-omap1/ams-delta-fiq-handler.S6
-rw-r--r--arch/arm/mach-omap1/ams-delta-fiq.c5
-rw-r--r--arch/arm/mach-omap1/include/mach/ams-delta-fiq.h2
-rw-r--r--arch/arm/mach-omap2/Kconfig12
-rw-r--r--arch/arm/mach-omap2/omap-secure.h1
-rw-r--r--arch/arm/mach-omap2/omap-smp.c48
-rw-r--r--arch/arm/mach-omap2/powerdomain.c9
-rw-r--r--arch/arm/mach-omap2/powerdomains7xx_data.c76
-rw-r--r--arch/arm/mach-omap2/timer.c7
-rw-r--r--arch/arm/mach-vexpress/spc.c2
-rw-r--r--arch/arm/plat-samsung/devs.c2
-rw-r--r--arch/arm64/boot/dts/lg/lg1312.dtsi2
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399.dtsi2
-rw-r--r--arch/arm64/include/asm/kgdb.h45
-rw-r--r--arch/arm64/include/asm/spinlock.h42
-rw-r--r--arch/arm64/kernel/kgdb.c14
-rw-r--r--arch/arm64/kernel/traps.c26
-rw-r--r--arch/arm64/mm/fault.c4
-rw-r--r--arch/mips/include/asm/kvm_host.h3
-rw-r--r--arch/mips/kvm/emulate.c19
-rw-r--r--arch/mips/kvm/interrupt.h1
-rw-r--r--arch/mips/kvm/locore.S1
-rw-r--r--arch/mips/kvm/mips.c11
-rw-r--r--arch/powerpc/include/asm/nohash/64/pgalloc.h2
-rw-r--r--arch/powerpc/kernel/prom_init.c2
-rw-r--r--arch/powerpc/kernel/ptrace.c4
-rw-r--r--arch/powerpc/mm/hash_native_64.c6
-rw-r--r--arch/powerpc/mm/tlb-radix.c8
-rw-r--r--arch/powerpc/platforms/512x/clock-commonclk.c2
-rw-r--r--arch/powerpc/platforms/cell/spufs/coredump.c2
-rw-r--r--arch/powerpc/platforms/pseries/iommu.c4
-rw-r--r--arch/s390/include/asm/kvm_host.h1
-rw-r--r--arch/s390/kvm/intercept.c2
-rw-r--r--arch/s390/kvm/kvm-s390.c3
-rw-r--r--arch/x86/Kconfig9
-rw-r--r--arch/x86/boot/Makefile3
-rw-r--r--arch/x86/events/intel/rapl.c2
-rw-r--r--arch/x86/events/intel/uncore_snbep.c21
-rw-r--r--arch/x86/include/asm/intel-family.h68
-rw-r--r--arch/x86/include/asm/kvm_host.h11
-rw-r--r--arch/x86/include/asm/msr.h4
-rw-r--r--arch/x86/kernel/apic/io_apic.c2
-rw-r--r--arch/x86/kernel/cpu/amd.c4
-rw-r--r--arch/x86/kernel/traps.c20
-rw-r--r--arch/x86/kvm/svm.c21
-rw-r--r--arch/x86/kvm/vmx.c15
112 files changed, 569 insertions, 655 deletions
diff --git a/arch/Kconfig b/arch/Kconfig
index d794384a0404..e9734796531f 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -606,6 +606,9 @@ config HAVE_ARCH_HASH
606 file which provides platform-specific implementations of some 606 file which provides platform-specific implementations of some
607 functions in <linux/hash.h> or fs/namei.c. 607 functions in <linux/hash.h> or fs/namei.c.
608 608
609config ISA_BUS_API
610 def_bool ISA
611
609# 612#
610# ABI hall of shame 613# ABI hall of shame
611# 614#
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 0dcbacfdea4b..0d3e59f56974 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -61,7 +61,7 @@ config RWSEM_GENERIC_SPINLOCK
61 def_bool y 61 def_bool y
62 62
63config ARCH_DISCONTIGMEM_ENABLE 63config ARCH_DISCONTIGMEM_ENABLE
64 def_bool y 64 def_bool n
65 65
66config ARCH_FLATMEM_ENABLE 66config ARCH_FLATMEM_ENABLE
67 def_bool y 67 def_bool y
@@ -186,9 +186,6 @@ if SMP
186config ARC_HAS_COH_CACHES 186config ARC_HAS_COH_CACHES
187 def_bool n 187 def_bool n
188 188
189config ARC_HAS_REENTRANT_IRQ_LV2
190 def_bool n
191
192config ARC_MCIP 189config ARC_MCIP
193 bool "ARConnect Multicore IP (MCIP) Support " 190 bool "ARConnect Multicore IP (MCIP) Support "
194 depends on ISA_ARCV2 191 depends on ISA_ARCV2
@@ -366,25 +363,10 @@ config NODES_SHIFT
366if ISA_ARCOMPACT 363if ISA_ARCOMPACT
367 364
368config ARC_COMPACT_IRQ_LEVELS 365config ARC_COMPACT_IRQ_LEVELS
369 bool "ARCompact IRQ Priorities: High(2)/Low(1)" 366 bool "Setup Timer IRQ as high Priority"
370 default n 367 default n
371 # Timer HAS to be high priority, for any other high priority config
372 select ARC_IRQ3_LV2
373 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 368 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
374 depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2 369 depends on !SMP
375
376if ARC_COMPACT_IRQ_LEVELS
377
378config ARC_IRQ3_LV2
379 bool
380
381config ARC_IRQ5_LV2
382 bool
383
384config ARC_IRQ6_LV2
385 bool
386
387endif #ARC_COMPACT_IRQ_LEVELS
388 370
389config ARC_FPU_SAVE_RESTORE 371config ARC_FPU_SAVE_RESTORE
390 bool "Enable FPU state persistence across context switch" 372 bool "Enable FPU state persistence across context switch"
@@ -407,11 +389,6 @@ config ARC_HAS_LLSC
407 default y 389 default y
408 depends on !ARC_CANT_LLSC 390 depends on !ARC_CANT_LLSC
409 391
410config ARC_STAR_9000923308
411 bool "Workaround for llock/scond livelock"
412 default n
413 depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC
414
415config ARC_HAS_SWAPE 392config ARC_HAS_SWAPE
416 bool "Insn: SWAPE (endian-swap)" 393 bool "Insn: SWAPE (endian-swap)"
417 default y 394 default y
@@ -471,7 +448,7 @@ config LINUX_LINK_BASE
471 448
472config HIGHMEM 449config HIGHMEM
473 bool "High Memory Support" 450 bool "High Memory Support"
474 select DISCONTIGMEM 451 select ARCH_DISCONTIGMEM_ENABLE
475 help 452 help
476 With ARC 2G:2G address split, only upper 2G is directly addressable by 453 With ARC 2G:2G address split, only upper 2G is directly addressable by
477 kernel. Enable this to potentially allow access to rest of 2G and PAE 454 kernel. Enable this to potentially allow access to rest of 2G and PAE
diff --git a/arch/arc/Makefile b/arch/arc/Makefile
index 02fabef2891c..d4df6be66d58 100644
--- a/arch/arc/Makefile
+++ b/arch/arc/Makefile
@@ -127,7 +127,7 @@ libs-y += arch/arc/lib/ $(LIBGCC)
127 127
128boot := arch/arc/boot 128boot := arch/arc/boot
129 129
130#default target for make without any arguements. 130#default target for make without any arguments.
131KBUILD_IMAGE := bootpImage 131KBUILD_IMAGE := bootpImage
132 132
133all: $(KBUILD_IMAGE) 133all: $(KBUILD_IMAGE)
diff --git a/arch/arc/boot/dts/abilis_tb100.dtsi b/arch/arc/boot/dts/abilis_tb100.dtsi
index 3942634f805a..02410b211433 100644
--- a/arch/arc/boot/dts/abilis_tb100.dtsi
+++ b/arch/arc/boot/dts/abilis_tb100.dtsi
@@ -23,8 +23,6 @@
23 23
24 24
25/ { 25/ {
26 clock-frequency = <500000000>; /* 500 MHZ */
27
28 soc100 { 26 soc100 {
29 bus-frequency = <166666666>; 27 bus-frequency = <166666666>;
30 28
diff --git a/arch/arc/boot/dts/abilis_tb101.dtsi b/arch/arc/boot/dts/abilis_tb101.dtsi
index b0467229a5c4..f9e7686044eb 100644
--- a/arch/arc/boot/dts/abilis_tb101.dtsi
+++ b/arch/arc/boot/dts/abilis_tb101.dtsi
@@ -23,8 +23,6 @@
23 23
24 24
25/ { 25/ {
26 clock-frequency = <500000000>; /* 500 MHZ */
27
28 soc100 { 26 soc100 {
29 bus-frequency = <166666666>; 27 bus-frequency = <166666666>;
30 28
diff --git a/arch/arc/boot/dts/axc001.dtsi b/arch/arc/boot/dts/axc001.dtsi
index 3e02f152edcb..6ae2c476ad82 100644
--- a/arch/arc/boot/dts/axc001.dtsi
+++ b/arch/arc/boot/dts/axc001.dtsi
@@ -15,7 +15,6 @@
15 15
16/ { 16/ {
17 compatible = "snps,arc"; 17 compatible = "snps,arc";
18 clock-frequency = <750000000>; /* 750 MHZ */
19 #address-cells = <1>; 18 #address-cells = <1>;
20 #size-cells = <1>; 19 #size-cells = <1>;
21 20
diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi
index 378e455a94c4..14df46f141bf 100644
--- a/arch/arc/boot/dts/axc003.dtsi
+++ b/arch/arc/boot/dts/axc003.dtsi
@@ -14,7 +14,6 @@
14 14
15/ { 15/ {
16 compatible = "snps,arc"; 16 compatible = "snps,arc";
17 clock-frequency = <90000000>;
18 #address-cells = <1>; 17 #address-cells = <1>;
19 #size-cells = <1>; 18 #size-cells = <1>;
20 19
diff --git a/arch/arc/boot/dts/axc003_idu.dtsi b/arch/arc/boot/dts/axc003_idu.dtsi
index 64c94b2860ab..3d6cfa32bf51 100644
--- a/arch/arc/boot/dts/axc003_idu.dtsi
+++ b/arch/arc/boot/dts/axc003_idu.dtsi
@@ -14,7 +14,6 @@
14 14
15/ { 15/ {
16 compatible = "snps,arc"; 16 compatible = "snps,arc";
17 clock-frequency = <90000000>;
18 #address-cells = <1>; 17 #address-cells = <1>;
19 #size-cells = <1>; 18 #size-cells = <1>;
20 19
diff --git a/arch/arc/boot/dts/eznps.dts b/arch/arc/boot/dts/eznps.dts
index b89f6c3eb352..1e0d225791c1 100644
--- a/arch/arc/boot/dts/eznps.dts
+++ b/arch/arc/boot/dts/eznps.dts
@@ -18,7 +18,6 @@
18 18
19/ { 19/ {
20 compatible = "ezchip,arc-nps"; 20 compatible = "ezchip,arc-nps";
21 clock-frequency = <83333333>; /* 83.333333 MHZ */
22 #address-cells = <1>; 21 #address-cells = <1>;
23 #size-cells = <1>; 22 #size-cells = <1>;
24 interrupt-parent = <&intc>; 23 interrupt-parent = <&intc>;
diff --git a/arch/arc/boot/dts/nsim_700.dts b/arch/arc/boot/dts/nsim_700.dts
index 5d5e373e0ebc..63970513e4ae 100644
--- a/arch/arc/boot/dts/nsim_700.dts
+++ b/arch/arc/boot/dts/nsim_700.dts
@@ -11,7 +11,6 @@
11 11
12/ { 12/ {
13 compatible = "snps,nsim"; 13 compatible = "snps,nsim";
14 clock-frequency = <80000000>; /* 80 MHZ */
15 #address-cells = <1>; 14 #address-cells = <1>;
16 #size-cells = <1>; 15 #size-cells = <1>;
17 interrupt-parent = <&core_intc>; 16 interrupt-parent = <&core_intc>;
diff --git a/arch/arc/boot/dts/nsimosci.dts b/arch/arc/boot/dts/nsimosci.dts
index b5b060adce8a..763d66c883da 100644
--- a/arch/arc/boot/dts/nsimosci.dts
+++ b/arch/arc/boot/dts/nsimosci.dts
@@ -11,7 +11,6 @@
11 11
12/ { 12/ {
13 compatible = "snps,nsimosci"; 13 compatible = "snps,nsimosci";
14 clock-frequency = <20000000>; /* 20 MHZ */
15 #address-cells = <1>; 14 #address-cells = <1>;
16 #size-cells = <1>; 15 #size-cells = <1>;
17 interrupt-parent = <&core_intc>; 16 interrupt-parent = <&core_intc>;
diff --git a/arch/arc/boot/dts/nsimosci_hs.dts b/arch/arc/boot/dts/nsimosci_hs.dts
index 325e73090a18..4eb97c584b18 100644
--- a/arch/arc/boot/dts/nsimosci_hs.dts
+++ b/arch/arc/boot/dts/nsimosci_hs.dts
@@ -11,7 +11,6 @@
11 11
12/ { 12/ {
13 compatible = "snps,nsimosci_hs"; 13 compatible = "snps,nsimosci_hs";
14 clock-frequency = <20000000>; /* 20 MHZ */
15 #address-cells = <1>; 14 #address-cells = <1>;
16 #size-cells = <1>; 15 #size-cells = <1>;
17 interrupt-parent = <&core_intc>; 16 interrupt-parent = <&core_intc>;
diff --git a/arch/arc/boot/dts/nsimosci_hs_idu.dts b/arch/arc/boot/dts/nsimosci_hs_idu.dts
index ee03d7126581..853f897eb2a3 100644
--- a/arch/arc/boot/dts/nsimosci_hs_idu.dts
+++ b/arch/arc/boot/dts/nsimosci_hs_idu.dts
@@ -11,7 +11,6 @@
11 11
12/ { 12/ {
13 compatible = "snps,nsimosci_hs"; 13 compatible = "snps,nsimosci_hs";
14 clock-frequency = <5000000>; /* 5 MHZ */
15 #address-cells = <1>; 14 #address-cells = <1>;
16 #size-cells = <1>; 15 #size-cells = <1>;
17 interrupt-parent = <&core_intc>; 16 interrupt-parent = <&core_intc>;
diff --git a/arch/arc/boot/dts/skeleton.dtsi b/arch/arc/boot/dts/skeleton.dtsi
index 3a10cc633e2b..65808fe0a290 100644
--- a/arch/arc/boot/dts/skeleton.dtsi
+++ b/arch/arc/boot/dts/skeleton.dtsi
@@ -13,7 +13,6 @@
13 13
14/ { 14/ {
15 compatible = "snps,arc"; 15 compatible = "snps,arc";
16 clock-frequency = <80000000>; /* 80 MHZ */
17 #address-cells = <1>; 16 #address-cells = <1>;
18 #size-cells = <1>; 17 #size-cells = <1>;
19 chosen { }; 18 chosen { };
diff --git a/arch/arc/boot/dts/skeleton_hs.dtsi b/arch/arc/boot/dts/skeleton_hs.dtsi
index 71fd308a9298..2dfe8037dfbb 100644
--- a/arch/arc/boot/dts/skeleton_hs.dtsi
+++ b/arch/arc/boot/dts/skeleton_hs.dtsi
@@ -8,7 +8,6 @@
8 8
9/ { 9/ {
10 compatible = "snps,arc"; 10 compatible = "snps,arc";
11 clock-frequency = <80000000>; /* 80 MHZ */
12 #address-cells = <1>; 11 #address-cells = <1>;
13 #size-cells = <1>; 12 #size-cells = <1>;
14 chosen { }; 13 chosen { };
diff --git a/arch/arc/boot/dts/skeleton_hs_idu.dtsi b/arch/arc/boot/dts/skeleton_hs_idu.dtsi
index d1cb25a66989..4c11079f3565 100644
--- a/arch/arc/boot/dts/skeleton_hs_idu.dtsi
+++ b/arch/arc/boot/dts/skeleton_hs_idu.dtsi
@@ -8,7 +8,6 @@
8 8
9/ { 9/ {
10 compatible = "snps,arc"; 10 compatible = "snps,arc";
11 clock-frequency = <80000000>; /* 80 MHZ */
12 #address-cells = <1>; 11 #address-cells = <1>;
13 #size-cells = <1>; 12 #size-cells = <1>;
14 chosen { }; 13 chosen { };
diff --git a/arch/arc/boot/dts/vdk_axc003.dtsi b/arch/arc/boot/dts/vdk_axc003.dtsi
index ad4ee43bd2ac..0fd6ba985b16 100644
--- a/arch/arc/boot/dts/vdk_axc003.dtsi
+++ b/arch/arc/boot/dts/vdk_axc003.dtsi
@@ -14,7 +14,6 @@
14 14
15/ { 15/ {
16 compatible = "snps,arc"; 16 compatible = "snps,arc";
17 clock-frequency = <50000000>;
18 #address-cells = <1>; 17 #address-cells = <1>;
19 #size-cells = <1>; 18 #size-cells = <1>;
20 19
diff --git a/arch/arc/boot/dts/vdk_axc003_idu.dtsi b/arch/arc/boot/dts/vdk_axc003_idu.dtsi
index a3cb6263c581..82214cd7ba0c 100644
--- a/arch/arc/boot/dts/vdk_axc003_idu.dtsi
+++ b/arch/arc/boot/dts/vdk_axc003_idu.dtsi
@@ -15,7 +15,6 @@
15 15
16/ { 16/ {
17 compatible = "snps,arc"; 17 compatible = "snps,arc";
18 clock-frequency = <50000000>;
19 #address-cells = <1>; 18 #address-cells = <1>;
20 #size-cells = <1>; 19 #size-cells = <1>;
21 20
diff --git a/arch/arc/include/asm/atomic.h b/arch/arc/include/asm/atomic.h
index 5f3dcbbc0cc9..dd683995bc9d 100644
--- a/arch/arc/include/asm/atomic.h
+++ b/arch/arc/include/asm/atomic.h
@@ -25,50 +25,17 @@
25 25
26#define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i)) 26#define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
27 27
28#ifdef CONFIG_ARC_STAR_9000923308
29
30#define SCOND_FAIL_RETRY_VAR_DEF \
31 unsigned int delay = 1, tmp; \
32
33#define SCOND_FAIL_RETRY_ASM \
34 " bz 4f \n" \
35 " ; --- scond fail delay --- \n" \
36 " mov %[tmp], %[delay] \n" /* tmp = delay */ \
37 "2: brne.d %[tmp], 0, 2b \n" /* while (tmp != 0) */ \
38 " sub %[tmp], %[tmp], 1 \n" /* tmp-- */ \
39 " rol %[delay], %[delay] \n" /* delay *= 2 */ \
40 " b 1b \n" /* start over */ \
41 "4: ; --- success --- \n" \
42
43#define SCOND_FAIL_RETRY_VARS \
44 ,[delay] "+&r" (delay),[tmp] "=&r" (tmp) \
45
46#else /* !CONFIG_ARC_STAR_9000923308 */
47
48#define SCOND_FAIL_RETRY_VAR_DEF
49
50#define SCOND_FAIL_RETRY_ASM \
51 " bnz 1b \n" \
52
53#define SCOND_FAIL_RETRY_VARS
54
55#endif
56
57#define ATOMIC_OP(op, c_op, asm_op) \ 28#define ATOMIC_OP(op, c_op, asm_op) \
58static inline void atomic_##op(int i, atomic_t *v) \ 29static inline void atomic_##op(int i, atomic_t *v) \
59{ \ 30{ \
60 unsigned int val; \ 31 unsigned int val; \
61 SCOND_FAIL_RETRY_VAR_DEF \
62 \ 32 \
63 __asm__ __volatile__( \ 33 __asm__ __volatile__( \
64 "1: llock %[val], [%[ctr]] \n" \ 34 "1: llock %[val], [%[ctr]] \n" \
65 " " #asm_op " %[val], %[val], %[i] \n" \ 35 " " #asm_op " %[val], %[val], %[i] \n" \
66 " scond %[val], [%[ctr]] \n" \ 36 " scond %[val], [%[ctr]] \n" \
67 " \n" \ 37 " bnz 1b \n" \
68 SCOND_FAIL_RETRY_ASM \
69 \
70 : [val] "=&r" (val) /* Early clobber to prevent reg reuse */ \ 38 : [val] "=&r" (val) /* Early clobber to prevent reg reuse */ \
71 SCOND_FAIL_RETRY_VARS \
72 : [ctr] "r" (&v->counter), /* Not "m": llock only supports reg direct addr mode */ \ 39 : [ctr] "r" (&v->counter), /* Not "m": llock only supports reg direct addr mode */ \
73 [i] "ir" (i) \ 40 [i] "ir" (i) \
74 : "cc"); \ 41 : "cc"); \
@@ -77,8 +44,7 @@ static inline void atomic_##op(int i, atomic_t *v) \
77#define ATOMIC_OP_RETURN(op, c_op, asm_op) \ 44#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
78static inline int atomic_##op##_return(int i, atomic_t *v) \ 45static inline int atomic_##op##_return(int i, atomic_t *v) \
79{ \ 46{ \
80 unsigned int val; \ 47 unsigned int val; \
81 SCOND_FAIL_RETRY_VAR_DEF \
82 \ 48 \
83 /* \ 49 /* \
84 * Explicit full memory barrier needed before/after as \ 50 * Explicit full memory barrier needed before/after as \
@@ -90,11 +56,8 @@ static inline int atomic_##op##_return(int i, atomic_t *v) \
90 "1: llock %[val], [%[ctr]] \n" \ 56 "1: llock %[val], [%[ctr]] \n" \
91 " " #asm_op " %[val], %[val], %[i] \n" \ 57 " " #asm_op " %[val], %[val], %[i] \n" \
92 " scond %[val], [%[ctr]] \n" \ 58 " scond %[val], [%[ctr]] \n" \
93 " \n" \ 59 " bnz 1b \n" \
94 SCOND_FAIL_RETRY_ASM \
95 \
96 : [val] "=&r" (val) \ 60 : [val] "=&r" (val) \
97 SCOND_FAIL_RETRY_VARS \
98 : [ctr] "r" (&v->counter), \ 61 : [ctr] "r" (&v->counter), \
99 [i] "ir" (i) \ 62 [i] "ir" (i) \
100 : "cc"); \ 63 : "cc"); \
diff --git a/arch/arc/include/asm/entry-compact.h b/arch/arc/include/asm/entry-compact.h
index e0e1faf03c50..14c310f2e0b1 100644
--- a/arch/arc/include/asm/entry-compact.h
+++ b/arch/arc/include/asm/entry-compact.h
@@ -76,8 +76,8 @@
76 * We need to be a bit more cautious here. What if a kernel bug in 76 * We need to be a bit more cautious here. What if a kernel bug in
77 * L1 ISR, caused SP to go whaco (some small value which looks like 77 * L1 ISR, caused SP to go whaco (some small value which looks like
78 * USER stk) and then we take L2 ISR. 78 * USER stk) and then we take L2 ISR.
79 * Above brlo alone would treat it as a valid L1-L2 sceanrio 79 * Above brlo alone would treat it as a valid L1-L2 scenario
80 * instead of shouting alound 80 * instead of shouting around
81 * The only feasible way is to make sure this L2 happened in 81 * The only feasible way is to make sure this L2 happened in
82 * L1 prelogue ONLY i.e. ilink2 is less than a pre-set marker in 82 * L1 prelogue ONLY i.e. ilink2 is less than a pre-set marker in
83 * L1 ISR before it switches stack 83 * L1 ISR before it switches stack
diff --git a/arch/arc/include/asm/mmu_context.h b/arch/arc/include/asm/mmu_context.h
index 1fd467ef658f..b0b87f2447f5 100644
--- a/arch/arc/include/asm/mmu_context.h
+++ b/arch/arc/include/asm/mmu_context.h
@@ -83,7 +83,7 @@ static inline void get_new_mmu_context(struct mm_struct *mm)
83 local_flush_tlb_all(); 83 local_flush_tlb_all();
84 84
85 /* 85 /*
86 * Above checke for rollover of 8 bit ASID in 32 bit container. 86 * Above check for rollover of 8 bit ASID in 32 bit container.
87 * If the container itself wrapped around, set it to a non zero 87 * If the container itself wrapped around, set it to a non zero
88 * "generation" to distinguish from no context 88 * "generation" to distinguish from no context
89 */ 89 */
diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h
index 034bbdc0ff61..858f98ef7f1b 100644
--- a/arch/arc/include/asm/pgtable.h
+++ b/arch/arc/include/asm/pgtable.h
@@ -47,7 +47,7 @@
47 * Page Tables are purely for Linux VM's consumption and the bits below are 47 * Page Tables are purely for Linux VM's consumption and the bits below are
48 * suited to that (uniqueness). Hence some are not implemented in the TLB and 48 * suited to that (uniqueness). Hence some are not implemented in the TLB and
49 * some have different value in TLB. 49 * some have different value in TLB.
50 * e.g. MMU v2: K_READ bit is 8 and so is GLOBAL (possible becoz they live in 50 * e.g. MMU v2: K_READ bit is 8 and so is GLOBAL (possible because they live in
51 * seperate PD0 and PD1, which combined forms a translation entry) 51 * seperate PD0 and PD1, which combined forms a translation entry)
52 * while for PTE perspective, they are 8 and 9 respectively 52 * while for PTE perspective, they are 8 and 9 respectively
53 * with MMU v3: Most bits (except SHARED) represent the exact hardware pos 53 * with MMU v3: Most bits (except SHARED) represent the exact hardware pos
diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h
index f9048994b22f..16b630fbeb6a 100644
--- a/arch/arc/include/asm/processor.h
+++ b/arch/arc/include/asm/processor.h
@@ -78,7 +78,7 @@ struct task_struct;
78#define KSTK_ESP(tsk) (task_pt_regs(tsk)->sp) 78#define KSTK_ESP(tsk) (task_pt_regs(tsk)->sp)
79 79
80/* 80/*
81 * Where abouts of Task's sp, fp, blink when it was last seen in kernel mode. 81 * Where about of Task's sp, fp, blink when it was last seen in kernel mode.
82 * Look in process.c for details of kernel stack layout 82 * Look in process.c for details of kernel stack layout
83 */ 83 */
84#define TSK_K_ESP(tsk) (tsk->thread.ksp) 84#define TSK_K_ESP(tsk) (tsk->thread.ksp)
diff --git a/arch/arc/include/asm/smp.h b/arch/arc/include/asm/smp.h
index 991380438d6b..89fdd1b0a76e 100644
--- a/arch/arc/include/asm/smp.h
+++ b/arch/arc/include/asm/smp.h
@@ -86,7 +86,7 @@ static inline const char *arc_platform_smp_cpuinfo(void)
86 * (1) These insn were introduced only in 4.10 release. So for older released 86 * (1) These insn were introduced only in 4.10 release. So for older released
87 * support needed. 87 * support needed.
88 * 88 *
89 * (2) In a SMP setup, the LLOCK/SCOND atomiticity across CPUs needs to be 89 * (2) In a SMP setup, the LLOCK/SCOND atomicity across CPUs needs to be
90 * gaurantted by the platform (not something which core handles). 90 * gaurantted by the platform (not something which core handles).
91 * Assuming a platform won't, SMP Linux needs to use spinlocks + local IRQ 91 * Assuming a platform won't, SMP Linux needs to use spinlocks + local IRQ
92 * disabling for atomicity. 92 * disabling for atomicity.
diff --git a/arch/arc/include/asm/spinlock.h b/arch/arc/include/asm/spinlock.h
index 800e7c430ca5..cded4a9b5438 100644
--- a/arch/arc/include/asm/spinlock.h
+++ b/arch/arc/include/asm/spinlock.h
@@ -20,11 +20,6 @@
20 20
21#ifdef CONFIG_ARC_HAS_LLSC 21#ifdef CONFIG_ARC_HAS_LLSC
22 22
23/*
24 * A normal LLOCK/SCOND based system, w/o need for livelock workaround
25 */
26#ifndef CONFIG_ARC_STAR_9000923308
27
28static inline void arch_spin_lock(arch_spinlock_t *lock) 23static inline void arch_spin_lock(arch_spinlock_t *lock)
29{ 24{
30 unsigned int val; 25 unsigned int val;
@@ -238,293 +233,6 @@ static inline void arch_write_unlock(arch_rwlock_t *rw)
238 smp_mb(); 233 smp_mb();
239} 234}
240 235
241#else /* CONFIG_ARC_STAR_9000923308 */
242
243/*
244 * HS38x4 could get into a LLOCK/SCOND livelock in case of multiple overlapping
245 * coherency transactions in the SCU. The exclusive line state keeps rotating
246 * among contenting cores leading to a never ending cycle. So break the cycle
247 * by deferring the retry of failed exclusive access (SCOND). The actual delay
248 * needed is function of number of contending cores as well as the unrelated
249 * coherency traffic from other cores. To keep the code simple, start off with
250 * small delay of 1 which would suffice most cases and in case of contention
251 * double the delay. Eventually the delay is sufficient such that the coherency
252 * pipeline is drained, thus a subsequent exclusive access would succeed.
253 */
254
255#define SCOND_FAIL_RETRY_VAR_DEF \
256 unsigned int delay, tmp; \
257
258#define SCOND_FAIL_RETRY_ASM \
259 " ; --- scond fail delay --- \n" \
260 " mov %[tmp], %[delay] \n" /* tmp = delay */ \
261 "2: brne.d %[tmp], 0, 2b \n" /* while (tmp != 0) */ \
262 " sub %[tmp], %[tmp], 1 \n" /* tmp-- */ \
263 " rol %[delay], %[delay] \n" /* delay *= 2 */ \
264 " b 1b \n" /* start over */ \
265 " \n" \
266 "4: ; --- done --- \n" \
267
268#define SCOND_FAIL_RETRY_VARS \
269 ,[delay] "=&r" (delay), [tmp] "=&r" (tmp) \
270
271static inline void arch_spin_lock(arch_spinlock_t *lock)
272{
273 unsigned int val;
274 SCOND_FAIL_RETRY_VAR_DEF;
275
276 smp_mb();
277
278 __asm__ __volatile__(
279 "0: mov %[delay], 1 \n"
280 "1: llock %[val], [%[slock]] \n"
281 " breq %[val], %[LOCKED], 0b \n" /* spin while LOCKED */
282 " scond %[LOCKED], [%[slock]] \n" /* acquire */
283 " bz 4f \n" /* done */
284 " \n"
285 SCOND_FAIL_RETRY_ASM
286
287 : [val] "=&r" (val)
288 SCOND_FAIL_RETRY_VARS
289 : [slock] "r" (&(lock->slock)),
290 [LOCKED] "r" (__ARCH_SPIN_LOCK_LOCKED__)
291 : "memory", "cc");
292
293 smp_mb();
294}
295
296/* 1 - lock taken successfully */
297static inline int arch_spin_trylock(arch_spinlock_t *lock)
298{
299 unsigned int val, got_it = 0;
300 SCOND_FAIL_RETRY_VAR_DEF;
301
302 smp_mb();
303
304 __asm__ __volatile__(
305 "0: mov %[delay], 1 \n"
306 "1: llock %[val], [%[slock]] \n"
307 " breq %[val], %[LOCKED], 4f \n" /* already LOCKED, just bail */
308 " scond %[LOCKED], [%[slock]] \n" /* acquire */
309 " bz.d 4f \n"
310 " mov.z %[got_it], 1 \n" /* got it */
311 " \n"
312 SCOND_FAIL_RETRY_ASM
313
314 : [val] "=&r" (val),
315 [got_it] "+&r" (got_it)
316 SCOND_FAIL_RETRY_VARS
317 : [slock] "r" (&(lock->slock)),
318 [LOCKED] "r" (__ARCH_SPIN_LOCK_LOCKED__)
319 : "memory", "cc");
320
321 smp_mb();
322
323 return got_it;
324}
325
326static inline void arch_spin_unlock(arch_spinlock_t *lock)
327{
328 smp_mb();
329
330 lock->slock = __ARCH_SPIN_LOCK_UNLOCKED__;
331
332 smp_mb();
333}
334
335/*
336 * Read-write spinlocks, allowing multiple readers but only one writer.
337 * Unfair locking as Writers could be starved indefinitely by Reader(s)
338 */
339
340static inline void arch_read_lock(arch_rwlock_t *rw)
341{
342 unsigned int val;
343 SCOND_FAIL_RETRY_VAR_DEF;
344
345 smp_mb();
346
347 /*
348 * zero means writer holds the lock exclusively, deny Reader.
349 * Otherwise grant lock to first/subseq reader
350 *
351 * if (rw->counter > 0) {
352 * rw->counter--;
353 * ret = 1;
354 * }
355 */
356
357 __asm__ __volatile__(
358 "0: mov %[delay], 1 \n"
359 "1: llock %[val], [%[rwlock]] \n"
360 " brls %[val], %[WR_LOCKED], 0b\n" /* <= 0: spin while write locked */
361 " sub %[val], %[val], 1 \n" /* reader lock */
362 " scond %[val], [%[rwlock]] \n"
363 " bz 4f \n" /* done */
364 " \n"
365 SCOND_FAIL_RETRY_ASM
366
367 : [val] "=&r" (val)
368 SCOND_FAIL_RETRY_VARS
369 : [rwlock] "r" (&(rw->counter)),
370 [WR_LOCKED] "ir" (0)
371 : "memory", "cc");
372
373 smp_mb();
374}
375
376/* 1 - lock taken successfully */
377static inline int arch_read_trylock(arch_rwlock_t *rw)
378{
379 unsigned int val, got_it = 0;
380 SCOND_FAIL_RETRY_VAR_DEF;
381
382 smp_mb();
383
384 __asm__ __volatile__(
385 "0: mov %[delay], 1 \n"
386 "1: llock %[val], [%[rwlock]] \n"
387 " brls %[val], %[WR_LOCKED], 4f\n" /* <= 0: already write locked, bail */
388 " sub %[val], %[val], 1 \n" /* counter-- */
389 " scond %[val], [%[rwlock]] \n"
390 " bz.d 4f \n"
391 " mov.z %[got_it], 1 \n" /* got it */
392 " \n"
393 SCOND_FAIL_RETRY_ASM
394
395 : [val] "=&r" (val),
396 [got_it] "+&r" (got_it)
397 SCOND_FAIL_RETRY_VARS
398 : [rwlock] "r" (&(rw->counter)),
399 [WR_LOCKED] "ir" (0)
400 : "memory", "cc");
401
402 smp_mb();
403
404 return got_it;
405}
406
407static inline void arch_write_lock(arch_rwlock_t *rw)
408{
409 unsigned int val;
410 SCOND_FAIL_RETRY_VAR_DEF;
411
412 smp_mb();
413
414 /*
415 * If reader(s) hold lock (lock < __ARCH_RW_LOCK_UNLOCKED__),
416 * deny writer. Otherwise if unlocked grant to writer
417 * Hence the claim that Linux rwlocks are unfair to writers.
418 * (can be starved for an indefinite time by readers).
419 *
420 * if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) {
421 * rw->counter = 0;
422 * ret = 1;
423 * }
424 */
425
426 __asm__ __volatile__(
427 "0: mov %[delay], 1 \n"
428 "1: llock %[val], [%[rwlock]] \n"
429 " brne %[val], %[UNLOCKED], 0b \n" /* while !UNLOCKED spin */
430 " mov %[val], %[WR_LOCKED] \n"
431 " scond %[val], [%[rwlock]] \n"
432 " bz 4f \n"
433 " \n"
434 SCOND_FAIL_RETRY_ASM
435
436 : [val] "=&r" (val)
437 SCOND_FAIL_RETRY_VARS
438 : [rwlock] "r" (&(rw->counter)),
439 [UNLOCKED] "ir" (__ARCH_RW_LOCK_UNLOCKED__),
440 [WR_LOCKED] "ir" (0)
441 : "memory", "cc");
442
443 smp_mb();
444}
445
446/* 1 - lock taken successfully */
447static inline int arch_write_trylock(arch_rwlock_t *rw)
448{
449 unsigned int val, got_it = 0;
450 SCOND_FAIL_RETRY_VAR_DEF;
451
452 smp_mb();
453
454 __asm__ __volatile__(
455 "0: mov %[delay], 1 \n"
456 "1: llock %[val], [%[rwlock]] \n"
457 " brne %[val], %[UNLOCKED], 4f \n" /* !UNLOCKED, bail */
458 " mov %[val], %[WR_LOCKED] \n"
459 " scond %[val], [%[rwlock]] \n"
460 " bz.d 4f \n"
461 " mov.z %[got_it], 1 \n" /* got it */
462 " \n"
463 SCOND_FAIL_RETRY_ASM
464
465 : [val] "=&r" (val),
466 [got_it] "+&r" (got_it)
467 SCOND_FAIL_RETRY_VARS
468 : [rwlock] "r" (&(rw->counter)),
469 [UNLOCKED] "ir" (__ARCH_RW_LOCK_UNLOCKED__),
470 [WR_LOCKED] "ir" (0)
471 : "memory", "cc");
472
473 smp_mb();
474
475 return got_it;
476}
477
478static inline void arch_read_unlock(arch_rwlock_t *rw)
479{
480 unsigned int val;
481
482 smp_mb();
483
484 /*
485 * rw->counter++;
486 */
487 __asm__ __volatile__(
488 "1: llock %[val], [%[rwlock]] \n"
489 " add %[val], %[val], 1 \n"
490 " scond %[val], [%[rwlock]] \n"
491 " bnz 1b \n"
492 " \n"
493 : [val] "=&r" (val)
494 : [rwlock] "r" (&(rw->counter))
495 : "memory", "cc");
496
497 smp_mb();
498}
499
500static inline void arch_write_unlock(arch_rwlock_t *rw)
501{
502 unsigned int val;
503
504 smp_mb();
505
506 /*
507 * rw->counter = __ARCH_RW_LOCK_UNLOCKED__;
508 */
509 __asm__ __volatile__(
510 "1: llock %[val], [%[rwlock]] \n"
511 " scond %[UNLOCKED], [%[rwlock]]\n"
512 " bnz 1b \n"
513 " \n"
514 : [val] "=&r" (val)
515 : [rwlock] "r" (&(rw->counter)),
516 [UNLOCKED] "r" (__ARCH_RW_LOCK_UNLOCKED__)
517 : "memory", "cc");
518
519 smp_mb();
520}
521
522#undef SCOND_FAIL_RETRY_VAR_DEF
523#undef SCOND_FAIL_RETRY_ASM
524#undef SCOND_FAIL_RETRY_VARS
525
526#endif /* CONFIG_ARC_STAR_9000923308 */
527
528#else /* !CONFIG_ARC_HAS_LLSC */ 236#else /* !CONFIG_ARC_HAS_LLSC */
529 237
530static inline void arch_spin_lock(arch_spinlock_t *lock) 238static inline void arch_spin_lock(arch_spinlock_t *lock)
diff --git a/arch/arc/include/asm/thread_info.h b/arch/arc/include/asm/thread_info.h
index 3af67455659a..2d79e527fa50 100644
--- a/arch/arc/include/asm/thread_info.h
+++ b/arch/arc/include/asm/thread_info.h
@@ -103,7 +103,7 @@ static inline __attribute_const__ struct thread_info *current_thread_info(void)
103 103
104/* 104/*
105 * _TIF_ALLWORK_MASK includes SYSCALL_TRACE, but we don't need it. 105 * _TIF_ALLWORK_MASK includes SYSCALL_TRACE, but we don't need it.
106 * SYSCALL_TRACE is anways seperately/unconditionally tested right after a 106 * SYSCALL_TRACE is anyway seperately/unconditionally tested right after a
107 * syscall, so all that reamins to be tested is _TIF_WORK_MASK 107 * syscall, so all that reamins to be tested is _TIF_WORK_MASK
108 */ 108 */
109 109
diff --git a/arch/arc/include/asm/uaccess.h b/arch/arc/include/asm/uaccess.h
index d1da6032b715..a78d5670884f 100644
--- a/arch/arc/include/asm/uaccess.h
+++ b/arch/arc/include/asm/uaccess.h
@@ -32,7 +32,7 @@
32#define __kernel_ok (segment_eq(get_fs(), KERNEL_DS)) 32#define __kernel_ok (segment_eq(get_fs(), KERNEL_DS))
33 33
34/* 34/*
35 * Algorthmically, for __user_ok() we want do: 35 * Algorithmically, for __user_ok() we want do:
36 * (start < TASK_SIZE) && (start+len < TASK_SIZE) 36 * (start < TASK_SIZE) && (start+len < TASK_SIZE)
37 * where TASK_SIZE could either be retrieved from thread_info->addr_limit or 37 * where TASK_SIZE could either be retrieved from thread_info->addr_limit or
38 * emitted directly in code. 38 * emitted directly in code.
diff --git a/arch/arc/include/uapi/asm/swab.h b/arch/arc/include/uapi/asm/swab.h
index 095599a73195..71f3918b0fc3 100644
--- a/arch/arc/include/uapi/asm/swab.h
+++ b/arch/arc/include/uapi/asm/swab.h
@@ -74,7 +74,7 @@
74 __tmp ^ __in; \ 74 __tmp ^ __in; \
75}) 75})
76 76
77#elif (ARC_BSWAP_TYPE == 2) /* Custom single cycle bwap instruction */ 77#elif (ARC_BSWAP_TYPE == 2) /* Custom single cycle bswap instruction */
78 78
79#define __arch_swab32(x) \ 79#define __arch_swab32(x) \
80({ \ 80({ \
diff --git a/arch/arc/kernel/entry-compact.S b/arch/arc/kernel/entry-compact.S
index 0cb0abaa0479..98812c1248df 100644
--- a/arch/arc/kernel/entry-compact.S
+++ b/arch/arc/kernel/entry-compact.S
@@ -91,27 +91,13 @@ VECTOR mem_service ; 0x8, Mem exception (0x1)
91VECTOR instr_service ; 0x10, Instrn Error (0x2) 91VECTOR instr_service ; 0x10, Instrn Error (0x2)
92 92
93; ******************** Device ISRs ********************** 93; ******************** Device ISRs **********************
94#ifdef CONFIG_ARC_IRQ3_LV2 94#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
95VECTOR handle_interrupt_level2
96#else
97VECTOR handle_interrupt_level1
98#endif
99
100VECTOR handle_interrupt_level1
101
102#ifdef CONFIG_ARC_IRQ5_LV2
103VECTOR handle_interrupt_level2
104#else
105VECTOR handle_interrupt_level1
106#endif
107
108#ifdef CONFIG_ARC_IRQ6_LV2
109VECTOR handle_interrupt_level2 95VECTOR handle_interrupt_level2
110#else 96#else
111VECTOR handle_interrupt_level1 97VECTOR handle_interrupt_level1
112#endif 98#endif
113 99
114.rept 25 100.rept 28
115VECTOR handle_interrupt_level1 ; Other devices 101VECTOR handle_interrupt_level1 ; Other devices
116.endr 102.endr
117 103
diff --git a/arch/arc/kernel/intc-compact.c b/arch/arc/kernel/intc-compact.c
index c5cceca36118..ce9deb953ca9 100644
--- a/arch/arc/kernel/intc-compact.c
+++ b/arch/arc/kernel/intc-compact.c
@@ -28,10 +28,8 @@ void arc_init_IRQ(void)
28{ 28{
29 int level_mask = 0; 29 int level_mask = 0;
30 30
31 /* setup any high priority Interrupts (Level2 in ARCompact jargon) */ 31 /* Is timer high priority Interrupt (Level2 in ARCompact jargon) */
32 level_mask |= IS_ENABLED(CONFIG_ARC_IRQ3_LV2) << 3; 32 level_mask |= IS_ENABLED(CONFIG_ARC_COMPACT_IRQ_LEVELS) << TIMER0_IRQ;
33 level_mask |= IS_ENABLED(CONFIG_ARC_IRQ5_LV2) << 5;
34 level_mask |= IS_ENABLED(CONFIG_ARC_IRQ6_LV2) << 6;
35 33
36 /* 34 /*
37 * Write to register, even if no LV2 IRQs configured to reset it 35 * Write to register, even if no LV2 IRQs configured to reset it
diff --git a/arch/arc/kernel/perf_event.c b/arch/arc/kernel/perf_event.c
index 6fd48021324b..08f03d9b5b3e 100644
--- a/arch/arc/kernel/perf_event.c
+++ b/arch/arc/kernel/perf_event.c
@@ -108,7 +108,7 @@ static void arc_perf_event_update(struct perf_event *event,
108 int64_t delta = new_raw_count - prev_raw_count; 108 int64_t delta = new_raw_count - prev_raw_count;
109 109
110 /* 110 /*
111 * We don't afaraid of hwc->prev_count changing beneath our feet 111 * We aren't afraid of hwc->prev_count changing beneath our feet
112 * because there's no way for us to re-enter this function anytime. 112 * because there's no way for us to re-enter this function anytime.
113 */ 113 */
114 local64_set(&hwc->prev_count, new_raw_count); 114 local64_set(&hwc->prev_count, new_raw_count);
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index f63b8bfefb0c..2ee7a4d758a8 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -392,7 +392,7 @@ void __init setup_arch(char **cmdline_p)
392 /* 392 /*
393 * If we are here, it is established that @uboot_arg didn't 393 * If we are here, it is established that @uboot_arg didn't
394 * point to DT blob. Instead if u-boot says it is cmdline, 394 * point to DT blob. Instead if u-boot says it is cmdline,
395 * Appent to embedded DT cmdline. 395 * append to embedded DT cmdline.
396 * setup_machine_fdt() would have populated @boot_command_line 396 * setup_machine_fdt() would have populated @boot_command_line
397 */ 397 */
398 if (uboot_tag == 1) { 398 if (uboot_tag == 1) {
diff --git a/arch/arc/kernel/signal.c b/arch/arc/kernel/signal.c
index 004b7f0bc76c..6cb3736b6b83 100644
--- a/arch/arc/kernel/signal.c
+++ b/arch/arc/kernel/signal.c
@@ -34,7 +34,7 @@
34 * -ViXS were still seeing crashes when using insmod to load drivers. 34 * -ViXS were still seeing crashes when using insmod to load drivers.
35 * It turned out that the code to change Execute permssions for TLB entries 35 * It turned out that the code to change Execute permssions for TLB entries
36 * of user was not guarded for interrupts (mod_tlb_permission) 36 * of user was not guarded for interrupts (mod_tlb_permission)
37 * This was cauing TLB entries to be overwritten on unrelated indexes 37 * This was causing TLB entries to be overwritten on unrelated indexes
38 * 38 *
39 * Vineetg: July 15th 2008: Bug #94183 39 * Vineetg: July 15th 2008: Bug #94183
40 * -Exception happens in Delay slot of a JMP, and before user space resumes, 40 * -Exception happens in Delay slot of a JMP, and before user space resumes,
diff --git a/arch/arc/kernel/troubleshoot.c b/arch/arc/kernel/troubleshoot.c
index a6f91e88ce36..934150e7ac48 100644
--- a/arch/arc/kernel/troubleshoot.c
+++ b/arch/arc/kernel/troubleshoot.c
@@ -276,7 +276,7 @@ static int tlb_stats_open(struct inode *inode, struct file *file)
276 return 0; 276 return 0;
277} 277}
278 278
279/* called on user read(): display the couters */ 279/* called on user read(): display the counters */
280static ssize_t tlb_stats_output(struct file *file, /* file descriptor */ 280static ssize_t tlb_stats_output(struct file *file, /* file descriptor */
281 char __user *user_buf, /* user buffer */ 281 char __user *user_buf, /* user buffer */
282 size_t len, /* length of buffer */ 282 size_t len, /* length of buffer */
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 9e5eddbb856f..5a294b2c3cb3 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -215,7 +215,7 @@ slc_chk:
215 * ------------------ 215 * ------------------
216 * This ver of MMU supports variable page sizes (1k-16k): although Linux will 216 * This ver of MMU supports variable page sizes (1k-16k): although Linux will
217 * only support 8k (default), 16k and 4k. 217 * only support 8k (default), 16k and 4k.
218 * However from hardware perspective, smaller page sizes aggrevate aliasing 218 * However from hardware perspective, smaller page sizes aggravate aliasing
219 * meaning more vaddr bits needed to disambiguate the cache-line-op ; 219 * meaning more vaddr bits needed to disambiguate the cache-line-op ;
220 * the existing scheme of piggybacking won't work for certain configurations. 220 * the existing scheme of piggybacking won't work for certain configurations.
221 * Two new registers IC_PTAG and DC_PTAG inttoduced. 221 * Two new registers IC_PTAG and DC_PTAG inttoduced.
@@ -302,7 +302,7 @@ void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,
302 302
303 /* 303 /*
304 * This is technically for MMU v4, using the MMU v3 programming model 304 * This is technically for MMU v4, using the MMU v3 programming model
305 * Special work for HS38 aliasing I-cache configuratino with PAE40 305 * Special work for HS38 aliasing I-cache configuration with PAE40
306 * - upper 8 bits of paddr need to be written into PTAG_HI 306 * - upper 8 bits of paddr need to be written into PTAG_HI
307 * - (and needs to be written before the lower 32 bits) 307 * - (and needs to be written before the lower 32 bits)
308 * Note that PTAG_HI is hoisted outside the line loop 308 * Note that PTAG_HI is hoisted outside the line loop
@@ -936,7 +936,7 @@ void arc_cache_init(void)
936 ic->ver, CONFIG_ARC_MMU_VER); 936 ic->ver, CONFIG_ARC_MMU_VER);
937 937
938 /* 938 /*
939 * In MMU v4 (HS38x) the alising icache config uses IVIL/PTAG 939 * In MMU v4 (HS38x) the aliasing icache config uses IVIL/PTAG
940 * pair to provide vaddr/paddr respectively, just as in MMU v3 940 * pair to provide vaddr/paddr respectively, just as in MMU v3
941 */ 941 */
942 if (is_isa_arcv2() && ic->alias) 942 if (is_isa_arcv2() && ic->alias)
diff --git a/arch/arc/mm/dma.c b/arch/arc/mm/dma.c
index 8c8e36fa5659..73d7e4c75b7d 100644
--- a/arch/arc/mm/dma.c
+++ b/arch/arc/mm/dma.c
@@ -10,7 +10,7 @@
10 * DMA Coherent API Notes 10 * DMA Coherent API Notes
11 * 11 *
12 * I/O is inherently non-coherent on ARC. So a coherent DMA buffer is 12 * I/O is inherently non-coherent on ARC. So a coherent DMA buffer is
13 * implemented by accessintg it using a kernel virtual address, with 13 * implemented by accessing it using a kernel virtual address, with
14 * Cache bit off in the TLB entry. 14 * Cache bit off in the TLB entry.
15 * 15 *
16 * The default DMA address == Phy address which is 0x8000_0000 based. 16 * The default DMA address == Phy address which is 0x8000_0000 based.
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 06b6c2d695bf..414b42710a36 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -741,6 +741,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
741 sun7i-a20-olimex-som-evb.dtb \ 741 sun7i-a20-olimex-som-evb.dtb \
742 sun7i-a20-olinuxino-lime.dtb \ 742 sun7i-a20-olinuxino-lime.dtb \
743 sun7i-a20-olinuxino-lime2.dtb \ 743 sun7i-a20-olinuxino-lime2.dtb \
744 sun7i-a20-olinuxino-lime2-emmc.dtb \
744 sun7i-a20-olinuxino-micro.dtb \ 745 sun7i-a20-olinuxino-micro.dtb \
745 sun7i-a20-orangepi.dtb \ 746 sun7i-a20-orangepi.dtb \
746 sun7i-a20-orangepi-mini.dtb \ 747 sun7i-a20-orangepi-mini.dtb \
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts
index d82dd6e3f9b1..5687d6b4da60 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -418,7 +418,7 @@
418 status = "okay"; 418 status = "okay";
419 pinctrl-names = "default"; 419 pinctrl-names = "default";
420 pinctrl-0 = <&i2c0_pins>; 420 pinctrl-0 = <&i2c0_pins>;
421 clock-frequency = <400000>; 421 clock-frequency = <100000>;
422 422
423 tps@24 { 423 tps@24 {
424 compatible = "ti,tps65218"; 424 compatible = "ti,tps65218";
diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi
index b01a5948cdd0..0e63b9dff6e7 100644
--- a/arch/arm/boot/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi
@@ -60,10 +60,26 @@
60 60
61 tps659038_pmic { 61 tps659038_pmic {
62 compatible = "ti,tps659038-pmic"; 62 compatible = "ti,tps659038-pmic";
63
64 smps12-in-supply = <&vmain>;
65 smps3-in-supply = <&vmain>;
66 smps45-in-supply = <&vmain>;
67 smps6-in-supply = <&vmain>;
68 smps7-in-supply = <&vmain>;
69 smps8-in-supply = <&vmain>;
70 smps9-in-supply = <&vmain>;
71 ldo1-in-supply = <&vmain>;
72 ldo2-in-supply = <&vmain>;
73 ldo3-in-supply = <&vmain>;
74 ldo4-in-supply = <&vmain>;
75 ldo9-in-supply = <&vmain>;
76 ldoln-in-supply = <&vmain>;
77 ldousb-in-supply = <&vmain>;
78 ldortc-in-supply = <&vmain>;
79
63 regulators { 80 regulators {
64 smps12_reg: smps12 { 81 smps12_reg: smps12 {
65 /* VDD_MPU */ 82 /* VDD_MPU */
66 vin-supply = <&vmain>;
67 regulator-name = "smps12"; 83 regulator-name = "smps12";
68 regulator-min-microvolt = <850000>; 84 regulator-min-microvolt = <850000>;
69 regulator-max-microvolt = <1250000>; 85 regulator-max-microvolt = <1250000>;
@@ -73,7 +89,6 @@
73 89
74 smps3_reg: smps3 { 90 smps3_reg: smps3 {
75 /* VDD_DDR EMIF1 EMIF2 */ 91 /* VDD_DDR EMIF1 EMIF2 */
76 vin-supply = <&vmain>;
77 regulator-name = "smps3"; 92 regulator-name = "smps3";
78 regulator-min-microvolt = <1350000>; 93 regulator-min-microvolt = <1350000>;
79 regulator-max-microvolt = <1350000>; 94 regulator-max-microvolt = <1350000>;
@@ -84,7 +99,6 @@
84 smps45_reg: smps45 { 99 smps45_reg: smps45 {
85 /* VDD_DSPEVE on AM572 */ 100 /* VDD_DSPEVE on AM572 */
86 /* VDD_IVA + VDD_DSP on AM571 */ 101 /* VDD_IVA + VDD_DSP on AM571 */
87 vin-supply = <&vmain>;
88 regulator-name = "smps45"; 102 regulator-name = "smps45";
89 regulator-min-microvolt = <850000>; 103 regulator-min-microvolt = <850000>;
90 regulator-max-microvolt = <1250000>; 104 regulator-max-microvolt = <1250000>;
@@ -94,7 +108,6 @@
94 108
95 smps6_reg: smps6 { 109 smps6_reg: smps6 {
96 /* VDD_GPU */ 110 /* VDD_GPU */
97 vin-supply = <&vmain>;
98 regulator-name = "smps6"; 111 regulator-name = "smps6";
99 regulator-min-microvolt = <850000>; 112 regulator-min-microvolt = <850000>;
100 regulator-max-microvolt = <1250000>; 113 regulator-max-microvolt = <1250000>;
@@ -104,7 +117,6 @@
104 117
105 smps7_reg: smps7 { 118 smps7_reg: smps7 {
106 /* VDD_CORE */ 119 /* VDD_CORE */
107 vin-supply = <&vmain>;
108 regulator-name = "smps7"; 120 regulator-name = "smps7";
109 regulator-min-microvolt = <850000>; 121 regulator-min-microvolt = <850000>;
110 regulator-max-microvolt = <1150000>; 122 regulator-max-microvolt = <1150000>;
@@ -115,13 +127,11 @@
115 smps8_reg: smps8 { 127 smps8_reg: smps8 {
116 /* 5728 - VDD_IVAHD */ 128 /* 5728 - VDD_IVAHD */
117 /* 5718 - N.C. test point */ 129 /* 5718 - N.C. test point */
118 vin-supply = <&vmain>;
119 regulator-name = "smps8"; 130 regulator-name = "smps8";
120 }; 131 };
121 132
122 smps9_reg: smps9 { 133 smps9_reg: smps9 {
123 /* VDD_3_3D */ 134 /* VDD_3_3D */
124 vin-supply = <&vmain>;
125 regulator-name = "smps9"; 135 regulator-name = "smps9";
126 regulator-min-microvolt = <3300000>; 136 regulator-min-microvolt = <3300000>;
127 regulator-max-microvolt = <3300000>; 137 regulator-max-microvolt = <3300000>;
@@ -132,7 +142,6 @@
132 ldo1_reg: ldo1 { 142 ldo1_reg: ldo1 {
133 /* VDDSHV8 - VSDMMC */ 143 /* VDDSHV8 - VSDMMC */
134 /* NOTE: on rev 1.3a, data supply */ 144 /* NOTE: on rev 1.3a, data supply */
135 vin-supply = <&vmain>;
136 regulator-name = "ldo1"; 145 regulator-name = "ldo1";
137 regulator-min-microvolt = <1800000>; 146 regulator-min-microvolt = <1800000>;
138 regulator-max-microvolt = <3300000>; 147 regulator-max-microvolt = <3300000>;
@@ -142,7 +151,6 @@
142 151
143 ldo2_reg: ldo2 { 152 ldo2_reg: ldo2 {
144 /* VDDSH18V */ 153 /* VDDSH18V */
145 vin-supply = <&vmain>;
146 regulator-name = "ldo2"; 154 regulator-name = "ldo2";
147 regulator-min-microvolt = <1800000>; 155 regulator-min-microvolt = <1800000>;
148 regulator-max-microvolt = <1800000>; 156 regulator-max-microvolt = <1800000>;
@@ -152,7 +160,6 @@
152 160
153 ldo3_reg: ldo3 { 161 ldo3_reg: ldo3 {
154 /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */ 162 /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */
155 vin-supply = <&vmain>;
156 regulator-name = "ldo3"; 163 regulator-name = "ldo3";
157 regulator-min-microvolt = <1800000>; 164 regulator-min-microvolt = <1800000>;
158 regulator-max-microvolt = <1800000>; 165 regulator-max-microvolt = <1800000>;
@@ -162,7 +169,6 @@
162 169
163 ldo4_reg: ldo4 { 170 ldo4_reg: ldo4 {
164 /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/ 171 /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
165 vin-supply = <&vmain>;
166 regulator-name = "ldo4"; 172 regulator-name = "ldo4";
167 regulator-min-microvolt = <1800000>; 173 regulator-min-microvolt = <1800000>;
168 regulator-max-microvolt = <1800000>; 174 regulator-max-microvolt = <1800000>;
@@ -174,7 +180,6 @@
174 180
175 ldo9_reg: ldo9 { 181 ldo9_reg: ldo9 {
176 /* VDD_RTC */ 182 /* VDD_RTC */
177 vin-supply = <&vmain>;
178 regulator-name = "ldo9"; 183 regulator-name = "ldo9";
179 regulator-min-microvolt = <840000>; 184 regulator-min-microvolt = <840000>;
180 regulator-max-microvolt = <1160000>; 185 regulator-max-microvolt = <1160000>;
@@ -184,7 +189,6 @@
184 189
185 ldoln_reg: ldoln { 190 ldoln_reg: ldoln {
186 /* VDDA_1V8_PLL */ 191 /* VDDA_1V8_PLL */
187 vin-supply = <&vmain>;
188 regulator-name = "ldoln"; 192 regulator-name = "ldoln";
189 regulator-min-microvolt = <1800000>; 193 regulator-min-microvolt = <1800000>;
190 regulator-max-microvolt = <1800000>; 194 regulator-max-microvolt = <1800000>;
@@ -194,7 +198,6 @@
194 198
195 ldousb_reg: ldousb { 199 ldousb_reg: ldousb {
196 /* VDDA_3V_USB: VDDA_USBHS33 */ 200 /* VDDA_3V_USB: VDDA_USBHS33 */
197 vin-supply = <&vmain>;
198 regulator-name = "ldousb"; 201 regulator-name = "ldousb";
199 regulator-min-microvolt = <3300000>; 202 regulator-min-microvolt = <3300000>;
200 regulator-max-microvolt = <3300000>; 203 regulator-max-microvolt = <3300000>;
@@ -204,7 +207,6 @@
204 207
205 ldortc_reg: ldortc { 208 ldortc_reg: ldortc {
206 /* VDDA_RTC */ 209 /* VDDA_RTC */
207 vin-supply = <&vmain>;
208 regulator-name = "ldortc"; 210 regulator-name = "ldortc";
209 regulator-min-microvolt = <1800000>; 211 regulator-min-microvolt = <1800000>;
210 regulator-max-microvolt = <1800000>; 212 regulator-max-microvolt = <1800000>;
diff --git a/arch/arm/boot/dts/dm8148-evm.dts b/arch/arm/boot/dts/dm8148-evm.dts
index cbc17b0794b1..4128fa91823c 100644
--- a/arch/arm/boot/dts/dm8148-evm.dts
+++ b/arch/arm/boot/dts/dm8148-evm.dts
@@ -93,6 +93,10 @@
93 }; 93 };
94}; 94};
95 95
96&mmc1 {
97 status = "disabled";
98};
99
96&mmc2 { 100&mmc2 {
97 pinctrl-names = "default"; 101 pinctrl-names = "default";
98 pinctrl-0 = <&sd1_pins>; 102 pinctrl-0 = <&sd1_pins>;
@@ -101,6 +105,10 @@
101 cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; 105 cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
102}; 106};
103 107
108&mmc3 {
109 status = "disabled";
110};
111
104&pincntl { 112&pincntl {
105 sd1_pins: pinmux_sd1_pins { 113 sd1_pins: pinmux_sd1_pins {
106 pinctrl-single,pins = < 114 pinctrl-single,pins = <
diff --git a/arch/arm/boot/dts/dm8148-t410.dts b/arch/arm/boot/dts/dm8148-t410.dts
index 5d4313fd5a46..3f184863e0c5 100644
--- a/arch/arm/boot/dts/dm8148-t410.dts
+++ b/arch/arm/boot/dts/dm8148-t410.dts
@@ -45,6 +45,14 @@
45 phy-mode = "rgmii"; 45 phy-mode = "rgmii";
46}; 46};
47 47
48&mmc1 {
49 status = "disabled";
50};
51
52&mmc2 {
53 status = "disabled";
54};
55
48&mmc3 { 56&mmc3 {
49 pinctrl-names = "default"; 57 pinctrl-names = "default";
50 pinctrl-0 = <&sd2_pins>; 58 pinctrl-0 = <&sd2_pins>;
@@ -53,6 +61,7 @@
53 dmas = <&edma_xbar 8 0 1 /* use SDTXEVT1 instead of MCASP0TX */ 61 dmas = <&edma_xbar 8 0 1 /* use SDTXEVT1 instead of MCASP0TX */
54 &edma_xbar 9 0 2>; /* use SDRXEVT1 instead of MCASP0RX */ 62 &edma_xbar 9 0 2>; /* use SDRXEVT1 instead of MCASP0RX */
55 dma-names = "tx", "rx"; 63 dma-names = "tx", "rx";
64 non-removable;
56}; 65};
57 66
58&pincntl { 67&pincntl {
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index e0074014385a..3a8f3976f6f9 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1451,6 +1451,8 @@
1451 ti,hwmods = "gpmc"; 1451 ti,hwmods = "gpmc";
1452 reg = <0x50000000 0x37c>; /* device IO registers */ 1452 reg = <0x50000000 0x37c>; /* device IO registers */
1453 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1453 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1454 dmas = <&edma_xbar 4 0>;
1455 dma-names = "rxtx";
1454 gpmc,num-cs = <8>; 1456 gpmc,num-cs = <8>;
1455 gpmc,num-waitpins = <2>; 1457 gpmc,num-waitpins = <2>;
1456 #address-cells = <2>; 1458 #address-cells = <2>;
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 4220eeffc65a..5e06020f450b 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -107,8 +107,8 @@
107 reg = <0x58000000 0x80>, 107 reg = <0x58000000 0x80>,
108 <0x58004054 0x4>, 108 <0x58004054 0x4>,
109 <0x58004300 0x20>, 109 <0x58004300 0x20>,
110 <0x58005054 0x4>, 110 <0x58009054 0x4>,
111 <0x58005300 0x20>; 111 <0x58009300 0x20>;
112 reg-names = "dss", "pll1_clkctrl", "pll1", 112 reg-names = "dss", "pll1_clkctrl", "pll1",
113 "pll2_clkctrl", "pll2"; 113 "pll2_clkctrl", "pll2";
114 114
diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
index ddfe1f558c10..fa14f77df563 100644
--- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
@@ -242,7 +242,7 @@
242 hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>; 242 hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
243 243
244 ports { 244 ports {
245 port0 { 245 port {
246 dp_out: endpoint { 246 dp_out: endpoint {
247 remote-endpoint = <&bridge_in>; 247 remote-endpoint = <&bridge_in>;
248 }; 248 };
@@ -485,13 +485,20 @@
485 edid-emulation = <5>; 485 edid-emulation = <5>;
486 486
487 ports { 487 ports {
488 port0 { 488 #address-cells = <1>;
489 #size-cells = <0>;
490
491 port@0 {
492 reg = <0>;
493
489 bridge_out: endpoint { 494 bridge_out: endpoint {
490 remote-endpoint = <&panel_in>; 495 remote-endpoint = <&panel_in>;
491 }; 496 };
492 }; 497 };
493 498
494 port1 { 499 port@1 {
500 reg = <1>;
501
495 bridge_in: endpoint { 502 bridge_in: endpoint {
496 remote-endpoint = <&dp_out>; 503 remote-endpoint = <&dp_out>;
497 }; 504 };
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index f9d2e4f1a0e0..1de972d46a87 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -163,7 +163,7 @@
163 hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; 163 hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>;
164 164
165 ports { 165 ports {
166 port0 { 166 port {
167 dp_out: endpoint { 167 dp_out: endpoint {
168 remote-endpoint = <&bridge_in>; 168 remote-endpoint = <&bridge_in>;
169 }; 169 };
@@ -631,13 +631,20 @@
631 use-external-pwm; 631 use-external-pwm;
632 632
633 ports { 633 ports {
634 port0 { 634 #address-cells = <1>;
635 #size-cells = <0>;
636
637 port@0 {
638 reg = <0>;
639
635 bridge_out: endpoint { 640 bridge_out: endpoint {
636 remote-endpoint = <&panel_in>; 641 remote-endpoint = <&panel_in>;
637 }; 642 };
638 }; 643 };
639 644
640 port1 { 645 port@1 {
646 reg = <1>;
647
641 bridge_in: endpoint { 648 bridge_in: endpoint {
642 remote-endpoint = <&dp_out>; 649 remote-endpoint = <&dp_out>;
643 }; 650 };
diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts
index 76056ba92ced..ed449827c3d3 100644
--- a/arch/arm/boot/dts/omap3-evm-37xx.dts
+++ b/arch/arm/boot/dts/omap3-evm-37xx.dts
@@ -85,7 +85,7 @@
85 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ 85 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
86 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ 86 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
87 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ 87 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
88 OMAP3_CORE1_IOPAD(0x215e, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ 88 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
89 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ 89 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
90 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ 90 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
91 >; 91 >;
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index 41f5d386f21f..f4f2ce46d681 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -188,6 +188,7 @@
188 vmmc-supply = <&vmmc1>; 188 vmmc-supply = <&vmmc1>;
189 vmmc_aux-supply = <&vsim>; 189 vmmc_aux-supply = <&vsim>;
190 bus-width = <4>; 190 bus-width = <4>;
191 cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
191}; 192};
192 193
193&mmc3 { 194&mmc3 {
diff --git a/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/omap3-igep0020-common.dtsi
index d6f839cab649..b6971060648a 100644
--- a/arch/arm/boot/dts/omap3-igep0020-common.dtsi
+++ b/arch/arm/boot/dts/omap3-igep0020-common.dtsi
@@ -194,6 +194,12 @@
194 OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */ 194 OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
195 >; 195 >;
196 }; 196 };
197
198 mmc1_wp_pins: pinmux_mmc1_cd_pins {
199 pinctrl-single,pins = <
200 OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT | MUX_MODE4) /* etk_d15.gpio_29 */
201 >;
202 };
197}; 203};
198 204
199&i2c3 { 205&i2c3 {
@@ -250,3 +256,8 @@
250 }; 256 };
251 }; 257 };
252}; 258};
259
260&mmc1 {
261 pinctrl-0 = <&mmc1_pins &mmc1_wp_pins>;
262 wp-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; /* gpio_29 */
263};
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index d9e2d9c6e999..2b74a81d1de2 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -288,7 +288,7 @@
288 pinctrl-single,pins = < 288 pinctrl-single,pins = <
289 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ 289 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */
290 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ 290 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */
291 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */ 291 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */
292 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ 292 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */
293 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ 293 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */
294 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ 294 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */
@@ -300,7 +300,7 @@
300 modem_pins: pinmux_modem { 300 modem_pins: pinmux_modem {
301 pinctrl-single,pins = < 301 pinctrl-single,pins = <
302 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */ 302 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */
303 OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* gpio 72 => ape_rst_rq */ 303 OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* gpio 72 => ape_rst_rq */
304 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */ 304 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */
305 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */ 305 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */
306 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */ 306 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi
index a00ca761675d..927b17fc4ed8 100644
--- a/arch/arm/boot/dts/omap3-n950-n9.dtsi
+++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi
@@ -97,7 +97,7 @@
97 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ 97 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */
98 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ 98 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */
99 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ 99 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */
100 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */ 100 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */
101 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ 101 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */
102 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ 102 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */
103 OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ 103 OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */
@@ -110,7 +110,7 @@
110 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE7) /* ssi1_dat_tx */ 110 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE7) /* ssi1_dat_tx */
111 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE7) /* ssi1_flag_tx */ 111 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE7) /* ssi1_flag_tx */
112 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLDOWN | MUX_MODE7) /* ssi1_rdy_tx */ 112 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLDOWN | MUX_MODE7) /* ssi1_rdy_tx */
113 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */ 113 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */
114 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE7) /* ssi1_dat_rx */ 114 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE7) /* ssi1_dat_rx */
115 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE7) /* ssi1_flag_rx */ 115 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE7) /* ssi1_flag_rx */
116 OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE4) /* ssi1_rdy_rx */ 116 OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE4) /* ssi1_rdy_rx */
@@ -120,7 +120,7 @@
120 120
121 modem_pins1: pinmux_modem_core1_pins { 121 modem_pins1: pinmux_modem_core1_pins {
122 pinctrl-single,pins = < 122 pinctrl-single,pins = <
123 OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* gpio_34 (ape_rst_rq) */ 123 OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | MUX_MODE4) /* gpio_34 (ape_rst_rq) */
124 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE4) /* gpio_88 (cmt_rst_rq) */ 124 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE4) /* gpio_88 (cmt_rst_rq) */
125 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE4) /* gpio_93 (cmt_apeslpx) */ 125 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE4) /* gpio_93 (cmt_apeslpx) */
126 >; 126 >;
diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts
index f19170bdcc1f..c29b41dc7b95 100644
--- a/arch/arm/boot/dts/omap3-zoom3.dts
+++ b/arch/arm/boot/dts/omap3-zoom3.dts
@@ -98,7 +98,7 @@
98 pinctrl-single,pins = < 98 pinctrl-single,pins = <
99 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ 99 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */
100 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ 100 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */
101 OMAP3_CORE1_IOPAD(0x217a, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ 101 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
102 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ 102 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
103 >; 103 >;
104 }; 104 };
@@ -107,7 +107,7 @@
107 pinctrl-single,pins = < 107 pinctrl-single,pins = <
108 OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ 108 OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */
109 OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ 109 OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */
110 OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ 110 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
111 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ 111 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
112 >; 112 >;
113 }; 113 };
@@ -125,7 +125,7 @@
125 pinctrl-single,pins = < 125 pinctrl-single,pins = <
126 OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ 126 OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */
127 OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ 127 OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */
128 OMAP3630_CORE2_IOPAD(0x25e6, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ 128 OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
129 OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ 129 OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */
130 OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ 130 OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */
131 >; 131 >;
diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi
index dc759a3028b7..5d5b620b7d9b 100644
--- a/arch/arm/boot/dts/omap5-board-common.dtsi
+++ b/arch/arm/boot/dts/omap5-board-common.dtsi
@@ -14,6 +14,29 @@
14 display0 = &hdmi0; 14 display0 = &hdmi0;
15 }; 15 };
16 16
17 vmain: fixedregulator-vmain {
18 compatible = "regulator-fixed";
19 regulator-name = "vmain";
20 regulator-min-microvolt = <5000000>;
21 regulator-max-microvolt = <5000000>;
22 };
23
24 vsys_cobra: fixedregulator-vsys_cobra {
25 compatible = "regulator-fixed";
26 regulator-name = "vsys_cobra";
27 vin-supply = <&vmain>;
28 regulator-min-microvolt = <5000000>;
29 regulator-max-microvolt = <5000000>;
30 };
31
32 vdds_1v8_main: fixedregulator-vdds_1v8_main {
33 compatible = "regulator-fixed";
34 regulator-name = "vdds_1v8_main";
35 vin-supply = <&smps7_reg>;
36 regulator-min-microvolt = <1800000>;
37 regulator-max-microvolt = <1800000>;
38 };
39
17 vmmcsd_fixed: fixedregulator-mmcsd { 40 vmmcsd_fixed: fixedregulator-mmcsd {
18 compatible = "regulator-fixed"; 41 compatible = "regulator-fixed";
19 regulator-name = "vmmcsd_fixed"; 42 regulator-name = "vmmcsd_fixed";
@@ -309,7 +332,7 @@
309 332
310 wlcore_irq_pin: pinmux_wlcore_irq_pin { 333 wlcore_irq_pin: pinmux_wlcore_irq_pin {
311 pinctrl-single,pins = < 334 pinctrl-single,pins = <
312 OMAP5_IOPAD(0x40, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */ 335 OMAP5_IOPAD(0x40, PIN_INPUT_PULLUP | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */
313 >; 336 >;
314 }; 337 };
315}; 338};
@@ -409,6 +432,26 @@
409 432
410 ti,ldo6-vibrator; 433 ti,ldo6-vibrator;
411 434
435 smps123-in-supply = <&vsys_cobra>;
436 smps45-in-supply = <&vsys_cobra>;
437 smps6-in-supply = <&vsys_cobra>;
438 smps7-in-supply = <&vsys_cobra>;
439 smps8-in-supply = <&vsys_cobra>;
440 smps9-in-supply = <&vsys_cobra>;
441 smps10_out2-in-supply = <&vsys_cobra>;
442 smps10_out1-in-supply = <&vsys_cobra>;
443 ldo1-in-supply = <&vsys_cobra>;
444 ldo2-in-supply = <&vsys_cobra>;
445 ldo3-in-supply = <&vdds_1v8_main>;
446 ldo4-in-supply = <&vdds_1v8_main>;
447 ldo5-in-supply = <&vsys_cobra>;
448 ldo6-in-supply = <&vdds_1v8_main>;
449 ldo7-in-supply = <&vsys_cobra>;
450 ldo8-in-supply = <&vsys_cobra>;
451 ldo9-in-supply = <&vmmcsd_fixed>;
452 ldoln-in-supply = <&vsys_cobra>;
453 ldousb-in-supply = <&vsys_cobra>;
454
412 regulators { 455 regulators {
413 smps123_reg: smps123 { 456 smps123_reg: smps123 {
414 /* VDD_OPP_MPU */ 457 /* VDD_OPP_MPU */
@@ -600,7 +643,8 @@
600 pinctrl-0 = <&twl6040_pins>; 643 pinctrl-0 = <&twl6040_pins>;
601 644
602 interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */ 645 interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */
603 ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */ 646
647 /* audpwron gpio defined in the board specific dts */
604 648
605 vio-supply = <&smps7_reg>; 649 vio-supply = <&smps7_reg>;
606 v2v1-supply = <&smps9_reg>; 650 v2v1-supply = <&smps9_reg>;
diff --git a/arch/arm/boot/dts/omap5-igep0050.dts b/arch/arm/boot/dts/omap5-igep0050.dts
index 46ecb1dd3b5c..f75ce02fb398 100644
--- a/arch/arm/boot/dts/omap5-igep0050.dts
+++ b/arch/arm/boot/dts/omap5-igep0050.dts
@@ -35,6 +35,22 @@
35 }; 35 };
36}; 36};
37 37
38/* LDO4 is VPP1 - ball AD9 */
39&ldo4_reg {
40 regulator-min-microvolt = <2000000>;
41 regulator-max-microvolt = <2000000>;
42};
43
44/*
45 * LDO7 is used for HDMI: VDDA_DSIPORTA - ball AA33, VDDA_DSIPORTC - ball AE33,
46 * VDDA_HDMI - ball AN25
47 */
48&ldo7_reg {
49 status = "okay";
50 regulator-min-microvolt = <1800000>;
51 regulator-max-microvolt = <1800000>;
52};
53
38&omap5_pmx_core { 54&omap5_pmx_core {
39 i2c4_pins: pinmux_i2c4_pins { 55 i2c4_pins: pinmux_i2c4_pins {
40 pinctrl-single,pins = < 56 pinctrl-single,pins = <
@@ -52,3 +68,13 @@
52 <&gpio7 3 0>; /* 195, SDA */ 68 <&gpio7 3 0>; /* 195, SDA */
53}; 69};
54 70
71&twl6040 {
72 ti,audpwron-gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio line 144 */
73};
74
75&twl6040_pins {
76 pinctrl-single,pins = <
77 OMAP5_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_144 */
78 OMAP5_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE6) /* perslimbus2_clock.gpio5_145 */
79 >;
80};
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 60b3fbb3bf07..a51e60518eb6 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -51,3 +51,13 @@
51 <&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */ 51 <&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */
52 <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */ 52 <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */
53}; 53};
54
55&twl6040 {
56 ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */
57};
58
59&twl6040_pins {
60 pinctrl-single,pins = <
61 OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */
62 >;
63};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
index a3601e4c0a2e..b844473601d2 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
@@ -136,6 +136,7 @@
136&gmac1 { 136&gmac1 {
137 status = "okay"; 137 status = "okay";
138 phy-mode = "rgmii"; 138 phy-mode = "rgmii";
139 phy-handle = <&phy1>;
139 140
140 snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>; 141 snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>;
141 snps,reset-active-low; 142 snps,reset-active-low;
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index ad8ba10764a3..d294e82447a2 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -24,18 +24,21 @@
24 compatible = "shared-dma-pool"; 24 compatible = "shared-dma-pool";
25 reg = <0x40000000 0x01000000>; 25 reg = <0x40000000 0x01000000>;
26 no-map; 26 no-map;
27 status = "disabled";
27 }; 28 };
28 29
29 gp1_reserved: rproc@41000000 { 30 gp1_reserved: rproc@41000000 {
30 compatible = "shared-dma-pool"; 31 compatible = "shared-dma-pool";
31 reg = <0x41000000 0x01000000>; 32 reg = <0x41000000 0x01000000>;
32 no-map; 33 no-map;
34 status = "disabled";
33 }; 35 };
34 36
35 audio_reserved: rproc@42000000 { 37 audio_reserved: rproc@42000000 {
36 compatible = "shared-dma-pool"; 38 compatible = "shared-dma-pool";
37 reg = <0x42000000 0x01000000>; 39 reg = <0x42000000 0x01000000>;
38 no-map; 40 no-map;
41 status = "disabled";
39 }; 42 };
40 43
41 dmu_reserved: rproc@43000000 { 44 dmu_reserved: rproc@43000000 {
diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts
index 68b479b8772c..73c133f5e79c 100644
--- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts
@@ -176,8 +176,6 @@
176}; 176};
177 177
178&reg_dc1sw { 178&reg_dc1sw {
179 regulator-min-microvolt = <3000000>;
180 regulator-max-microvolt = <3000000>;
181 regulator-name = "vcc-lcd"; 179 regulator-name = "vcc-lcd";
182}; 180};
183 181
diff --git a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
index 360adfb1e9ca..d6ad6196a768 100644
--- a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
@@ -135,8 +135,6 @@
135 135
136&reg_dc1sw { 136&reg_dc1sw {
137 regulator-name = "vcc-lcd-usb2"; 137 regulator-name = "vcc-lcd-usb2";
138 regulator-min-microvolt = <3000000>;
139 regulator-max-microvolt = <3000000>;
140}; 138};
141 139
142&reg_dc5ldo { 140&reg_dc5ldo {
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index 10f49ab5328e..47195e8690b4 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -82,6 +82,7 @@ CONFIG_TOUCHSCREEN_MMS114=y
82CONFIG_INPUT_MISC=y 82CONFIG_INPUT_MISC=y
83CONFIG_INPUT_MAX77693_HAPTIC=y 83CONFIG_INPUT_MAX77693_HAPTIC=y
84CONFIG_INPUT_MAX8997_HAPTIC=y 84CONFIG_INPUT_MAX8997_HAPTIC=y
85CONFIG_KEYBOARD_SAMSUNG=y
85CONFIG_SERIAL_8250=y 86CONFIG_SERIAL_8250=y
86CONFIG_SERIAL_SAMSUNG=y 87CONFIG_SERIAL_SAMSUNG=y
87CONFIG_SERIAL_SAMSUNG_CONSOLE=y 88CONFIG_SERIAL_SAMSUNG_CONSOLE=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 8f857564657f..8a5fff1b7f6f 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -264,6 +264,7 @@ CONFIG_KEYBOARD_TEGRA=y
264CONFIG_KEYBOARD_SPEAR=y 264CONFIG_KEYBOARD_SPEAR=y
265CONFIG_KEYBOARD_ST_KEYSCAN=y 265CONFIG_KEYBOARD_ST_KEYSCAN=y
266CONFIG_KEYBOARD_CROS_EC=m 266CONFIG_KEYBOARD_CROS_EC=m
267CONFIG_KEYBOARD_SAMSUNG=m
267CONFIG_MOUSE_PS2_ELANTECH=y 268CONFIG_MOUSE_PS2_ELANTECH=y
268CONFIG_MOUSE_CYAPA=m 269CONFIG_MOUSE_CYAPA=m
269CONFIG_MOUSE_ELAN_I2C=y 270CONFIG_MOUSE_ELAN_I2C=y
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
index aeddd28b3595..92fd2c8a9af0 100644
--- a/arch/arm/include/asm/pgtable-2level.h
+++ b/arch/arm/include/asm/pgtable-2level.h
@@ -193,6 +193,7 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
193 193
194#define pmd_large(pmd) (pmd_val(pmd) & 2) 194#define pmd_large(pmd) (pmd_val(pmd) & 2)
195#define pmd_bad(pmd) (pmd_val(pmd) & 2) 195#define pmd_bad(pmd) (pmd_val(pmd) & 2)
196#define pmd_present(pmd) (pmd_val(pmd))
196 197
197#define copy_pmd(pmdpd,pmdps) \ 198#define copy_pmd(pmdpd,pmdps) \
198 do { \ 199 do { \
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index fa70db7c714b..2a029bceaf2f 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -211,6 +211,7 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
211 : !!(pmd_val(pmd) & (val))) 211 : !!(pmd_val(pmd) & (val)))
212#define pmd_isclear(pmd, val) (!(pmd_val(pmd) & (val))) 212#define pmd_isclear(pmd, val) (!(pmd_val(pmd) & (val)))
213 213
214#define pmd_present(pmd) (pmd_isset((pmd), L_PMD_SECT_VALID))
214#define pmd_young(pmd) (pmd_isset((pmd), PMD_SECT_AF)) 215#define pmd_young(pmd) (pmd_isset((pmd), PMD_SECT_AF))
215#define pte_special(pte) (pte_isset((pte), L_PTE_SPECIAL)) 216#define pte_special(pte) (pte_isset((pte), L_PTE_SPECIAL))
216static inline pte_t pte_mkspecial(pte_t pte) 217static inline pte_t pte_mkspecial(pte_t pte)
@@ -249,10 +250,10 @@ PMD_BIT_FUNC(mkyoung, |= PMD_SECT_AF);
249#define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) 250#define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
250#define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 251#define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
251 252
252/* represent a notpresent pmd by zero, this is used by pmdp_invalidate */ 253/* represent a notpresent pmd by faulting entry, this is used by pmdp_invalidate */
253static inline pmd_t pmd_mknotpresent(pmd_t pmd) 254static inline pmd_t pmd_mknotpresent(pmd_t pmd)
254{ 255{
255 return __pmd(0); 256 return __pmd(pmd_val(pmd) & ~L_PMD_SECT_VALID);
256} 257}
257 258
258static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 259static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 348caabb7625..d62204060cbe 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -182,7 +182,6 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
182#define pgd_offset_k(addr) pgd_offset(&init_mm, addr) 182#define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
183 183
184#define pmd_none(pmd) (!pmd_val(pmd)) 184#define pmd_none(pmd) (!pmd_val(pmd))
185#define pmd_present(pmd) (pmd_val(pmd))
186 185
187static inline pte_t *pmd_page_vaddr(pmd_t pmd) 186static inline pte_t *pmd_page_vaddr(pmd_t pmd)
188{ 187{
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index df90bc59bfce..861521606c6d 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -486,7 +486,7 @@ static const char *ipi_types[NR_IPI] __tracepoint_string = {
486 486
487static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) 487static void smp_cross_call(const struct cpumask *target, unsigned int ipinr)
488{ 488{
489 trace_ipi_raise(target, ipi_types[ipinr]); 489 trace_ipi_raise_rcuidle(target, ipi_types[ipinr]);
490 __smp_cross_call(target, ipinr); 490 __smp_cross_call(target, ipinr);
491} 491}
492 492
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index e65aa7d11b20..20dcf6e904b2 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -61,7 +61,6 @@ config ARCH_EXYNOS4
61 select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210 61 select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210
62 select CPU_EXYNOS4210 62 select CPU_EXYNOS4210
63 select GIC_NON_BANKED 63 select GIC_NON_BANKED
64 select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
65 select MIGHT_HAVE_CACHE_L2X0 64 select MIGHT_HAVE_CACHE_L2X0
66 help 65 help
67 Samsung EXYNOS4 (Cortex-A9) SoC based systems 66 Samsung EXYNOS4 (Cortex-A9) SoC based systems
diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c
index a38b16b69923..b56de4b8cdf2 100644
--- a/arch/arm/mach-imx/mach-imx6ul.c
+++ b/arch/arm/mach-imx/mach-imx6ul.c
@@ -46,7 +46,7 @@ static int ksz8081_phy_fixup(struct phy_device *dev)
46static void __init imx6ul_enet_phy_init(void) 46static void __init imx6ul_enet_phy_init(void)
47{ 47{
48 if (IS_BUILTIN(CONFIG_PHYLIB)) 48 if (IS_BUILTIN(CONFIG_PHYLIB))
49 phy_register_fixup_for_uid(PHY_ID_KSZ8081, 0xffffffff, 49 phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK,
50 ksz8081_phy_fixup); 50 ksz8081_phy_fixup);
51} 51}
52 52
diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
index 5d7fb596bf4a..bf608441b357 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq-handler.S
+++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
@@ -43,8 +43,8 @@
43#define OTHERS_MASK (MODEM_IRQ_MASK | HOOK_SWITCH_MASK) 43#define OTHERS_MASK (MODEM_IRQ_MASK | HOOK_SWITCH_MASK)
44 44
45/* IRQ handler register bitmasks */ 45/* IRQ handler register bitmasks */
46#define DEFERRED_FIQ_MASK (0x1 << (INT_DEFERRED_FIQ % IH2_BASE)) 46#define DEFERRED_FIQ_MASK OMAP_IRQ_BIT(INT_DEFERRED_FIQ)
47#define GPIO_BANK1_MASK (0x1 << INT_GPIO_BANK1) 47#define GPIO_BANK1_MASK OMAP_IRQ_BIT(INT_GPIO_BANK1)
48 48
49/* Driver buffer byte offsets */ 49/* Driver buffer byte offsets */
50#define BUF_MASK (FIQ_MASK * 4) 50#define BUF_MASK (FIQ_MASK * 4)
@@ -110,7 +110,7 @@ ENTRY(qwerty_fiqin_start)
110 mov r8, #2 @ reset FIQ agreement 110 mov r8, #2 @ reset FIQ agreement
111 str r8, [r12, #IRQ_CONTROL_REG_OFFSET] 111 str r8, [r12, #IRQ_CONTROL_REG_OFFSET]
112 112
113 cmp r10, #INT_GPIO_BANK1 @ is it GPIO bank interrupt? 113 cmp r10, #(INT_GPIO_BANK1 - NR_IRQS_LEGACY) @ is it GPIO interrupt?
114 beq gpio @ yes - process it 114 beq gpio @ yes - process it
115 115
116 mov r8, #1 116 mov r8, #1
diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c
index d1f12095f315..ec760ae2f917 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq.c
+++ b/arch/arm/mach-omap1/ams-delta-fiq.c
@@ -109,7 +109,8 @@ void __init ams_delta_init_fiq(void)
109 * Since no set_type() method is provided by OMAP irq chip, 109 * Since no set_type() method is provided by OMAP irq chip,
110 * switch to edge triggered interrupt type manually. 110 * switch to edge triggered interrupt type manually.
111 */ 111 */
112 offset = IRQ_ILR0_REG_OFFSET + INT_DEFERRED_FIQ * 0x4; 112 offset = IRQ_ILR0_REG_OFFSET +
113 ((INT_DEFERRED_FIQ - NR_IRQS_LEGACY) & 0x1f) * 0x4;
113 val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1); 114 val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1);
114 omap_writel(val, DEFERRED_FIQ_IH_BASE + offset); 115 omap_writel(val, DEFERRED_FIQ_IH_BASE + offset);
115 116
@@ -149,7 +150,7 @@ void __init ams_delta_init_fiq(void)
149 /* 150 /*
150 * Redirect GPIO interrupts to FIQ 151 * Redirect GPIO interrupts to FIQ
151 */ 152 */
152 offset = IRQ_ILR0_REG_OFFSET + INT_GPIO_BANK1 * 0x4; 153 offset = IRQ_ILR0_REG_OFFSET + (INT_GPIO_BANK1 - NR_IRQS_LEGACY) * 0x4;
153 val = omap_readl(OMAP_IH1_BASE + offset) | 1; 154 val = omap_readl(OMAP_IH1_BASE + offset) | 1;
154 omap_writel(val, OMAP_IH1_BASE + offset); 155 omap_writel(val, OMAP_IH1_BASE + offset);
155} 156}
diff --git a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
index adb5e7649659..6dfc3e1210a3 100644
--- a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
+++ b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
@@ -14,6 +14,8 @@
14#ifndef __AMS_DELTA_FIQ_H 14#ifndef __AMS_DELTA_FIQ_H
15#define __AMS_DELTA_FIQ_H 15#define __AMS_DELTA_FIQ_H
16 16
17#include <mach/irqs.h>
18
17/* 19/*
18 * Interrupt number used for passing control from FIQ to IRQ. 20 * Interrupt number used for passing control from FIQ to IRQ.
19 * IRQ12, described as reserved, has been selected. 21 * IRQ12, described as reserved, has been selected.
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 0517f0c1581a..1a648e9dfaa0 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -17,6 +17,7 @@ config ARCH_OMAP3
17 select PM_OPP if PM 17 select PM_OPP if PM
18 select PM if CPU_IDLE 18 select PM if CPU_IDLE
19 select SOC_HAS_OMAP2_SDRC 19 select SOC_HAS_OMAP2_SDRC
20 select ARM_ERRATA_430973
20 21
21config ARCH_OMAP4 22config ARCH_OMAP4
22 bool "TI OMAP4" 23 bool "TI OMAP4"
@@ -36,6 +37,7 @@ config ARCH_OMAP4
36 select PM if CPU_IDLE 37 select PM if CPU_IDLE
37 select ARM_ERRATA_754322 38 select ARM_ERRATA_754322
38 select ARM_ERRATA_775420 39 select ARM_ERRATA_775420
40 select OMAP_INTERCONNECT
39 41
40config SOC_OMAP5 42config SOC_OMAP5
41 bool "TI OMAP5" 43 bool "TI OMAP5"
@@ -67,6 +69,8 @@ config SOC_AM43XX
67 select HAVE_ARM_SCU 69 select HAVE_ARM_SCU
68 select GENERIC_CLOCKEVENTS_BROADCAST 70 select GENERIC_CLOCKEVENTS_BROADCAST
69 select HAVE_ARM_TWD 71 select HAVE_ARM_TWD
72 select ARM_ERRATA_754322
73 select ARM_ERRATA_775420
70 74
71config SOC_DRA7XX 75config SOC_DRA7XX
72 bool "TI DRA7XX" 76 bool "TI DRA7XX"
@@ -240,4 +244,12 @@ endmenu
240 244
241endif 245endif
242 246
247config OMAP5_ERRATA_801819
248 bool "Errata 801819: An eviction from L1 data cache might stall indefinitely"
249 depends on SOC_OMAP5 || SOC_DRA7XX
250 help
251 A livelock can occur in the L2 cache arbitration that might prevent
252 a snoop from completing. Under certain conditions this can cause the
253 system to deadlock.
254
243endmenu 255endmenu
diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index af2851fbcdf0..bae263fba640 100644
--- a/arch/arm/mach-omap2/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
@@ -46,6 +46,7 @@
46 46
47#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109 47#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109
48#define OMAP5_MON_AMBA_IF_INDEX 0x108 48#define OMAP5_MON_AMBA_IF_INDEX 0x108
49#define OMAP5_DRA7_MON_SET_ACR_INDEX 0x107
49 50
50/* Secure PPA(Primary Protected Application) APIs */ 51/* Secure PPA(Primary Protected Application) APIs */
51#define OMAP4_PPA_L2_POR_INDEX 0x23 52#define OMAP4_PPA_L2_POR_INDEX 0x23
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index c625cc10d9f9..8cd1de914ee4 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -50,6 +50,39 @@ void __iomem *omap4_get_scu_base(void)
50 return scu_base; 50 return scu_base;
51} 51}
52 52
53#ifdef CONFIG_OMAP5_ERRATA_801819
54void omap5_erratum_workaround_801819(void)
55{
56 u32 acr, revidr;
57 u32 acr_mask;
58
59 /* REVIDR[3] indicates erratum fix available on silicon */
60 asm volatile ("mrc p15, 0, %0, c0, c0, 6" : "=r" (revidr));
61 if (revidr & (0x1 << 3))
62 return;
63
64 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
65 /*
66 * BIT(27) - Disables streaming. All write-allocate lines allocate in
67 * the L1 or L2 cache.
68 * BIT(25) - Disables streaming. All write-allocate lines allocate in
69 * the L1 cache.
70 */
71 acr_mask = (0x3 << 25) | (0x3 << 27);
72 /* do we already have it done.. if yes, skip expensive smc */
73 if ((acr & acr_mask) == acr_mask)
74 return;
75
76 acr |= acr_mask;
77 omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr);
78
79 pr_debug("%s: ARM erratum workaround 801819 applied on CPU%d\n",
80 __func__, smp_processor_id());
81}
82#else
83static inline void omap5_erratum_workaround_801819(void) { }
84#endif
85
53static void omap4_secondary_init(unsigned int cpu) 86static void omap4_secondary_init(unsigned int cpu)
54{ 87{
55 /* 88 /*
@@ -64,12 +97,15 @@ static void omap4_secondary_init(unsigned int cpu)
64 omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX, 97 omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
65 4, 0, 0, 0, 0, 0); 98 4, 0, 0, 0, 0, 0);
66 99
67 /* 100 if (soc_is_omap54xx() || soc_is_dra7xx()) {
68 * Configure the CNTFRQ register for the secondary cpu's which 101 /*
69 * indicates the frequency of the cpu local timers. 102 * Configure the CNTFRQ register for the secondary cpu's which
70 */ 103 * indicates the frequency of the cpu local timers.
71 if (soc_is_omap54xx() || soc_is_dra7xx()) 104 */
72 set_cntfreq(); 105 set_cntfreq();
106 /* Configure ACR to disable streaming WA for 801819 */
107 omap5_erratum_workaround_801819();
108 }
73 109
74 /* 110 /*
75 * Synchronise with the boot thread. 111 * Synchronise with the boot thread.
@@ -218,6 +254,8 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
218 254
219 if (cpu_is_omap446x()) 255 if (cpu_is_omap446x())
220 startup_addr = omap4460_secondary_startup; 256 startup_addr = omap4460_secondary_startup;
257 if (soc_is_dra74x() || soc_is_omap54xx())
258 omap5_erratum_workaround_801819();
221 259
222 /* 260 /*
223 * Write the address of secondary startup routine into the 261 * Write the address of secondary startup routine into the
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 78af6d8cf2e2..daf2753de7aa 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -186,8 +186,9 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
186 trace_state = (PWRDM_TRACE_STATES_FLAG | 186 trace_state = (PWRDM_TRACE_STATES_FLAG |
187 ((next & OMAP_POWERSTATE_MASK) << 8) | 187 ((next & OMAP_POWERSTATE_MASK) << 8) |
188 ((prev & OMAP_POWERSTATE_MASK) << 0)); 188 ((prev & OMAP_POWERSTATE_MASK) << 0));
189 trace_power_domain_target(pwrdm->name, trace_state, 189 trace_power_domain_target_rcuidle(pwrdm->name,
190 smp_processor_id()); 190 trace_state,
191 smp_processor_id());
191 } 192 }
192 break; 193 break;
193 default: 194 default:
@@ -523,8 +524,8 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
523 524
524 if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) { 525 if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
525 /* Trace the pwrdm desired target state */ 526 /* Trace the pwrdm desired target state */
526 trace_power_domain_target(pwrdm->name, pwrst, 527 trace_power_domain_target_rcuidle(pwrdm->name, pwrst,
527 smp_processor_id()); 528 smp_processor_id());
528 /* Program the pwrdm desired target state */ 529 /* Program the pwrdm desired target state */
529 ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst); 530 ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst);
530 } 531 }
diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
index 0ec2d00f4237..eb350a673133 100644
--- a/arch/arm/mach-omap2/powerdomains7xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -36,14 +36,7 @@ static struct powerdomain iva_7xx_pwrdm = {
36 .prcm_offs = DRA7XX_PRM_IVA_INST, 36 .prcm_offs = DRA7XX_PRM_IVA_INST,
37 .prcm_partition = DRA7XX_PRM_PARTITION, 37 .prcm_partition = DRA7XX_PRM_PARTITION,
38 .pwrsts = PWRSTS_OFF_ON, 38 .pwrsts = PWRSTS_OFF_ON,
39 .pwrsts_logic_ret = PWRSTS_OFF,
40 .banks = 4, 39 .banks = 4,
41 .pwrsts_mem_ret = {
42 [0] = PWRSTS_OFF_RET, /* hwa_mem */
43 [1] = PWRSTS_OFF_RET, /* sl2_mem */
44 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
45 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
46 },
47 .pwrsts_mem_on = { 40 .pwrsts_mem_on = {
48 [0] = PWRSTS_ON, /* hwa_mem */ 41 [0] = PWRSTS_ON, /* hwa_mem */
49 [1] = PWRSTS_ON, /* sl2_mem */ 42 [1] = PWRSTS_ON, /* sl2_mem */
@@ -76,12 +69,7 @@ static struct powerdomain ipu_7xx_pwrdm = {
76 .prcm_offs = DRA7XX_PRM_IPU_INST, 69 .prcm_offs = DRA7XX_PRM_IPU_INST,
77 .prcm_partition = DRA7XX_PRM_PARTITION, 70 .prcm_partition = DRA7XX_PRM_PARTITION,
78 .pwrsts = PWRSTS_OFF_ON, 71 .pwrsts = PWRSTS_OFF_ON,
79 .pwrsts_logic_ret = PWRSTS_OFF,
80 .banks = 2, 72 .banks = 2,
81 .pwrsts_mem_ret = {
82 [0] = PWRSTS_OFF_RET, /* aessmem */
83 [1] = PWRSTS_OFF_RET, /* periphmem */
84 },
85 .pwrsts_mem_on = { 73 .pwrsts_mem_on = {
86 [0] = PWRSTS_ON, /* aessmem */ 74 [0] = PWRSTS_ON, /* aessmem */
87 [1] = PWRSTS_ON, /* periphmem */ 75 [1] = PWRSTS_ON, /* periphmem */
@@ -95,11 +83,7 @@ static struct powerdomain dss_7xx_pwrdm = {
95 .prcm_offs = DRA7XX_PRM_DSS_INST, 83 .prcm_offs = DRA7XX_PRM_DSS_INST,
96 .prcm_partition = DRA7XX_PRM_PARTITION, 84 .prcm_partition = DRA7XX_PRM_PARTITION,
97 .pwrsts = PWRSTS_OFF_ON, 85 .pwrsts = PWRSTS_OFF_ON,
98 .pwrsts_logic_ret = PWRSTS_OFF,
99 .banks = 1, 86 .banks = 1,
100 .pwrsts_mem_ret = {
101 [0] = PWRSTS_OFF_RET, /* dss_mem */
102 },
103 .pwrsts_mem_on = { 87 .pwrsts_mem_on = {
104 [0] = PWRSTS_ON, /* dss_mem */ 88 [0] = PWRSTS_ON, /* dss_mem */
105 }, 89 },
@@ -111,13 +95,8 @@ static struct powerdomain l4per_7xx_pwrdm = {
111 .name = "l4per_pwrdm", 95 .name = "l4per_pwrdm",
112 .prcm_offs = DRA7XX_PRM_L4PER_INST, 96 .prcm_offs = DRA7XX_PRM_L4PER_INST,
113 .prcm_partition = DRA7XX_PRM_PARTITION, 97 .prcm_partition = DRA7XX_PRM_PARTITION,
114 .pwrsts = PWRSTS_RET_ON, 98 .pwrsts = PWRSTS_ON,
115 .pwrsts_logic_ret = PWRSTS_RET,
116 .banks = 2, 99 .banks = 2,
117 .pwrsts_mem_ret = {
118 [0] = PWRSTS_OFF_RET, /* nonretained_bank */
119 [1] = PWRSTS_OFF_RET, /* retained_bank */
120 },
121 .pwrsts_mem_on = { 100 .pwrsts_mem_on = {
122 [0] = PWRSTS_ON, /* nonretained_bank */ 101 [0] = PWRSTS_ON, /* nonretained_bank */
123 [1] = PWRSTS_ON, /* retained_bank */ 102 [1] = PWRSTS_ON, /* retained_bank */
@@ -132,9 +111,6 @@ static struct powerdomain gpu_7xx_pwrdm = {
132 .prcm_partition = DRA7XX_PRM_PARTITION, 111 .prcm_partition = DRA7XX_PRM_PARTITION,
133 .pwrsts = PWRSTS_OFF_ON, 112 .pwrsts = PWRSTS_OFF_ON,
134 .banks = 1, 113 .banks = 1,
135 .pwrsts_mem_ret = {
136 [0] = PWRSTS_OFF_RET, /* gpu_mem */
137 },
138 .pwrsts_mem_on = { 114 .pwrsts_mem_on = {
139 [0] = PWRSTS_ON, /* gpu_mem */ 115 [0] = PWRSTS_ON, /* gpu_mem */
140 }, 116 },
@@ -148,8 +124,6 @@ static struct powerdomain wkupaon_7xx_pwrdm = {
148 .prcm_partition = DRA7XX_PRM_PARTITION, 124 .prcm_partition = DRA7XX_PRM_PARTITION,
149 .pwrsts = PWRSTS_ON, 125 .pwrsts = PWRSTS_ON,
150 .banks = 1, 126 .banks = 1,
151 .pwrsts_mem_ret = {
152 },
153 .pwrsts_mem_on = { 127 .pwrsts_mem_on = {
154 [0] = PWRSTS_ON, /* wkup_bank */ 128 [0] = PWRSTS_ON, /* wkup_bank */
155 }, 129 },
@@ -161,15 +135,7 @@ static struct powerdomain core_7xx_pwrdm = {
161 .prcm_offs = DRA7XX_PRM_CORE_INST, 135 .prcm_offs = DRA7XX_PRM_CORE_INST,
162 .prcm_partition = DRA7XX_PRM_PARTITION, 136 .prcm_partition = DRA7XX_PRM_PARTITION,
163 .pwrsts = PWRSTS_ON, 137 .pwrsts = PWRSTS_ON,
164 .pwrsts_logic_ret = PWRSTS_RET,
165 .banks = 5, 138 .banks = 5,
166 .pwrsts_mem_ret = {
167 [0] = PWRSTS_OFF_RET, /* core_nret_bank */
168 [1] = PWRSTS_OFF_RET, /* core_ocmram */
169 [2] = PWRSTS_OFF_RET, /* core_other_bank */
170 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
171 [4] = PWRSTS_OFF_RET, /* ipu_unicache */
172 },
173 .pwrsts_mem_on = { 139 .pwrsts_mem_on = {
174 [0] = PWRSTS_ON, /* core_nret_bank */ 140 [0] = PWRSTS_ON, /* core_nret_bank */
175 [1] = PWRSTS_ON, /* core_ocmram */ 141 [1] = PWRSTS_ON, /* core_ocmram */
@@ -226,11 +192,7 @@ static struct powerdomain vpe_7xx_pwrdm = {
226 .prcm_offs = DRA7XX_PRM_VPE_INST, 192 .prcm_offs = DRA7XX_PRM_VPE_INST,
227 .prcm_partition = DRA7XX_PRM_PARTITION, 193 .prcm_partition = DRA7XX_PRM_PARTITION,
228 .pwrsts = PWRSTS_OFF_ON, 194 .pwrsts = PWRSTS_OFF_ON,
229 .pwrsts_logic_ret = PWRSTS_OFF,
230 .banks = 1, 195 .banks = 1,
231 .pwrsts_mem_ret = {
232 [0] = PWRSTS_OFF_RET, /* vpe_bank */
233 },
234 .pwrsts_mem_on = { 196 .pwrsts_mem_on = {
235 [0] = PWRSTS_ON, /* vpe_bank */ 197 [0] = PWRSTS_ON, /* vpe_bank */
236 }, 198 },
@@ -260,14 +222,8 @@ static struct powerdomain l3init_7xx_pwrdm = {
260 .name = "l3init_pwrdm", 222 .name = "l3init_pwrdm",
261 .prcm_offs = DRA7XX_PRM_L3INIT_INST, 223 .prcm_offs = DRA7XX_PRM_L3INIT_INST,
262 .prcm_partition = DRA7XX_PRM_PARTITION, 224 .prcm_partition = DRA7XX_PRM_PARTITION,
263 .pwrsts = PWRSTS_RET_ON, 225 .pwrsts = PWRSTS_ON,
264 .pwrsts_logic_ret = PWRSTS_RET,
265 .banks = 3, 226 .banks = 3,
266 .pwrsts_mem_ret = {
267 [0] = PWRSTS_OFF_RET, /* gmac_bank */
268 [1] = PWRSTS_OFF_RET, /* l3init_bank1 */
269 [2] = PWRSTS_OFF_RET, /* l3init_bank2 */
270 },
271 .pwrsts_mem_on = { 227 .pwrsts_mem_on = {
272 [0] = PWRSTS_ON, /* gmac_bank */ 228 [0] = PWRSTS_ON, /* gmac_bank */
273 [1] = PWRSTS_ON, /* l3init_bank1 */ 229 [1] = PWRSTS_ON, /* l3init_bank1 */
@@ -283,9 +239,6 @@ static struct powerdomain eve3_7xx_pwrdm = {
283 .prcm_partition = DRA7XX_PRM_PARTITION, 239 .prcm_partition = DRA7XX_PRM_PARTITION,
284 .pwrsts = PWRSTS_OFF_ON, 240 .pwrsts = PWRSTS_OFF_ON,
285 .banks = 1, 241 .banks = 1,
286 .pwrsts_mem_ret = {
287 [0] = PWRSTS_OFF_RET, /* eve3_bank */
288 },
289 .pwrsts_mem_on = { 242 .pwrsts_mem_on = {
290 [0] = PWRSTS_ON, /* eve3_bank */ 243 [0] = PWRSTS_ON, /* eve3_bank */
291 }, 244 },
@@ -299,9 +252,6 @@ static struct powerdomain emu_7xx_pwrdm = {
299 .prcm_partition = DRA7XX_PRM_PARTITION, 252 .prcm_partition = DRA7XX_PRM_PARTITION,
300 .pwrsts = PWRSTS_OFF_ON, 253 .pwrsts = PWRSTS_OFF_ON,
301 .banks = 1, 254 .banks = 1,
302 .pwrsts_mem_ret = {
303 [0] = PWRSTS_OFF_RET, /* emu_bank */
304 },
305 .pwrsts_mem_on = { 255 .pwrsts_mem_on = {
306 [0] = PWRSTS_ON, /* emu_bank */ 256 [0] = PWRSTS_ON, /* emu_bank */
307 }, 257 },
@@ -314,11 +264,6 @@ static struct powerdomain dsp2_7xx_pwrdm = {
314 .prcm_partition = DRA7XX_PRM_PARTITION, 264 .prcm_partition = DRA7XX_PRM_PARTITION,
315 .pwrsts = PWRSTS_OFF_ON, 265 .pwrsts = PWRSTS_OFF_ON,
316 .banks = 3, 266 .banks = 3,
317 .pwrsts_mem_ret = {
318 [0] = PWRSTS_OFF_RET, /* dsp2_edma */
319 [1] = PWRSTS_OFF_RET, /* dsp2_l1 */
320 [2] = PWRSTS_OFF_RET, /* dsp2_l2 */
321 },
322 .pwrsts_mem_on = { 267 .pwrsts_mem_on = {
323 [0] = PWRSTS_ON, /* dsp2_edma */ 268 [0] = PWRSTS_ON, /* dsp2_edma */
324 [1] = PWRSTS_ON, /* dsp2_l1 */ 269 [1] = PWRSTS_ON, /* dsp2_l1 */
@@ -334,11 +279,6 @@ static struct powerdomain dsp1_7xx_pwrdm = {
334 .prcm_partition = DRA7XX_PRM_PARTITION, 279 .prcm_partition = DRA7XX_PRM_PARTITION,
335 .pwrsts = PWRSTS_OFF_ON, 280 .pwrsts = PWRSTS_OFF_ON,
336 .banks = 3, 281 .banks = 3,
337 .pwrsts_mem_ret = {
338 [0] = PWRSTS_OFF_RET, /* dsp1_edma */
339 [1] = PWRSTS_OFF_RET, /* dsp1_l1 */
340 [2] = PWRSTS_OFF_RET, /* dsp1_l2 */
341 },
342 .pwrsts_mem_on = { 282 .pwrsts_mem_on = {
343 [0] = PWRSTS_ON, /* dsp1_edma */ 283 [0] = PWRSTS_ON, /* dsp1_edma */
344 [1] = PWRSTS_ON, /* dsp1_l1 */ 284 [1] = PWRSTS_ON, /* dsp1_l1 */
@@ -354,9 +294,6 @@ static struct powerdomain cam_7xx_pwrdm = {
354 .prcm_partition = DRA7XX_PRM_PARTITION, 294 .prcm_partition = DRA7XX_PRM_PARTITION,
355 .pwrsts = PWRSTS_OFF_ON, 295 .pwrsts = PWRSTS_OFF_ON,
356 .banks = 1, 296 .banks = 1,
357 .pwrsts_mem_ret = {
358 [0] = PWRSTS_OFF_RET, /* vip_bank */
359 },
360 .pwrsts_mem_on = { 297 .pwrsts_mem_on = {
361 [0] = PWRSTS_ON, /* vip_bank */ 298 [0] = PWRSTS_ON, /* vip_bank */
362 }, 299 },
@@ -370,9 +307,6 @@ static struct powerdomain eve4_7xx_pwrdm = {
370 .prcm_partition = DRA7XX_PRM_PARTITION, 307 .prcm_partition = DRA7XX_PRM_PARTITION,
371 .pwrsts = PWRSTS_OFF_ON, 308 .pwrsts = PWRSTS_OFF_ON,
372 .banks = 1, 309 .banks = 1,
373 .pwrsts_mem_ret = {
374 [0] = PWRSTS_OFF_RET, /* eve4_bank */
375 },
376 .pwrsts_mem_on = { 310 .pwrsts_mem_on = {
377 [0] = PWRSTS_ON, /* eve4_bank */ 311 [0] = PWRSTS_ON, /* eve4_bank */
378 }, 312 },
@@ -386,9 +320,6 @@ static struct powerdomain eve2_7xx_pwrdm = {
386 .prcm_partition = DRA7XX_PRM_PARTITION, 320 .prcm_partition = DRA7XX_PRM_PARTITION,
387 .pwrsts = PWRSTS_OFF_ON, 321 .pwrsts = PWRSTS_OFF_ON,
388 .banks = 1, 322 .banks = 1,
389 .pwrsts_mem_ret = {
390 [0] = PWRSTS_OFF_RET, /* eve2_bank */
391 },
392 .pwrsts_mem_on = { 323 .pwrsts_mem_on = {
393 [0] = PWRSTS_ON, /* eve2_bank */ 324 [0] = PWRSTS_ON, /* eve2_bank */
394 }, 325 },
@@ -402,9 +333,6 @@ static struct powerdomain eve1_7xx_pwrdm = {
402 .prcm_partition = DRA7XX_PRM_PARTITION, 333 .prcm_partition = DRA7XX_PRM_PARTITION,
403 .pwrsts = PWRSTS_OFF_ON, 334 .pwrsts = PWRSTS_OFF_ON,
404 .banks = 1, 335 .banks = 1,
405 .pwrsts_mem_ret = {
406 [0] = PWRSTS_OFF_RET, /* eve1_bank */
407 },
408 .pwrsts_mem_on = { 336 .pwrsts_mem_on = {
409 [0] = PWRSTS_ON, /* eve1_bank */ 337 [0] = PWRSTS_ON, /* eve1_bank */
410 }, 338 },
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 5b385bb8aff9..cb9497a20fb3 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -496,8 +496,7 @@ void __init omap_init_time(void)
496 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon", 496 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
497 2, "timer_sys_ck", NULL, false); 497 2, "timer_sys_ck", NULL, false);
498 498
499 if (of_have_populated_dt()) 499 clocksource_probe();
500 clocksource_probe();
501} 500}
502 501
503#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX) 502#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
@@ -505,6 +504,8 @@ void __init omap3_secure_sync32k_timer_init(void)
505{ 504{
506 __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure", 505 __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
507 2, "timer_sys_ck", NULL, false); 506 2, "timer_sys_ck", NULL, false);
507
508 clocksource_probe();
508} 509}
509#endif /* CONFIG_ARCH_OMAP3 */ 510#endif /* CONFIG_ARCH_OMAP3 */
510 511
@@ -513,6 +514,8 @@ void __init omap3_gptimer_timer_init(void)
513{ 514{
514 __omap_sync32k_timer_init(2, "timer_sys_ck", NULL, 515 __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
515 1, "timer_sys_ck", "ti,timer-alwon", true); 516 1, "timer_sys_ck", "ti,timer-alwon", true);
517
518 clocksource_probe();
516} 519}
517#endif 520#endif
518 521
diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c
index 5766ce2be32b..8409cab3f760 100644
--- a/arch/arm/mach-vexpress/spc.c
+++ b/arch/arm/mach-vexpress/spc.c
@@ -547,7 +547,7 @@ static struct clk *ve_spc_clk_register(struct device *cpu_dev)
547 547
548 init.name = dev_name(cpu_dev); 548 init.name = dev_name(cpu_dev);
549 init.ops = &clk_spc_ops; 549 init.ops = &clk_spc_ops;
550 init.flags = CLK_IS_ROOT | CLK_GET_RATE_NOCACHE; 550 init.flags = CLK_GET_RATE_NOCACHE;
551 init.num_parents = 0; 551 init.num_parents = 0;
552 552
553 return devm_clk_register(cpu_dev, &spc->hw); 553 return devm_clk_register(cpu_dev, &spc->hw);
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 84baa16f4c0b..e93aa6734147 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -68,7 +68,7 @@
68#include <linux/platform_data/asoc-s3c.h> 68#include <linux/platform_data/asoc-s3c.h>
69#include <linux/platform_data/spi-s3c64xx.h> 69#include <linux/platform_data/spi-s3c64xx.h>
70 70
71static u64 samsung_device_dma_mask = DMA_BIT_MASK(32); 71#define samsung_device_dma_mask (*((u64[]) { DMA_BIT_MASK(32) }))
72 72
73/* AC97 */ 73/* AC97 */
74#ifdef CONFIG_CPU_S3C2440 74#ifdef CONFIG_CPU_S3C2440
diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi
index 3a4e9a2ab313..fbafa24cd533 100644
--- a/arch/arm64/boot/dts/lg/lg1312.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1312.dtsi
@@ -125,7 +125,7 @@
125 #size-cells = <1>; 125 #size-cells = <1>;
126 #interrupts-cells = <3>; 126 #interrupts-cells = <3>;
127 127
128 compatible = "arm,amba-bus"; 128 compatible = "simple-bus";
129 interrupt-parent = <&gic>; 129 interrupt-parent = <&gic>;
130 ranges; 130 ranges;
131 131
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 46f325a143b0..d7f8e06910bc 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -163,7 +163,7 @@
163 }; 163 };
164 164
165 amba { 165 amba {
166 compatible = "arm,amba-bus"; 166 compatible = "simple-bus";
167 #address-cells = <2>; 167 #address-cells = <2>;
168 #size-cells = <2>; 168 #size-cells = <2>;
169 ranges; 169 ranges;
diff --git a/arch/arm64/include/asm/kgdb.h b/arch/arm64/include/asm/kgdb.h
index f69f69c8120c..da84645525b9 100644
--- a/arch/arm64/include/asm/kgdb.h
+++ b/arch/arm64/include/asm/kgdb.h
@@ -38,25 +38,54 @@ extern int kgdb_fault_expected;
38#endif /* !__ASSEMBLY__ */ 38#endif /* !__ASSEMBLY__ */
39 39
40/* 40/*
41 * gdb is expecting the following registers layout. 41 * gdb remote procotol (well most versions of it) expects the following
42 * register layout.
42 * 43 *
43 * General purpose regs: 44 * General purpose regs:
44 * r0-r30: 64 bit 45 * r0-r30: 64 bit
45 * sp,pc : 64 bit 46 * sp,pc : 64 bit
46 * pstate : 64 bit 47 * pstate : 32 bit
47 * Total: 34 48 * Total: 33 + 1
48 * FPU regs: 49 * FPU regs:
49 * f0-f31: 128 bit 50 * f0-f31: 128 bit
50 * Total: 32
51 * Extra regs
52 * fpsr & fpcr: 32 bit 51 * fpsr & fpcr: 32 bit
53 * Total: 2 52 * Total: 32 + 2
54 * 53 *
54 * To expand a little on the "most versions of it"... when the gdb remote
55 * protocol for AArch64 was developed it depended on a statement in the
56 * Architecture Reference Manual that claimed "SPSR_ELx is a 32-bit register".
57 * and, as a result, allocated only 32-bits for the PSTATE in the remote
58 * protocol. In fact this statement is still present in ARM DDI 0487A.i.
59 *
60 * Unfortunately "is a 32-bit register" has a very special meaning for
61 * system registers. It means that "the upper bits, bits[63:32], are
62 * RES0.". RES0 is heavily used in the ARM architecture documents as a
63 * way to leave space for future architecture changes. So to translate a
64 * little for people who don't spend their spare time reading ARM architecture
65 * manuals, what "is a 32-bit register" actually means in this context is
66 * "is a 64-bit register but one with no meaning allocated to any of the
67 * upper 32-bits... *yet*".
68 *
69 * Perhaps then we should not be surprised that this has led to some
70 * confusion. Specifically a patch, influenced by the above translation,
71 * that extended PSTATE to 64-bit was accepted into gdb-7.7 but the patch
72 * was reverted in gdb-7.8.1 and all later releases, when this was
73 * discovered to be an undocumented protocol change.
74 *
75 * So... it is *not* wrong for us to only allocate 32-bits to PSTATE
76 * here even though the kernel itself allocates 64-bits for the same
77 * state. That is because this bit of code tells the kernel how the gdb
78 * remote protocol (well most versions of it) describes the register state.
79 *
80 * Note that if you are using one of the versions of gdb that supports
81 * the gdb-7.7 version of the protocol you cannot use kgdb directly
82 * without providing a custom register description (gdb can load new
83 * protocol descriptions at runtime).
55 */ 84 */
56 85
57#define _GP_REGS 34 86#define _GP_REGS 33
58#define _FP_REGS 32 87#define _FP_REGS 32
59#define _EXTRA_REGS 2 88#define _EXTRA_REGS 3
60/* 89/*
61 * general purpose registers size in bytes. 90 * general purpose registers size in bytes.
62 * pstate is only 4 bytes. subtract 4 bytes 91 * pstate is only 4 bytes. subtract 4 bytes
diff --git a/arch/arm64/include/asm/spinlock.h b/arch/arm64/include/asm/spinlock.h
index fc9682bfe002..e875a5a551d7 100644
--- a/arch/arm64/include/asm/spinlock.h
+++ b/arch/arm64/include/asm/spinlock.h
@@ -30,22 +30,53 @@ static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
30{ 30{
31 unsigned int tmp; 31 unsigned int tmp;
32 arch_spinlock_t lockval; 32 arch_spinlock_t lockval;
33 u32 owner;
34
35 /*
36 * Ensure prior spin_lock operations to other locks have completed
37 * on this CPU before we test whether "lock" is locked.
38 */
39 smp_mb();
40 owner = READ_ONCE(lock->owner) << 16;
33 41
34 asm volatile( 42 asm volatile(
35" sevl\n" 43" sevl\n"
36"1: wfe\n" 44"1: wfe\n"
37"2: ldaxr %w0, %2\n" 45"2: ldaxr %w0, %2\n"
46 /* Is the lock free? */
38" eor %w1, %w0, %w0, ror #16\n" 47" eor %w1, %w0, %w0, ror #16\n"
39" cbnz %w1, 1b\n" 48" cbz %w1, 3f\n"
49 /* Lock taken -- has there been a subsequent unlock->lock transition? */
50" eor %w1, %w3, %w0, lsl #16\n"
51" cbz %w1, 1b\n"
52 /*
53 * The owner has been updated, so there was an unlock->lock
54 * transition that we missed. That means we can rely on the
55 * store-release of the unlock operation paired with the
56 * load-acquire of the lock operation to publish any of our
57 * previous stores to the new lock owner and therefore don't
58 * need to bother with the writeback below.
59 */
60" b 4f\n"
61"3:\n"
62 /*
63 * Serialise against any concurrent lockers by writing back the
64 * unlocked lock value
65 */
40 ARM64_LSE_ATOMIC_INSN( 66 ARM64_LSE_ATOMIC_INSN(
41 /* LL/SC */ 67 /* LL/SC */
42" stxr %w1, %w0, %2\n" 68" stxr %w1, %w0, %2\n"
43" cbnz %w1, 2b\n", /* Serialise against any concurrent lockers */
44 /* LSE atomics */
45" nop\n" 69" nop\n"
46" nop\n") 70" nop\n",
71 /* LSE atomics */
72" mov %w1, %w0\n"
73" cas %w0, %w0, %2\n"
74" eor %w1, %w1, %w0\n")
75 /* Somebody else wrote to the lock, GOTO 10 and reload the value */
76" cbnz %w1, 2b\n"
77"4:"
47 : "=&r" (lockval), "=&r" (tmp), "+Q" (*lock) 78 : "=&r" (lockval), "=&r" (tmp), "+Q" (*lock)
48 : 79 : "r" (owner)
49 : "memory"); 80 : "memory");
50} 81}
51 82
@@ -148,6 +179,7 @@ static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
148 179
149static inline int arch_spin_is_locked(arch_spinlock_t *lock) 180static inline int arch_spin_is_locked(arch_spinlock_t *lock)
150{ 181{
182 smp_mb(); /* See arch_spin_unlock_wait */
151 return !arch_spin_value_unlocked(READ_ONCE(*lock)); 183 return !arch_spin_value_unlocked(READ_ONCE(*lock));
152} 184}
153 185
diff --git a/arch/arm64/kernel/kgdb.c b/arch/arm64/kernel/kgdb.c
index b67531a13136..b5f063e5eff7 100644
--- a/arch/arm64/kernel/kgdb.c
+++ b/arch/arm64/kernel/kgdb.c
@@ -58,7 +58,17 @@ struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = {
58 { "x30", 8, offsetof(struct pt_regs, regs[30])}, 58 { "x30", 8, offsetof(struct pt_regs, regs[30])},
59 { "sp", 8, offsetof(struct pt_regs, sp)}, 59 { "sp", 8, offsetof(struct pt_regs, sp)},
60 { "pc", 8, offsetof(struct pt_regs, pc)}, 60 { "pc", 8, offsetof(struct pt_regs, pc)},
61 { "pstate", 8, offsetof(struct pt_regs, pstate)}, 61 /*
62 * struct pt_regs thinks PSTATE is 64-bits wide but gdb remote
63 * protocol disagrees. Therefore we must extract only the lower
64 * 32-bits. Look for the big comment in asm/kgdb.h for more
65 * detail.
66 */
67 { "pstate", 4, offsetof(struct pt_regs, pstate)
68#ifdef CONFIG_CPU_BIG_ENDIAN
69 + 4
70#endif
71 },
62 { "v0", 16, -1 }, 72 { "v0", 16, -1 },
63 { "v1", 16, -1 }, 73 { "v1", 16, -1 },
64 { "v2", 16, -1 }, 74 { "v2", 16, -1 },
@@ -128,6 +138,8 @@ sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *task)
128 memset((char *)gdb_regs, 0, NUMREGBYTES); 138 memset((char *)gdb_regs, 0, NUMREGBYTES);
129 thread_regs = task_pt_regs(task); 139 thread_regs = task_pt_regs(task);
130 memcpy((void *)gdb_regs, (void *)thread_regs->regs, GP_REG_BYTES); 140 memcpy((void *)gdb_regs, (void *)thread_regs->regs, GP_REG_BYTES);
141 /* Special case for PSTATE (check comments in asm/kgdb.h for details) */
142 dbg_get_reg(33, gdb_regs + GP_REG_BYTES, thread_regs);
131} 143}
132 144
133void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long pc) 145void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long pc)
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index f7cf463107df..2a43012616b7 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -64,8 +64,7 @@ static void dump_mem(const char *lvl, const char *str, unsigned long bottom,
64 64
65 /* 65 /*
66 * We need to switch to kernel mode so that we can use __get_user 66 * We need to switch to kernel mode so that we can use __get_user
67 * to safely read from kernel space. Note that we now dump the 67 * to safely read from kernel space.
68 * code first, just in case the backtrace kills us.
69 */ 68 */
70 fs = get_fs(); 69 fs = get_fs();
71 set_fs(KERNEL_DS); 70 set_fs(KERNEL_DS);
@@ -111,21 +110,12 @@ static void dump_backtrace_entry(unsigned long where)
111 print_ip_sym(where); 110 print_ip_sym(where);
112} 111}
113 112
114static void dump_instr(const char *lvl, struct pt_regs *regs) 113static void __dump_instr(const char *lvl, struct pt_regs *regs)
115{ 114{
116 unsigned long addr = instruction_pointer(regs); 115 unsigned long addr = instruction_pointer(regs);
117 mm_segment_t fs;
118 char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str; 116 char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
119 int i; 117 int i;
120 118
121 /*
122 * We need to switch to kernel mode so that we can use __get_user
123 * to safely read from kernel space. Note that we now dump the
124 * code first, just in case the backtrace kills us.
125 */
126 fs = get_fs();
127 set_fs(KERNEL_DS);
128
129 for (i = -4; i < 1; i++) { 119 for (i = -4; i < 1; i++) {
130 unsigned int val, bad; 120 unsigned int val, bad;
131 121
@@ -139,8 +129,18 @@ static void dump_instr(const char *lvl, struct pt_regs *regs)
139 } 129 }
140 } 130 }
141 printk("%sCode: %s\n", lvl, str); 131 printk("%sCode: %s\n", lvl, str);
132}
142 133
143 set_fs(fs); 134static void dump_instr(const char *lvl, struct pt_regs *regs)
135{
136 if (!user_mode(regs)) {
137 mm_segment_t fs = get_fs();
138 set_fs(KERNEL_DS);
139 __dump_instr(lvl, regs);
140 set_fs(fs);
141 } else {
142 __dump_instr(lvl, regs);
143 }
144} 144}
145 145
146static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk) 146static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index 5954881a35ac..013e2cbe7924 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -109,7 +109,7 @@ int ptep_set_access_flags(struct vm_area_struct *vma,
109 * PTE_RDONLY is cleared by default in the asm below, so set it in 109 * PTE_RDONLY is cleared by default in the asm below, so set it in
110 * back if necessary (read-only or clean PTE). 110 * back if necessary (read-only or clean PTE).
111 */ 111 */
112 if (!pte_write(entry) || !dirty) 112 if (!pte_write(entry) || !pte_sw_dirty(entry))
113 pte_val(entry) |= PTE_RDONLY; 113 pte_val(entry) |= PTE_RDONLY;
114 114
115 /* 115 /*
@@ -441,7 +441,7 @@ static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs)
441 return 1; 441 return 1;
442} 442}
443 443
444static struct fault_info { 444static const struct fault_info {
445 int (*fn)(unsigned long addr, unsigned int esr, struct pt_regs *regs); 445 int (*fn)(unsigned long addr, unsigned int esr, struct pt_regs *regs);
446 int sig; 446 int sig;
447 int code; 447 int code;
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 6733ac575da4..36a391d289aa 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -74,7 +74,7 @@
74#define KVM_GUEST_KUSEG 0x00000000UL 74#define KVM_GUEST_KUSEG 0x00000000UL
75#define KVM_GUEST_KSEG0 0x40000000UL 75#define KVM_GUEST_KSEG0 0x40000000UL
76#define KVM_GUEST_KSEG23 0x60000000UL 76#define KVM_GUEST_KSEG23 0x60000000UL
77#define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000) 77#define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0xe0000000)
78#define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) 78#define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
79 79
80#define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0) 80#define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
@@ -338,6 +338,7 @@ struct kvm_mips_tlb {
338#define KVM_MIPS_GUEST_TLB_SIZE 64 338#define KVM_MIPS_GUEST_TLB_SIZE 64
339struct kvm_vcpu_arch { 339struct kvm_vcpu_arch {
340 void *host_ebase, *guest_ebase; 340 void *host_ebase, *guest_ebase;
341 int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu);
341 unsigned long host_stack; 342 unsigned long host_stack;
342 unsigned long host_gp; 343 unsigned long host_gp;
343 344
diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c
index 396df6eb0a12..645c8a1982a7 100644
--- a/arch/mips/kvm/emulate.c
+++ b/arch/mips/kvm/emulate.c
@@ -1636,6 +1636,7 @@ enum emulation_result kvm_mips_emulate_cache(uint32_t inst, uint32_t *opc,
1636 if (index < 0) { 1636 if (index < 0) {
1637 vcpu->arch.host_cp0_entryhi = (va & VPN2_MASK); 1637 vcpu->arch.host_cp0_entryhi = (va & VPN2_MASK);
1638 vcpu->arch.host_cp0_badvaddr = va; 1638 vcpu->arch.host_cp0_badvaddr = va;
1639 vcpu->arch.pc = curr_pc;
1639 er = kvm_mips_emulate_tlbmiss_ld(cause, NULL, run, 1640 er = kvm_mips_emulate_tlbmiss_ld(cause, NULL, run,
1640 vcpu); 1641 vcpu);
1641 preempt_enable(); 1642 preempt_enable();
@@ -1647,6 +1648,8 @@ enum emulation_result kvm_mips_emulate_cache(uint32_t inst, uint32_t *opc,
1647 * invalid exception to the guest 1648 * invalid exception to the guest
1648 */ 1649 */
1649 if (!TLB_IS_VALID(*tlb, va)) { 1650 if (!TLB_IS_VALID(*tlb, va)) {
1651 vcpu->arch.host_cp0_badvaddr = va;
1652 vcpu->arch.pc = curr_pc;
1650 er = kvm_mips_emulate_tlbinv_ld(cause, NULL, 1653 er = kvm_mips_emulate_tlbinv_ld(cause, NULL,
1651 run, vcpu); 1654 run, vcpu);
1652 preempt_enable(); 1655 preempt_enable();
@@ -1666,7 +1669,7 @@ enum emulation_result kvm_mips_emulate_cache(uint32_t inst, uint32_t *opc,
1666 cache, op, base, arch->gprs[base], offset); 1669 cache, op, base, arch->gprs[base], offset);
1667 er = EMULATE_FAIL; 1670 er = EMULATE_FAIL;
1668 preempt_enable(); 1671 preempt_enable();
1669 goto dont_update_pc; 1672 goto done;
1670 1673
1671 } 1674 }
1672 1675
@@ -1694,16 +1697,20 @@ skip_fault:
1694 kvm_err("NO-OP CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n", 1697 kvm_err("NO-OP CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1695 cache, op, base, arch->gprs[base], offset); 1698 cache, op, base, arch->gprs[base], offset);
1696 er = EMULATE_FAIL; 1699 er = EMULATE_FAIL;
1697 preempt_enable();
1698 goto dont_update_pc;
1699 } 1700 }
1700 1701
1701 preempt_enable(); 1702 preempt_enable();
1703done:
1704 /* Rollback PC only if emulation was unsuccessful */
1705 if (er == EMULATE_FAIL)
1706 vcpu->arch.pc = curr_pc;
1702 1707
1703dont_update_pc: 1708dont_update_pc:
1704 /* Rollback PC */ 1709 /*
1705 vcpu->arch.pc = curr_pc; 1710 * This is for exceptions whose emulation updates the PC, so do not
1706done: 1711 * overwrite the PC under any circumstances
1712 */
1713
1707 return er; 1714 return er;
1708} 1715}
1709 1716
diff --git a/arch/mips/kvm/interrupt.h b/arch/mips/kvm/interrupt.h
index 4ab4bdfad703..2143884709e4 100644
--- a/arch/mips/kvm/interrupt.h
+++ b/arch/mips/kvm/interrupt.h
@@ -28,6 +28,7 @@
28#define MIPS_EXC_MAX 12 28#define MIPS_EXC_MAX 12
29/* XXXSL More to follow */ 29/* XXXSL More to follow */
30 30
31extern char __kvm_mips_vcpu_run_end[];
31extern char mips32_exception[], mips32_exceptionEnd[]; 32extern char mips32_exception[], mips32_exceptionEnd[];
32extern char mips32_GuestException[], mips32_GuestExceptionEnd[]; 33extern char mips32_GuestException[], mips32_GuestExceptionEnd[];
33 34
diff --git a/arch/mips/kvm/locore.S b/arch/mips/kvm/locore.S
index 3ef03009de5f..828fcfc1cd7f 100644
--- a/arch/mips/kvm/locore.S
+++ b/arch/mips/kvm/locore.S
@@ -202,6 +202,7 @@ FEXPORT(__kvm_mips_load_k0k1)
202 202
203 /* Jump to guest */ 203 /* Jump to guest */
204 eret 204 eret
205EXPORT(__kvm_mips_vcpu_run_end)
205 206
206VECTOR(MIPSX(exception), unknown) 207VECTOR(MIPSX(exception), unknown)
207/* Find out what mode we came from and jump to the proper handler. */ 208/* Find out what mode we came from and jump to the proper handler. */
diff --git a/arch/mips/kvm/mips.c b/arch/mips/kvm/mips.c
index dc052fb5c7a2..44da5259f390 100644
--- a/arch/mips/kvm/mips.c
+++ b/arch/mips/kvm/mips.c
@@ -315,6 +315,15 @@ struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
315 memcpy(gebase + offset, mips32_GuestException, 315 memcpy(gebase + offset, mips32_GuestException,
316 mips32_GuestExceptionEnd - mips32_GuestException); 316 mips32_GuestExceptionEnd - mips32_GuestException);
317 317
318#ifdef MODULE
319 offset += mips32_GuestExceptionEnd - mips32_GuestException;
320 memcpy(gebase + offset, (char *)__kvm_mips_vcpu_run,
321 __kvm_mips_vcpu_run_end - (char *)__kvm_mips_vcpu_run);
322 vcpu->arch.vcpu_run = gebase + offset;
323#else
324 vcpu->arch.vcpu_run = __kvm_mips_vcpu_run;
325#endif
326
318 /* Invalidate the icache for these ranges */ 327 /* Invalidate the icache for these ranges */
319 local_flush_icache_range((unsigned long)gebase, 328 local_flush_icache_range((unsigned long)gebase,
320 (unsigned long)gebase + ALIGN(size, PAGE_SIZE)); 329 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
@@ -404,7 +413,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
404 /* Disable hardware page table walking while in guest */ 413 /* Disable hardware page table walking while in guest */
405 htw_stop(); 414 htw_stop();
406 415
407 r = __kvm_mips_vcpu_run(run, vcpu); 416 r = vcpu->arch.vcpu_run(run, vcpu);
408 417
409 /* Re-enable HTW before enabling interrupts */ 418 /* Re-enable HTW before enabling interrupts */
410 htw_start(); 419 htw_start();
diff --git a/arch/powerpc/include/asm/nohash/64/pgalloc.h b/arch/powerpc/include/asm/nohash/64/pgalloc.h
index 0c12a3bfe2ab..069369f6414b 100644
--- a/arch/powerpc/include/asm/nohash/64/pgalloc.h
+++ b/arch/powerpc/include/asm/nohash/64/pgalloc.h
@@ -172,7 +172,7 @@ static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
172 172
173static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) 173static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
174{ 174{
175 pte_fragment_fre((unsigned long *)pte, 1); 175 pte_fragment_free((unsigned long *)pte, 1);
176} 176}
177 177
178static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage) 178static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index ccd2037c797f..6ee4b72cda42 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -719,7 +719,7 @@ unsigned char ibm_architecture_vec[] = {
719 * must match by the macro below. Update the definition if 719 * must match by the macro below. Update the definition if
720 * the structure layout changes. 720 * the structure layout changes.
721 */ 721 */
722#define IBM_ARCH_VEC_NRCORES_OFFSET 125 722#define IBM_ARCH_VEC_NRCORES_OFFSET 133
723 W(NR_CPUS), /* number of cores supported */ 723 W(NR_CPUS), /* number of cores supported */
724 0, 724 0,
725 0, 725 0,
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 30a03c03fe73..060b140f03c6 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -377,7 +377,7 @@ static int fpr_get(struct task_struct *target, const struct user_regset *regset,
377 377
378#else 378#else
379 BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) != 379 BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) !=
380 offsetof(struct thread_fp_state, fpr[32][0])); 380 offsetof(struct thread_fp_state, fpr[32]));
381 381
382 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, 382 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
383 &target->thread.fp_state, 0, -1); 383 &target->thread.fp_state, 0, -1);
@@ -405,7 +405,7 @@ static int fpr_set(struct task_struct *target, const struct user_regset *regset,
405 return 0; 405 return 0;
406#else 406#else
407 BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) != 407 BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) !=
408 offsetof(struct thread_fp_state, fpr[32][0])); 408 offsetof(struct thread_fp_state, fpr[32]));
409 409
410 return user_regset_copyin(&pos, &count, &kbuf, &ubuf, 410 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
411 &target->thread.fp_state, 0, -1); 411 &target->thread.fp_state, 0, -1);
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index d873f6507f72..40e05e7f43de 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -550,7 +550,11 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
550 } 550 }
551 } 551 }
552 /* This works for all page sizes, and for 256M and 1T segments */ 552 /* This works for all page sizes, and for 256M and 1T segments */
553 *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT; 553 if (cpu_has_feature(CPU_FTR_ARCH_300))
554 *ssize = hpte_r >> HPTE_R_3_0_SSIZE_SHIFT;
555 else
556 *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT;
557
554 shift = mmu_psize_defs[size].shift; 558 shift = mmu_psize_defs[size].shift;
555 559
556 avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm); 560 avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm);
diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
index 0fdaf93a3e09..54efba2fd66e 100644
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
@@ -117,7 +117,7 @@ static inline void _tlbie_va(unsigned long va, unsigned long pid,
117 */ 117 */
118void radix__local_flush_tlb_mm(struct mm_struct *mm) 118void radix__local_flush_tlb_mm(struct mm_struct *mm)
119{ 119{
120 unsigned int pid; 120 unsigned long pid;
121 121
122 preempt_disable(); 122 preempt_disable();
123 pid = mm->context.id; 123 pid = mm->context.id;
@@ -130,7 +130,7 @@ EXPORT_SYMBOL(radix__local_flush_tlb_mm);
130void radix___local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr, 130void radix___local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
131 unsigned long ap, int nid) 131 unsigned long ap, int nid)
132{ 132{
133 unsigned int pid; 133 unsigned long pid;
134 134
135 preempt_disable(); 135 preempt_disable();
136 pid = mm ? mm->context.id : 0; 136 pid = mm ? mm->context.id : 0;
@@ -160,7 +160,7 @@ static int mm_is_core_local(struct mm_struct *mm)
160 160
161void radix__flush_tlb_mm(struct mm_struct *mm) 161void radix__flush_tlb_mm(struct mm_struct *mm)
162{ 162{
163 unsigned int pid; 163 unsigned long pid;
164 164
165 preempt_disable(); 165 preempt_disable();
166 pid = mm->context.id; 166 pid = mm->context.id;
@@ -185,7 +185,7 @@ EXPORT_SYMBOL(radix__flush_tlb_mm);
185void radix___flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr, 185void radix___flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
186 unsigned long ap, int nid) 186 unsigned long ap, int nid)
187{ 187{
188 unsigned int pid; 188 unsigned long pid;
189 189
190 preempt_disable(); 190 preempt_disable();
191 pid = mm ? mm->context.id : 0; 191 pid = mm ? mm->context.id : 0;
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index c50ea76ba66c..6081fbd75330 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -221,7 +221,7 @@ static bool soc_has_mclk_mux0_canin(void)
221/* convenience wrappers around the common clk API */ 221/* convenience wrappers around the common clk API */
222static inline struct clk *mpc512x_clk_fixed(const char *name, int rate) 222static inline struct clk *mpc512x_clk_fixed(const char *name, int rate)
223{ 223{
224 return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); 224 return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
225} 225}
226 226
227static inline struct clk *mpc512x_clk_factor( 227static inline struct clk *mpc512x_clk_factor(
diff --git a/arch/powerpc/platforms/cell/spufs/coredump.c b/arch/powerpc/platforms/cell/spufs/coredump.c
index 84fb984f29c1..85c85eb3e245 100644
--- a/arch/powerpc/platforms/cell/spufs/coredump.c
+++ b/arch/powerpc/platforms/cell/spufs/coredump.c
@@ -172,7 +172,7 @@ static int spufs_arch_write_note(struct spu_context *ctx, int i,
172 if (rc < 0) 172 if (rc < 0)
173 goto out; 173 goto out;
174 174
175 skip = roundup(cprm->file->f_pos - total + sz, 4) - cprm->file->f_pos; 175 skip = roundup(cprm->pos - total + sz, 4) - cprm->pos;
176 if (!dump_skip(cprm, skip)) 176 if (!dump_skip(cprm, skip))
177 goto Eio; 177 goto Eio;
178out: 178out:
diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c
index b7dfc1359d01..3e8865b187de 100644
--- a/arch/powerpc/platforms/pseries/iommu.c
+++ b/arch/powerpc/platforms/pseries/iommu.c
@@ -927,7 +927,7 @@ static int query_ddw(struct pci_dev *dev, const u32 *ddw_avail,
927 dn = pci_device_to_OF_node(dev); 927 dn = pci_device_to_OF_node(dev);
928 pdn = PCI_DN(dn); 928 pdn = PCI_DN(dn);
929 buid = pdn->phb->buid; 929 buid = pdn->phb->buid;
930 cfg_addr = (pdn->busno << 8) | pdn->devfn; 930 cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8));
931 931
932 ret = rtas_call(ddw_avail[0], 3, 5, (u32 *)query, 932 ret = rtas_call(ddw_avail[0], 3, 5, (u32 *)query,
933 cfg_addr, BUID_HI(buid), BUID_LO(buid)); 933 cfg_addr, BUID_HI(buid), BUID_LO(buid));
@@ -956,7 +956,7 @@ static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail,
956 dn = pci_device_to_OF_node(dev); 956 dn = pci_device_to_OF_node(dev);
957 pdn = PCI_DN(dn); 957 pdn = PCI_DN(dn);
958 buid = pdn->phb->buid; 958 buid = pdn->phb->buid;
959 cfg_addr = (pdn->busno << 8) | pdn->devfn; 959 cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8));
960 960
961 do { 961 do {
962 /* extra outputs are LIOBN and dma-addr (hi, lo) */ 962 /* extra outputs are LIOBN and dma-addr (hi, lo) */
diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h
index 37b9017c6a96..ac82e8eb936d 100644
--- a/arch/s390/include/asm/kvm_host.h
+++ b/arch/s390/include/asm/kvm_host.h
@@ -245,6 +245,7 @@ struct kvm_vcpu_stat {
245 u32 exit_stop_request; 245 u32 exit_stop_request;
246 u32 exit_validity; 246 u32 exit_validity;
247 u32 exit_instruction; 247 u32 exit_instruction;
248 u32 exit_pei;
248 u32 halt_successful_poll; 249 u32 halt_successful_poll;
249 u32 halt_attempted_poll; 250 u32 halt_attempted_poll;
250 u32 halt_poll_invalid; 251 u32 halt_poll_invalid;
diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c
index 2e6b54e4d3f9..252157181302 100644
--- a/arch/s390/kvm/intercept.c
+++ b/arch/s390/kvm/intercept.c
@@ -341,6 +341,8 @@ static int handle_mvpg_pei(struct kvm_vcpu *vcpu)
341 341
342static int handle_partial_execution(struct kvm_vcpu *vcpu) 342static int handle_partial_execution(struct kvm_vcpu *vcpu)
343{ 343{
344 vcpu->stat.exit_pei++;
345
344 if (vcpu->arch.sie_block->ipa == 0xb254) /* MVPG */ 346 if (vcpu->arch.sie_block->ipa == 0xb254) /* MVPG */
345 return handle_mvpg_pei(vcpu); 347 return handle_mvpg_pei(vcpu);
346 if (vcpu->arch.sie_block->ipa >> 8 == 0xae) /* SIGP */ 348 if (vcpu->arch.sie_block->ipa >> 8 == 0xae) /* SIGP */
diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c
index 6d8ec3ac9dd8..43f2a2b80490 100644
--- a/arch/s390/kvm/kvm-s390.c
+++ b/arch/s390/kvm/kvm-s390.c
@@ -61,6 +61,7 @@ struct kvm_stats_debugfs_item debugfs_entries[] = {
61 { "exit_external_request", VCPU_STAT(exit_external_request) }, 61 { "exit_external_request", VCPU_STAT(exit_external_request) },
62 { "exit_external_interrupt", VCPU_STAT(exit_external_interrupt) }, 62 { "exit_external_interrupt", VCPU_STAT(exit_external_interrupt) },
63 { "exit_instruction", VCPU_STAT(exit_instruction) }, 63 { "exit_instruction", VCPU_STAT(exit_instruction) },
64 { "exit_pei", VCPU_STAT(exit_pei) },
64 { "exit_program_interruption", VCPU_STAT(exit_program_interruption) }, 65 { "exit_program_interruption", VCPU_STAT(exit_program_interruption) },
65 { "exit_instr_and_program_int", VCPU_STAT(exit_instr_and_program) }, 66 { "exit_instr_and_program_int", VCPU_STAT(exit_instr_and_program) },
66 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 67 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
@@ -657,7 +658,7 @@ static int kvm_s390_set_processor(struct kvm *kvm, struct kvm_device_attr *attr)
657 kvm->arch.model.cpuid = proc->cpuid; 658 kvm->arch.model.cpuid = proc->cpuid;
658 lowest_ibc = sclp.ibc >> 16 & 0xfff; 659 lowest_ibc = sclp.ibc >> 16 & 0xfff;
659 unblocked_ibc = sclp.ibc & 0xfff; 660 unblocked_ibc = sclp.ibc & 0xfff;
660 if (lowest_ibc) { 661 if (lowest_ibc && proc->ibc) {
661 if (proc->ibc > unblocked_ibc) 662 if (proc->ibc > unblocked_ibc)
662 kvm->arch.model.ibc = unblocked_ibc; 663 kvm->arch.model.ibc = unblocked_ibc;
663 else if (proc->ibc < lowest_ibc) 664 else if (proc->ibc < lowest_ibc)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 0a7b885964ba..d9a94da0c29f 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -2439,6 +2439,15 @@ config PCI_CNB20LE_QUIRK
2439 2439
2440source "drivers/pci/Kconfig" 2440source "drivers/pci/Kconfig"
2441 2441
2442config ISA_BUS
2443 bool "ISA-style bus support on modern systems" if EXPERT
2444 select ISA_BUS_API
2445 help
2446 Enables ISA-style drivers on modern systems. This is necessary to
2447 support PC/104 devices on X86_64 platforms.
2448
2449 If unsure, say N.
2450
2442# x86_64 have no ISA slots, but can have ISA-style DMA. 2451# x86_64 have no ISA slots, but can have ISA-style DMA.
2443config ISA_DMA_API 2452config ISA_DMA_API
2444 bool "ISA-style DMA support" if (X86_64 && EXPERT) 2453 bool "ISA-style DMA support" if (X86_64 && EXPERT)
diff --git a/arch/x86/boot/Makefile b/arch/x86/boot/Makefile
index 700a9c6e6159..be8e688fa0d4 100644
--- a/arch/x86/boot/Makefile
+++ b/arch/x86/boot/Makefile
@@ -162,6 +162,9 @@ isoimage: $(obj)/bzImage
162 for i in lib lib64 share end ; do \ 162 for i in lib lib64 share end ; do \
163 if [ -f /usr/$$i/syslinux/isolinux.bin ] ; then \ 163 if [ -f /usr/$$i/syslinux/isolinux.bin ] ; then \
164 cp /usr/$$i/syslinux/isolinux.bin $(obj)/isoimage ; \ 164 cp /usr/$$i/syslinux/isolinux.bin $(obj)/isoimage ; \
165 if [ -f /usr/$$i/syslinux/ldlinux.c32 ]; then \
166 cp /usr/$$i/syslinux/ldlinux.c32 $(obj)/isoimage ; \
167 fi ; \
165 break ; \ 168 break ; \
166 fi ; \ 169 fi ; \
167 if [ $$i = end ] ; then exit 1 ; fi ; \ 170 if [ $$i = end ] ; then exit 1 ; fi ; \
diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c
index 99c4bab123cd..e30eef4f29a6 100644
--- a/arch/x86/events/intel/rapl.c
+++ b/arch/x86/events/intel/rapl.c
@@ -714,7 +714,7 @@ static void cleanup_rapl_pmus(void)
714 int i; 714 int i;
715 715
716 for (i = 0; i < rapl_pmus->maxpkg; i++) 716 for (i = 0; i < rapl_pmus->maxpkg; i++)
717 kfree(rapl_pmus->pmus + i); 717 kfree(rapl_pmus->pmus[i]);
718 kfree(rapl_pmus); 718 kfree(rapl_pmus);
719} 719}
720 720
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index b2625867ebd1..874e8bd64d1d 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -2868,27 +2868,10 @@ static struct intel_uncore_type bdx_uncore_cbox = {
2868 .format_group = &hswep_uncore_cbox_format_group, 2868 .format_group = &hswep_uncore_cbox_format_group,
2869}; 2869};
2870 2870
2871static struct intel_uncore_type bdx_uncore_sbox = {
2872 .name = "sbox",
2873 .num_counters = 4,
2874 .num_boxes = 4,
2875 .perf_ctr_bits = 48,
2876 .event_ctl = HSWEP_S0_MSR_PMON_CTL0,
2877 .perf_ctr = HSWEP_S0_MSR_PMON_CTR0,
2878 .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK,
2879 .box_ctl = HSWEP_S0_MSR_PMON_BOX_CTL,
2880 .msr_offset = HSWEP_SBOX_MSR_OFFSET,
2881 .ops = &hswep_uncore_sbox_msr_ops,
2882 .format_group = &hswep_uncore_sbox_format_group,
2883};
2884
2885#define BDX_MSR_UNCORE_SBOX 3
2886
2887static struct intel_uncore_type *bdx_msr_uncores[] = { 2871static struct intel_uncore_type *bdx_msr_uncores[] = {
2888 &bdx_uncore_ubox, 2872 &bdx_uncore_ubox,
2889 &bdx_uncore_cbox, 2873 &bdx_uncore_cbox,
2890 &hswep_uncore_pcu, 2874 &hswep_uncore_pcu,
2891 &bdx_uncore_sbox,
2892 NULL, 2875 NULL,
2893}; 2876};
2894 2877
@@ -2897,10 +2880,6 @@ void bdx_uncore_cpu_init(void)
2897 if (bdx_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) 2880 if (bdx_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
2898 bdx_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores; 2881 bdx_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
2899 uncore_msr_uncores = bdx_msr_uncores; 2882 uncore_msr_uncores = bdx_msr_uncores;
2900
2901 /* BDX-DE doesn't have SBOX */
2902 if (boot_cpu_data.x86_model == 86)
2903 uncore_msr_uncores[BDX_MSR_UNCORE_SBOX] = NULL;
2904} 2883}
2905 2884
2906static struct intel_uncore_type bdx_uncore_ha = { 2885static struct intel_uncore_type bdx_uncore_ha = {
diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
new file mode 100644
index 000000000000..6999f7d01a0d
--- /dev/null
+++ b/arch/x86/include/asm/intel-family.h
@@ -0,0 +1,68 @@
1#ifndef _ASM_X86_INTEL_FAMILY_H
2#define _ASM_X86_INTEL_FAMILY_H
3
4/*
5 * "Big Core" Processors (Branded as Core, Xeon, etc...)
6 *
7 * The "_X" parts are generally the EP and EX Xeons, or the
8 * "Extreme" ones, like Broadwell-E.
9 *
10 * Things ending in "2" are usually because we have no better
11 * name for them. There's no processor called "WESTMERE2".
12 */
13
14#define INTEL_FAM6_CORE_YONAH 0x0E
15#define INTEL_FAM6_CORE2_MEROM 0x0F
16#define INTEL_FAM6_CORE2_MEROM_L 0x16
17#define INTEL_FAM6_CORE2_PENRYN 0x17
18#define INTEL_FAM6_CORE2_DUNNINGTON 0x1D
19
20#define INTEL_FAM6_NEHALEM 0x1E
21#define INTEL_FAM6_NEHALEM_EP 0x1A
22#define INTEL_FAM6_NEHALEM_EX 0x2E
23#define INTEL_FAM6_WESTMERE 0x25
24#define INTEL_FAM6_WESTMERE2 0x1F
25#define INTEL_FAM6_WESTMERE_EP 0x2C
26#define INTEL_FAM6_WESTMERE_EX 0x2F
27
28#define INTEL_FAM6_SANDYBRIDGE 0x2A
29#define INTEL_FAM6_SANDYBRIDGE_X 0x2D
30#define INTEL_FAM6_IVYBRIDGE 0x3A
31#define INTEL_FAM6_IVYBRIDGE_X 0x3E
32
33#define INTEL_FAM6_HASWELL_CORE 0x3C
34#define INTEL_FAM6_HASWELL_X 0x3F
35#define INTEL_FAM6_HASWELL_ULT 0x45
36#define INTEL_FAM6_HASWELL_GT3E 0x46
37
38#define INTEL_FAM6_BROADWELL_CORE 0x3D
39#define INTEL_FAM6_BROADWELL_XEON_D 0x56
40#define INTEL_FAM6_BROADWELL_GT3E 0x47
41#define INTEL_FAM6_BROADWELL_X 0x4F
42
43#define INTEL_FAM6_SKYLAKE_MOBILE 0x4E
44#define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E
45#define INTEL_FAM6_SKYLAKE_X 0x55
46#define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
47#define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E
48
49/* "Small Core" Processors (Atom) */
50
51#define INTEL_FAM6_ATOM_PINEVIEW 0x1C
52#define INTEL_FAM6_ATOM_LINCROFT 0x26
53#define INTEL_FAM6_ATOM_PENWELL 0x27
54#define INTEL_FAM6_ATOM_CLOVERVIEW 0x35
55#define INTEL_FAM6_ATOM_CEDARVIEW 0x36
56#define INTEL_FAM6_ATOM_SILVERMONT1 0x37 /* BayTrail/BYT / Valleyview */
57#define INTEL_FAM6_ATOM_SILVERMONT2 0x4D /* Avaton/Rangely */
58#define INTEL_FAM6_ATOM_AIRMONT 0x4C /* CherryTrail / Braswell */
59#define INTEL_FAM6_ATOM_MERRIFIELD1 0x4A /* Tangier */
60#define INTEL_FAM6_ATOM_MERRIFIELD2 0x5A /* Annidale */
61#define INTEL_FAM6_ATOM_GOLDMONT 0x5C
62#define INTEL_FAM6_ATOM_DENVERTON 0x5F /* Goldmont Microserver */
63
64/* Xeon Phi */
65
66#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */
67
68#endif /* _ASM_X86_INTEL_FAMILY_H */
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index e0fbe7e70dc1..69e62862b622 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -27,6 +27,7 @@
27#include <linux/irqbypass.h> 27#include <linux/irqbypass.h>
28#include <linux/hyperv.h> 28#include <linux/hyperv.h>
29 29
30#include <asm/apic.h>
30#include <asm/pvclock-abi.h> 31#include <asm/pvclock-abi.h>
31#include <asm/desc.h> 32#include <asm/desc.h>
32#include <asm/mtrr.h> 33#include <asm/mtrr.h>
@@ -1368,4 +1369,14 @@ static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu)
1368 1369
1369static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} 1370static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
1370 1371
1372static inline int kvm_cpu_get_apicid(int mps_cpu)
1373{
1374#ifdef CONFIG_X86_LOCAL_APIC
1375 return __default_cpu_present_to_apicid(mps_cpu);
1376#else
1377 WARN_ON_ONCE(1);
1378 return BAD_APICID;
1379#endif
1380}
1381
1371#endif /* _ASM_X86_KVM_HOST_H */ 1382#endif /* _ASM_X86_KVM_HOST_H */
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 7dc1d8fef7fd..b5fee97813cd 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -122,7 +122,7 @@ notrace static inline void native_write_msr(unsigned int msr,
122 "2:\n" 122 "2:\n"
123 _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_wrmsr_unsafe) 123 _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_wrmsr_unsafe)
124 : : "c" (msr), "a"(low), "d" (high) : "memory"); 124 : : "c" (msr), "a"(low), "d" (high) : "memory");
125 if (msr_tracepoint_active(__tracepoint_read_msr)) 125 if (msr_tracepoint_active(__tracepoint_write_msr))
126 do_trace_write_msr(msr, ((u64)high << 32 | low), 0); 126 do_trace_write_msr(msr, ((u64)high << 32 | low), 0);
127} 127}
128 128
@@ -141,7 +141,7 @@ notrace static inline int native_write_msr_safe(unsigned int msr,
141 : "c" (msr), "0" (low), "d" (high), 141 : "c" (msr), "0" (low), "d" (high),
142 [fault] "i" (-EIO) 142 [fault] "i" (-EIO)
143 : "memory"); 143 : "memory");
144 if (msr_tracepoint_active(__tracepoint_read_msr)) 144 if (msr_tracepoint_active(__tracepoint_write_msr))
145 do_trace_write_msr(msr, ((u64)high << 32 | low), err); 145 do_trace_write_msr(msr, ((u64)high << 32 | low), err);
146 return err; 146 return err;
147} 147}
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 84e33ff5a6d5..446702ed99dc 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -2588,8 +2588,8 @@ static struct resource * __init ioapic_setup_resources(void)
2588 res[num].flags = IORESOURCE_MEM | IORESOURCE_BUSY; 2588 res[num].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2589 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); 2589 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2590 mem += IOAPIC_RESOURCE_NAME_SIZE; 2590 mem += IOAPIC_RESOURCE_NAME_SIZE;
2591 ioapics[i].iomem_res = &res[num];
2591 num++; 2592 num++;
2592 ioapics[i].iomem_res = res;
2593 } 2593 }
2594 2594
2595 ioapic_resources = res; 2595 ioapic_resources = res;
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index c343a54bed39..f5c69d8974e1 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -674,14 +674,14 @@ static void init_amd_bd(struct cpuinfo_x86 *c)
674 u64 value; 674 u64 value;
675 675
676 /* re-enable TopologyExtensions if switched off by BIOS */ 676 /* re-enable TopologyExtensions if switched off by BIOS */
677 if ((c->x86_model >= 0x10) && (c->x86_model <= 0x1f) && 677 if ((c->x86_model >= 0x10) && (c->x86_model <= 0x6f) &&
678 !cpu_has(c, X86_FEATURE_TOPOEXT)) { 678 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
679 679
680 if (msr_set_bit(0xc0011005, 54) > 0) { 680 if (msr_set_bit(0xc0011005, 54) > 0) {
681 rdmsrl(0xc0011005, value); 681 rdmsrl(0xc0011005, value);
682 if (value & BIT_64(54)) { 682 if (value & BIT_64(54)) {
683 set_cpu_cap(c, X86_FEATURE_TOPOEXT); 683 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
684 pr_info(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); 684 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
685 } 685 }
686 } 686 }
687 } 687 }
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index d1590486204a..00f03d82e69a 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -96,6 +96,12 @@ static inline void cond_local_irq_disable(struct pt_regs *regs)
96 local_irq_disable(); 96 local_irq_disable();
97} 97}
98 98
99/*
100 * In IST context, we explicitly disable preemption. This serves two
101 * purposes: it makes it much less likely that we would accidentally
102 * schedule in IST context and it will force a warning if we somehow
103 * manage to schedule by accident.
104 */
99void ist_enter(struct pt_regs *regs) 105void ist_enter(struct pt_regs *regs)
100{ 106{
101 if (user_mode(regs)) { 107 if (user_mode(regs)) {
@@ -110,13 +116,7 @@ void ist_enter(struct pt_regs *regs)
110 rcu_nmi_enter(); 116 rcu_nmi_enter();
111 } 117 }
112 118
113 /* 119 preempt_disable();
114 * We are atomic because we're on the IST stack; or we're on
115 * x86_32, in which case we still shouldn't schedule; or we're
116 * on x86_64 and entered from user mode, in which case we're
117 * still atomic unless ist_begin_non_atomic is called.
118 */
119 preempt_count_add(HARDIRQ_OFFSET);
120 120
121 /* This code is a bit fragile. Test it. */ 121 /* This code is a bit fragile. Test it. */
122 RCU_LOCKDEP_WARN(!rcu_is_watching(), "ist_enter didn't work"); 122 RCU_LOCKDEP_WARN(!rcu_is_watching(), "ist_enter didn't work");
@@ -124,7 +124,7 @@ void ist_enter(struct pt_regs *regs)
124 124
125void ist_exit(struct pt_regs *regs) 125void ist_exit(struct pt_regs *regs)
126{ 126{
127 preempt_count_sub(HARDIRQ_OFFSET); 127 preempt_enable_no_resched();
128 128
129 if (!user_mode(regs)) 129 if (!user_mode(regs))
130 rcu_nmi_exit(); 130 rcu_nmi_exit();
@@ -155,7 +155,7 @@ void ist_begin_non_atomic(struct pt_regs *regs)
155 BUG_ON((unsigned long)(current_top_of_stack() - 155 BUG_ON((unsigned long)(current_top_of_stack() -
156 current_stack_pointer()) >= THREAD_SIZE); 156 current_stack_pointer()) >= THREAD_SIZE);
157 157
158 preempt_count_sub(HARDIRQ_OFFSET); 158 preempt_enable_no_resched();
159} 159}
160 160
161/** 161/**
@@ -165,7 +165,7 @@ void ist_begin_non_atomic(struct pt_regs *regs)
165 */ 165 */
166void ist_end_non_atomic(void) 166void ist_end_non_atomic(void)
167{ 167{
168 preempt_count_add(HARDIRQ_OFFSET); 168 preempt_disable();
169} 169}
170 170
171static nokprobe_inline int 171static nokprobe_inline int
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 1163e8173e5a..16ef31b87452 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -238,7 +238,9 @@ module_param(nested, int, S_IRUGO);
238 238
239/* enable / disable AVIC */ 239/* enable / disable AVIC */
240static int avic; 240static int avic;
241#ifdef CONFIG_X86_LOCAL_APIC
241module_param(avic, int, S_IRUGO); 242module_param(avic, int, S_IRUGO);
243#endif
242 244
243static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 245static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
244static void svm_flush_tlb(struct kvm_vcpu *vcpu); 246static void svm_flush_tlb(struct kvm_vcpu *vcpu);
@@ -981,11 +983,14 @@ static __init int svm_hardware_setup(void)
981 } else 983 } else
982 kvm_disable_tdp(); 984 kvm_disable_tdp();
983 985
984 if (avic && (!npt_enabled || !boot_cpu_has(X86_FEATURE_AVIC))) 986 if (avic) {
985 avic = false; 987 if (!npt_enabled ||
986 988 !boot_cpu_has(X86_FEATURE_AVIC) ||
987 if (avic) 989 !IS_ENABLED(CONFIG_X86_LOCAL_APIC))
988 pr_info("AVIC enabled\n"); 990 avic = false;
991 else
992 pr_info("AVIC enabled\n");
993 }
989 994
990 return 0; 995 return 0;
991 996
@@ -1324,7 +1329,7 @@ free_avic:
1324static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run) 1329static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1325{ 1330{
1326 u64 entry; 1331 u64 entry;
1327 int h_physical_id = __default_cpu_present_to_apicid(vcpu->cpu); 1332 int h_physical_id = kvm_cpu_get_apicid(vcpu->cpu);
1328 struct vcpu_svm *svm = to_svm(vcpu); 1333 struct vcpu_svm *svm = to_svm(vcpu);
1329 1334
1330 if (!kvm_vcpu_apicv_active(vcpu)) 1335 if (!kvm_vcpu_apicv_active(vcpu))
@@ -1349,7 +1354,7 @@ static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1349{ 1354{
1350 u64 entry; 1355 u64 entry;
1351 /* ID = 0xff (broadcast), ID > 0xff (reserved) */ 1356 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1352 int h_physical_id = __default_cpu_present_to_apicid(cpu); 1357 int h_physical_id = kvm_cpu_get_apicid(cpu);
1353 struct vcpu_svm *svm = to_svm(vcpu); 1358 struct vcpu_svm *svm = to_svm(vcpu);
1354 1359
1355 if (!kvm_vcpu_apicv_active(vcpu)) 1360 if (!kvm_vcpu_apicv_active(vcpu))
@@ -4236,7 +4241,7 @@ static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
4236 4241
4237 if (avic_vcpu_is_running(vcpu)) 4242 if (avic_vcpu_is_running(vcpu))
4238 wrmsrl(SVM_AVIC_DOORBELL, 4243 wrmsrl(SVM_AVIC_DOORBELL,
4239 __default_cpu_present_to_apicid(vcpu->cpu)); 4244 kvm_cpu_get_apicid(vcpu->cpu));
4240 else 4245 else
4241 kvm_vcpu_wake_up(vcpu); 4246 kvm_vcpu_wake_up(vcpu);
4242} 4247}
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index fb93010beaa4..003618e324ce 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -2072,7 +2072,8 @@ static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2072 unsigned int dest; 2072 unsigned int dest;
2073 2073
2074 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 2074 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2075 !irq_remapping_cap(IRQ_POSTING_CAP)) 2075 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2076 !kvm_vcpu_apicv_active(vcpu))
2076 return; 2077 return;
2077 2078
2078 do { 2079 do {
@@ -2180,7 +2181,8 @@ static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2180 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 2181 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2181 2182
2182 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 2183 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2183 !irq_remapping_cap(IRQ_POSTING_CAP)) 2184 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2185 !kvm_vcpu_apicv_active(vcpu))
2184 return; 2186 return;
2185 2187
2186 /* Set SN when the vCPU is preempted */ 2188 /* Set SN when the vCPU is preempted */
@@ -10714,7 +10716,8 @@ static int vmx_pre_block(struct kvm_vcpu *vcpu)
10714 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 10716 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10715 10717
10716 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 10718 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10717 !irq_remapping_cap(IRQ_POSTING_CAP)) 10719 !irq_remapping_cap(IRQ_POSTING_CAP) ||
10720 !kvm_vcpu_apicv_active(vcpu))
10718 return 0; 10721 return 0;
10719 10722
10720 vcpu->pre_pcpu = vcpu->cpu; 10723 vcpu->pre_pcpu = vcpu->cpu;
@@ -10780,7 +10783,8 @@ static void vmx_post_block(struct kvm_vcpu *vcpu)
10780 unsigned long flags; 10783 unsigned long flags;
10781 10784
10782 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 10785 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10783 !irq_remapping_cap(IRQ_POSTING_CAP)) 10786 !irq_remapping_cap(IRQ_POSTING_CAP) ||
10787 !kvm_vcpu_apicv_active(vcpu))
10784 return; 10788 return;
10785 10789
10786 do { 10790 do {
@@ -10833,7 +10837,8 @@ static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10833 int idx, ret = -EINVAL; 10837 int idx, ret = -EINVAL;
10834 10838
10835 if (!kvm_arch_has_assigned_device(kvm) || 10839 if (!kvm_arch_has_assigned_device(kvm) ||
10836 !irq_remapping_cap(IRQ_POSTING_CAP)) 10840 !irq_remapping_cap(IRQ_POSTING_CAP) ||
10841 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
10837 return 0; 10842 return 0;
10838 10843
10839 idx = srcu_read_lock(&kvm->irq_srcu); 10844 idx = srcu_read_lock(&kvm->irq_srcu);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-18 07:04:18 -0400