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Diffstat (limited to 'arch/arm/mach-omap2/powerdomains7xx_data.c')
-rw-r--r--arch/arm/mach-omap2/powerdomains7xx_data.c76
1 files changed, 2 insertions, 74 deletions
diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
index 0ec2d00f4237..eb350a673133 100644
--- a/arch/arm/mach-omap2/powerdomains7xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -36,14 +36,7 @@ static struct powerdomain iva_7xx_pwrdm = {
36 .prcm_offs = DRA7XX_PRM_IVA_INST, 36 .prcm_offs = DRA7XX_PRM_IVA_INST,
37 .prcm_partition = DRA7XX_PRM_PARTITION, 37 .prcm_partition = DRA7XX_PRM_PARTITION,
38 .pwrsts = PWRSTS_OFF_ON, 38 .pwrsts = PWRSTS_OFF_ON,
39 .pwrsts_logic_ret = PWRSTS_OFF,
40 .banks = 4, 39 .banks = 4,
41 .pwrsts_mem_ret = {
42 [0] = PWRSTS_OFF_RET, /* hwa_mem */
43 [1] = PWRSTS_OFF_RET, /* sl2_mem */
44 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
45 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
46 },
47 .pwrsts_mem_on = { 40 .pwrsts_mem_on = {
48 [0] = PWRSTS_ON, /* hwa_mem */ 41 [0] = PWRSTS_ON, /* hwa_mem */
49 [1] = PWRSTS_ON, /* sl2_mem */ 42 [1] = PWRSTS_ON, /* sl2_mem */
@@ -76,12 +69,7 @@ static struct powerdomain ipu_7xx_pwrdm = {
76 .prcm_offs = DRA7XX_PRM_IPU_INST, 69 .prcm_offs = DRA7XX_PRM_IPU_INST,
77 .prcm_partition = DRA7XX_PRM_PARTITION, 70 .prcm_partition = DRA7XX_PRM_PARTITION,
78 .pwrsts = PWRSTS_OFF_ON, 71 .pwrsts = PWRSTS_OFF_ON,
79 .pwrsts_logic_ret = PWRSTS_OFF,
80 .banks = 2, 72 .banks = 2,
81 .pwrsts_mem_ret = {
82 [0] = PWRSTS_OFF_RET, /* aessmem */
83 [1] = PWRSTS_OFF_RET, /* periphmem */
84 },
85 .pwrsts_mem_on = { 73 .pwrsts_mem_on = {
86 [0] = PWRSTS_ON, /* aessmem */ 74 [0] = PWRSTS_ON, /* aessmem */
87 [1] = PWRSTS_ON, /* periphmem */ 75 [1] = PWRSTS_ON, /* periphmem */
@@ -95,11 +83,7 @@ static struct powerdomain dss_7xx_pwrdm = {
95 .prcm_offs = DRA7XX_PRM_DSS_INST, 83 .prcm_offs = DRA7XX_PRM_DSS_INST,
96 .prcm_partition = DRA7XX_PRM_PARTITION, 84 .prcm_partition = DRA7XX_PRM_PARTITION,
97 .pwrsts = PWRSTS_OFF_ON, 85 .pwrsts = PWRSTS_OFF_ON,
98 .pwrsts_logic_ret = PWRSTS_OFF,
99 .banks = 1, 86 .banks = 1,
100 .pwrsts_mem_ret = {
101 [0] = PWRSTS_OFF_RET, /* dss_mem */
102 },
103 .pwrsts_mem_on = { 87 .pwrsts_mem_on = {
104 [0] = PWRSTS_ON, /* dss_mem */ 88 [0] = PWRSTS_ON, /* dss_mem */
105 }, 89 },
@@ -111,13 +95,8 @@ static struct powerdomain l4per_7xx_pwrdm = {
111 .name = "l4per_pwrdm", 95 .name = "l4per_pwrdm",
112 .prcm_offs = DRA7XX_PRM_L4PER_INST, 96 .prcm_offs = DRA7XX_PRM_L4PER_INST,
113 .prcm_partition = DRA7XX_PRM_PARTITION, 97 .prcm_partition = DRA7XX_PRM_PARTITION,
114 .pwrsts = PWRSTS_RET_ON, 98 .pwrsts = PWRSTS_ON,
115 .pwrsts_logic_ret = PWRSTS_RET,
116 .banks = 2, 99 .banks = 2,
117 .pwrsts_mem_ret = {
118 [0] = PWRSTS_OFF_RET, /* nonretained_bank */
119 [1] = PWRSTS_OFF_RET, /* retained_bank */
120 },
121 .pwrsts_mem_on = { 100 .pwrsts_mem_on = {
122 [0] = PWRSTS_ON, /* nonretained_bank */ 101 [0] = PWRSTS_ON, /* nonretained_bank */
123 [1] = PWRSTS_ON, /* retained_bank */ 102 [1] = PWRSTS_ON, /* retained_bank */
@@ -132,9 +111,6 @@ static struct powerdomain gpu_7xx_pwrdm = {
132 .prcm_partition = DRA7XX_PRM_PARTITION, 111 .prcm_partition = DRA7XX_PRM_PARTITION,
133 .pwrsts = PWRSTS_OFF_ON, 112 .pwrsts = PWRSTS_OFF_ON,
134 .banks = 1, 113 .banks = 1,
135 .pwrsts_mem_ret = {
136 [0] = PWRSTS_OFF_RET, /* gpu_mem */
137 },
138 .pwrsts_mem_on = { 114 .pwrsts_mem_on = {
139 [0] = PWRSTS_ON, /* gpu_mem */ 115 [0] = PWRSTS_ON, /* gpu_mem */
140 }, 116 },
@@ -148,8 +124,6 @@ static struct powerdomain wkupaon_7xx_pwrdm = {
148 .prcm_partition = DRA7XX_PRM_PARTITION, 124 .prcm_partition = DRA7XX_PRM_PARTITION,
149 .pwrsts = PWRSTS_ON, 125 .pwrsts = PWRSTS_ON,
150 .banks = 1, 126 .banks = 1,
151 .pwrsts_mem_ret = {
152 },
153 .pwrsts_mem_on = { 127 .pwrsts_mem_on = {
154 [0] = PWRSTS_ON, /* wkup_bank */ 128 [0] = PWRSTS_ON, /* wkup_bank */
155 }, 129 },
@@ -161,15 +135,7 @@ static struct powerdomain core_7xx_pwrdm = {
161 .prcm_offs = DRA7XX_PRM_CORE_INST, 135 .prcm_offs = DRA7XX_PRM_CORE_INST,
162 .prcm_partition = DRA7XX_PRM_PARTITION, 136 .prcm_partition = DRA7XX_PRM_PARTITION,
163 .pwrsts = PWRSTS_ON, 137 .pwrsts = PWRSTS_ON,
164 .pwrsts_logic_ret = PWRSTS_RET,
165 .banks = 5, 138 .banks = 5,
166 .pwrsts_mem_ret = {
167 [0] = PWRSTS_OFF_RET, /* core_nret_bank */
168 [1] = PWRSTS_OFF_RET, /* core_ocmram */
169 [2] = PWRSTS_OFF_RET, /* core_other_bank */
170 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
171 [4] = PWRSTS_OFF_RET, /* ipu_unicache */
172 },
173 .pwrsts_mem_on = { 139 .pwrsts_mem_on = {
174 [0] = PWRSTS_ON, /* core_nret_bank */ 140 [0] = PWRSTS_ON, /* core_nret_bank */
175 [1] = PWRSTS_ON, /* core_ocmram */ 141 [1] = PWRSTS_ON, /* core_ocmram */
@@ -226,11 +192,7 @@ static struct powerdomain vpe_7xx_pwrdm = {
226 .prcm_offs = DRA7XX_PRM_VPE_INST, 192 .prcm_offs = DRA7XX_PRM_VPE_INST,
227 .prcm_partition = DRA7XX_PRM_PARTITION, 193 .prcm_partition = DRA7XX_PRM_PARTITION,
228 .pwrsts = PWRSTS_OFF_ON, 194 .pwrsts = PWRSTS_OFF_ON,
229 .pwrsts_logic_ret = PWRSTS_OFF,
230 .banks = 1, 195 .banks = 1,
231 .pwrsts_mem_ret = {
232 [0] = PWRSTS_OFF_RET, /* vpe_bank */
233 },
234 .pwrsts_mem_on = { 196 .pwrsts_mem_on = {
235 [0] = PWRSTS_ON, /* vpe_bank */ 197 [0] = PWRSTS_ON, /* vpe_bank */
236 }, 198 },
@@ -260,14 +222,8 @@ static struct powerdomain l3init_7xx_pwrdm = {
260 .name = "l3init_pwrdm", 222 .name = "l3init_pwrdm",
261 .prcm_offs = DRA7XX_PRM_L3INIT_INST, 223 .prcm_offs = DRA7XX_PRM_L3INIT_INST,
262 .prcm_partition = DRA7XX_PRM_PARTITION, 224 .prcm_partition = DRA7XX_PRM_PARTITION,
263 .pwrsts = PWRSTS_RET_ON, 225 .pwrsts = PWRSTS_ON,
264 .pwrsts_logic_ret = PWRSTS_RET,
265 .banks = 3, 226 .banks = 3,
266 .pwrsts_mem_ret = {
267 [0] = PWRSTS_OFF_RET, /* gmac_bank */
268 [1] = PWRSTS_OFF_RET, /* l3init_bank1 */
269 [2] = PWRSTS_OFF_RET, /* l3init_bank2 */
270 },
271 .pwrsts_mem_on = { 227 .pwrsts_mem_on = {
272 [0] = PWRSTS_ON, /* gmac_bank */ 228 [0] = PWRSTS_ON, /* gmac_bank */
273 [1] = PWRSTS_ON, /* l3init_bank1 */ 229 [1] = PWRSTS_ON, /* l3init_bank1 */
@@ -283,9 +239,6 @@ static struct powerdomain eve3_7xx_pwrdm = {
283 .prcm_partition = DRA7XX_PRM_PARTITION, 239 .prcm_partition = DRA7XX_PRM_PARTITION,
284 .pwrsts = PWRSTS_OFF_ON, 240 .pwrsts = PWRSTS_OFF_ON,
285 .banks = 1, 241 .banks = 1,
286 .pwrsts_mem_ret = {
287 [0] = PWRSTS_OFF_RET, /* eve3_bank */
288 },
289 .pwrsts_mem_on = { 242 .pwrsts_mem_on = {
290 [0] = PWRSTS_ON, /* eve3_bank */ 243 [0] = PWRSTS_ON, /* eve3_bank */
291 }, 244 },
@@ -299,9 +252,6 @@ static struct powerdomain emu_7xx_pwrdm = {
299 .prcm_partition = DRA7XX_PRM_PARTITION, 252 .prcm_partition = DRA7XX_PRM_PARTITION,
300 .pwrsts = PWRSTS_OFF_ON, 253 .pwrsts = PWRSTS_OFF_ON,
301 .banks = 1, 254 .banks = 1,
302 .pwrsts_mem_ret = {
303 [0] = PWRSTS_OFF_RET, /* emu_bank */
304 },
305 .pwrsts_mem_on = { 255 .pwrsts_mem_on = {
306 [0] = PWRSTS_ON, /* emu_bank */ 256 [0] = PWRSTS_ON, /* emu_bank */
307 }, 257 },
@@ -314,11 +264,6 @@ static struct powerdomain dsp2_7xx_pwrdm = {
314 .prcm_partition = DRA7XX_PRM_PARTITION, 264 .prcm_partition = DRA7XX_PRM_PARTITION,
315 .pwrsts = PWRSTS_OFF_ON, 265 .pwrsts = PWRSTS_OFF_ON,
316 .banks = 3, 266 .banks = 3,
317 .pwrsts_mem_ret = {
318 [0] = PWRSTS_OFF_RET, /* dsp2_edma */
319 [1] = PWRSTS_OFF_RET, /* dsp2_l1 */
320 [2] = PWRSTS_OFF_RET, /* dsp2_l2 */
321 },
322 .pwrsts_mem_on = { 267 .pwrsts_mem_on = {
323 [0] = PWRSTS_ON, /* dsp2_edma */ 268 [0] = PWRSTS_ON, /* dsp2_edma */
324 [1] = PWRSTS_ON, /* dsp2_l1 */ 269 [1] = PWRSTS_ON, /* dsp2_l1 */
@@ -334,11 +279,6 @@ static struct powerdomain dsp1_7xx_pwrdm = {
334 .prcm_partition = DRA7XX_PRM_PARTITION, 279 .prcm_partition = DRA7XX_PRM_PARTITION,
335 .pwrsts = PWRSTS_OFF_ON, 280 .pwrsts = PWRSTS_OFF_ON,
336 .banks = 3, 281 .banks = 3,
337 .pwrsts_mem_ret = {
338 [0] = PWRSTS_OFF_RET, /* dsp1_edma */
339 [1] = PWRSTS_OFF_RET, /* dsp1_l1 */
340 [2] = PWRSTS_OFF_RET, /* dsp1_l2 */
341 },
342 .pwrsts_mem_on = { 282 .pwrsts_mem_on = {
343 [0] = PWRSTS_ON, /* dsp1_edma */ 283 [0] = PWRSTS_ON, /* dsp1_edma */
344 [1] = PWRSTS_ON, /* dsp1_l1 */ 284 [1] = PWRSTS_ON, /* dsp1_l1 */
@@ -354,9 +294,6 @@ static struct powerdomain cam_7xx_pwrdm = {
354 .prcm_partition = DRA7XX_PRM_PARTITION, 294 .prcm_partition = DRA7XX_PRM_PARTITION,
355 .pwrsts = PWRSTS_OFF_ON, 295 .pwrsts = PWRSTS_OFF_ON,
356 .banks = 1, 296 .banks = 1,
357 .pwrsts_mem_ret = {
358 [0] = PWRSTS_OFF_RET, /* vip_bank */
359 },
360 .pwrsts_mem_on = { 297 .pwrsts_mem_on = {
361 [0] = PWRSTS_ON, /* vip_bank */ 298 [0] = PWRSTS_ON, /* vip_bank */
362 }, 299 },
@@ -370,9 +307,6 @@ static struct powerdomain eve4_7xx_pwrdm = {
370 .prcm_partition = DRA7XX_PRM_PARTITION, 307 .prcm_partition = DRA7XX_PRM_PARTITION,
371 .pwrsts = PWRSTS_OFF_ON, 308 .pwrsts = PWRSTS_OFF_ON,
372 .banks = 1, 309 .banks = 1,
373 .pwrsts_mem_ret = {
374 [0] = PWRSTS_OFF_RET, /* eve4_bank */
375 },
376 .pwrsts_mem_on = { 310 .pwrsts_mem_on = {
377 [0] = PWRSTS_ON, /* eve4_bank */ 311 [0] = PWRSTS_ON, /* eve4_bank */
378 }, 312 },
@@ -386,9 +320,6 @@ static struct powerdomain eve2_7xx_pwrdm = {
386 .prcm_partition = DRA7XX_PRM_PARTITION, 320 .prcm_partition = DRA7XX_PRM_PARTITION,
387 .pwrsts = PWRSTS_OFF_ON, 321 .pwrsts = PWRSTS_OFF_ON,
388 .banks = 1, 322 .banks = 1,
389 .pwrsts_mem_ret = {
390 [0] = PWRSTS_OFF_RET, /* eve2_bank */
391 },
392 .pwrsts_mem_on = { 323 .pwrsts_mem_on = {
393 [0] = PWRSTS_ON, /* eve2_bank */ 324 [0] = PWRSTS_ON, /* eve2_bank */
394 }, 325 },
@@ -402,9 +333,6 @@ static struct powerdomain eve1_7xx_pwrdm = {
402 .prcm_partition = DRA7XX_PRM_PARTITION, 333 .prcm_partition = DRA7XX_PRM_PARTITION,
403 .pwrsts = PWRSTS_OFF_ON, 334 .pwrsts = PWRSTS_OFF_ON,
404 .banks = 1, 335 .banks = 1,
405 .pwrsts_mem_ret = {
406 [0] = PWRSTS_OFF_RET, /* eve1_bank */
407 },
408 .pwrsts_mem_on = { 336 .pwrsts_mem_on = {
409 [0] = PWRSTS_ON, /* eve1_bank */ 337 [0] = PWRSTS_ON, /* eve1_bank */
410 }, 338 },
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 01:37:10 -0400