Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net

Two easily resolvable overlapping change conflicts, one in
TCP and one in the eBPF verifier.

Signed-off-by: David S. Miller <davem@davemloft.net>

49 files changed, 404 insertions, 184 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 664e918e2624..26524b75970a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1400,6 +1400,7 @@ config NR_CPUS
 config HOTPLUG_CPU
         bool "Support for hot-pluggable CPUs"
         depends on SMP
+        select GENERIC_IRQ_MIGRATION
         help
           Say Y here to experiment with turning CPUs off and on.  CPUs
           can be controlled through /sys/devices/system/cpu.
diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts
index 04758a2a87f0..67d77eee9433 100644
--- a/arch/arm/boot/dts/omap4-droid4-xt894.dts
+++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts
@@ -644,6 +644,17 @@
         };
 };
 
+/* Configure pwm clock source for timers 8 & 9 */
+&timer8 {
+        assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
+        assigned-clock-parents = <&sys_clkin_ck>;
+};
+
+&timer9 {
+        assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>;
+        assigned-clock-parents = <&sys_clkin_ck>;
+};
+
 /*
  * As uart1 is wired to mdm6600 with rts and cts, we can use the cts pin for
  * uart1 wakeirq.
diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi
index bc853ebeda22..61a06f6add3c 100644
--- a/arch/arm/boot/dts/omap5-board-common.dtsi
+++ b/arch/arm/boot/dts/omap5-board-common.dtsi
@@ -317,7 +317,8 @@
 
         palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins {
                 pinctrl-single,pins = <
-                        OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1 */
+                        /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */
+                        OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0)
                 >;
         };
 
@@ -385,7 +386,8 @@
 
         palmas: palmas@48 {
                 compatible = "ti,palmas";
-                interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
+                /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
                 reg = <0x48>;
                 interrupt-controller;
                 #interrupt-cells = <2>;
@@ -651,7 +653,8 @@
                 pinctrl-names = "default";
                 pinctrl-0 = <&twl6040_pins>;
 
-                interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */
+                /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
+                interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_LOW>;
 
                 /* audpwron gpio defined in the board specific dts */
 
diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts
index 5e21fb430a65..e78d3718f145 100644
--- a/arch/arm/boot/dts/omap5-cm-t54.dts
+++ b/arch/arm/boot/dts/omap5-cm-t54.dts
@@ -181,6 +181,13 @@
                         OMAP5_IOPAD(0x0042, PIN_INPUT_PULLDOWN | MUX_MODE6)  /* llib_wakereqin.gpio1_wk15 */
                 >;
         };
+
+        palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins {
+                pinctrl-single,pins = <
+                        /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */
+                        OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0)
+                >;
+        };
 };
 
 &omap5_pmx_core {
@@ -414,8 +421,11 @@
 
         palmas: palmas@48 {
                 compatible = "ti,palmas";
-                interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
                 reg = <0x48>;
+                pinctrl-0 = <&palmas_sys_nirq_pins>;
+                pinctrl-names = "default";
+                /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
                 interrupt-controller;
                 #interrupt-cells = <2>;
                 ti,system-power-controller;
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 4acb501dd3f8..3ed49898f4b2 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -719,7 +719,6 @@
                         pm_qos = <&qos_lcdc0>,
                                  <&qos_lcdc1>,
                                  <&qos_cif0>,
-                                 <&qos_cif1>,
                                  <&qos_ipp>,
                                  <&qos_rga>;
                 };
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index c883fcbe93b6..46d41140df27 100644
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -25,7 +25,6 @@
 #ifndef __ASSEMBLY__
 struct irqaction;
 struct pt_regs;
-extern void migrate_irqs(void);
 
 extern void asm_do_IRQ(unsigned int, struct pt_regs *);
 void handle_IRQ(unsigned int, struct pt_regs *);
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index ca56537b61bc..50e89869178a 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -48,6 +48,7 @@
 #define KVM_REQ_SLEEP \
         KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
 #define KVM_REQ_IRQ_PENDING     KVM_ARCH_REQ(1)
+#define KVM_REQ_VCPU_RESET      KVM_ARCH_REQ(2)
 
 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
 
@@ -147,6 +148,13 @@ struct kvm_cpu_context {
 
 typedef struct kvm_cpu_context kvm_cpu_context_t;
 
+struct vcpu_reset_state {
+        unsigned long   pc;
+        unsigned long   r0;
+        bool            be;
+        bool            reset;
+};
+
 struct kvm_vcpu_arch {
         struct kvm_cpu_context ctxt;
 
@@ -186,6 +194,8 @@ struct kvm_vcpu_arch {
         /* Cache some mmu pages needed inside spinlock regions */
         struct kvm_mmu_memory_cache mmu_page_cache;
 
+        struct vcpu_reset_state reset_state;
+
         /* Detect first run of a vcpu */
         bool has_run_once;
 };
diff --git a/arch/arm/include/asm/stage2_pgtable.h b/arch/arm/include/asm/stage2_pgtable.h
index c4b1d4fb1797..de2089501b8b 100644
--- a/arch/arm/include/asm/stage2_pgtable.h
+++ b/arch/arm/include/asm/stage2_pgtable.h
@@ -76,4 +76,9 @@ static inline bool kvm_stage2_has_pud(struct kvm *kvm)
 #define S2_PMD_MASK                             PMD_MASK
 #define S2_PMD_SIZE                             PMD_SIZE
 
+static inline bool kvm_stage2_has_pmd(struct kvm *kvm)
+{
+        return true;
+}
+
 #endif  /* __ARM_S2_PGTABLE_H_ */
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 9908dacf9229..844861368cd5 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -31,7 +31,6 @@
 #include <linux/smp.h>
 #include <linux/init.h>
 #include <linux/seq_file.h>
-#include <linux/ratelimit.h>
 #include <linux/errno.h>
 #include <linux/list.h>
 #include <linux/kallsyms.h>
@@ -109,64 +108,3 @@ int __init arch_probe_nr_irqs(void)
         return nr_irqs;
 }
 #endif
-
-#ifdef CONFIG_HOTPLUG_CPU
-static bool migrate_one_irq(struct irq_desc *desc)
-{
-        struct irq_data *d = irq_desc_get_irq_data(desc);
-        const struct cpumask *affinity = irq_data_get_affinity_mask(d);
-        struct irq_chip *c;
-        bool ret = false;
-
-        /*
-         * If this is a per-CPU interrupt, or the affinity does not
-         * include this CPU, then we have nothing to do.
-         */
-        if (irqd_is_per_cpu(d) || !cpumask_test_cpu(smp_processor_id(), affinity))
-                return false;
-
-        if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
-                affinity = cpu_online_mask;
-                ret = true;
-        }
-
-        c = irq_data_get_irq_chip(d);
-        if (!c->irq_set_affinity)
-                pr_debug("IRQ%u: unable to set affinity\n", d->irq);
-        else if (c->irq_set_affinity(d, affinity, false) == IRQ_SET_MASK_OK && ret)
-                cpumask_copy(irq_data_get_affinity_mask(d), affinity);
-
-        return ret;
-}
-
-/*
- * The current CPU has been marked offline.  Migrate IRQs off this CPU.
- * If the affinity settings do not allow other CPUs, force them onto any
- * available CPU.
- *
- * Note: we must iterate over all IRQs, whether they have an attached
- * action structure or not, as we need to get chained interrupts too.
- */
-void migrate_irqs(void)
-{
-        unsigned int i;
-        struct irq_desc *desc;
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        for_each_irq_desc(i, desc) {
-                bool affinity_broken;
-
-                raw_spin_lock(&desc->lock);
-                affinity_broken = migrate_one_irq(desc);
-                raw_spin_unlock(&desc->lock);
-
-                if (affinity_broken)
-                        pr_warn_ratelimited("IRQ%u no longer affine to CPU%u\n",
-                                i, smp_processor_id());
-        }
-
-        local_irq_restore(flags);
-}
-#endif /* CONFIG_HOTPLUG_CPU */
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 3bf82232b1be..1d6f5ea522f4 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -254,7 +254,7 @@ int __cpu_disable(void)
         /*
          * OK - migrate IRQs away from this CPU
          */
-        migrate_irqs();
+        irq_migrate_all_off_this_cpu();
 
         /*
          * Flush user cache and TLB mappings, and then remove this CPU
diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
index 222c1635bc7a..e8bd288fd5be 100644
--- a/arch/arm/kvm/coproc.c
+++ b/arch/arm/kvm/coproc.c
@@ -1450,6 +1450,6 @@ void kvm_reset_coprocs(struct kvm_vcpu *vcpu)
         reset_coproc_regs(vcpu, table, num);
 
         for (num = 1; num < NR_CP15_REGS; num++)
-                if (vcpu_cp15(vcpu, num) == 0x42424242)
-                        panic("Didn't reset vcpu_cp15(vcpu, %zi)", num);
+                WARN(vcpu_cp15(vcpu, num) == 0x42424242,
+                     "Didn't reset vcpu_cp15(vcpu, %zi)", num);
 }
diff --git a/arch/arm/kvm/reset.c b/arch/arm/kvm/reset.c
index 5ed0c3ee33d6..e53327912adc 100644
--- a/arch/arm/kvm/reset.c
+++ b/arch/arm/kvm/reset.c
@@ -26,6 +26,7 @@
 #include <asm/cputype.h>
 #include <asm/kvm_arm.h>
 #include <asm/kvm_coproc.h>
+#include <asm/kvm_emulate.h>
 
 #include <kvm/arm_arch_timer.h>
 
@@ -69,6 +70,29 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
         /* Reset CP15 registers */
         kvm_reset_coprocs(vcpu);
 
+        /*
+         * Additional reset state handling that PSCI may have imposed on us.
+         * Must be done after all the sys_reg reset.
+         */
+        if (READ_ONCE(vcpu->arch.reset_state.reset)) {
+                unsigned long target_pc = vcpu->arch.reset_state.pc;
+
+                /* Gracefully handle Thumb2 entry point */
+                if (target_pc & 1) {
+                        target_pc &= ~1UL;
+                        vcpu_set_thumb(vcpu);
+                }
+
+                /* Propagate caller endianness */
+                if (vcpu->arch.reset_state.be)
+                        kvm_vcpu_set_be(vcpu);
+
+                *vcpu_pc(vcpu) = target_pc;
+                vcpu_set_reg(vcpu, 0, vcpu->arch.reset_state.r0);
+
+                vcpu->arch.reset_state.reset = false;
+        }
+
         /* Reset arch_timer context */
         return kvm_timer_vcpu_reset(vcpu);
 }
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index a8b291f00109..dae514c8276a 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -152,6 +152,10 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
         mpuss_can_lose_context = (cx->mpu_state == PWRDM_POWER_RET) &&
                                  (cx->mpu_logic_state == PWRDM_POWER_OFF);
 
+        /* Enter broadcast mode for periodic timers */
+        tick_broadcast_enable();
+
+        /* Enter broadcast mode for one-shot timers */
         tick_broadcast_enter();
 
         /*
@@ -218,15 +222,6 @@ fail:
         return index;
 }
 
-/*
- * For each cpu, setup the broadcast timer because local timers
- * stops for the states above C1.
- */
-static void omap_setup_broadcast_timer(void *arg)
-{
-        tick_broadcast_enable();
-}
-
 static struct cpuidle_driver omap4_idle_driver = {
         .name                           = "omap4_idle",
         .owner                          = THIS_MODULE,
@@ -319,8 +314,5 @@ int __init omap4_idle_init(void)
         if (!cpu_clkdm[0] || !cpu_clkdm[1])
                 return -ENODEV;
 
-        /* Configure the broadcast timer on each cpu */
-        on_each_cpu(omap_setup_broadcast_timer, NULL, 1);
-
         return cpuidle_register(idle_driver, cpu_online_mask);
 }
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index f86b72d1d59e..1444b4b4bd9f 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -83,6 +83,7 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
         u32 enable_mask, enable_shift;
         u32 pipd_mask, pipd_shift;
         u32 reg;
+        int ret;
 
         if (dsi_id == 0) {
                 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
@@ -98,7 +99,11 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
                 return -ENODEV;
         }
 
-        regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, &reg);
+        ret = regmap_read(omap4_dsi_mux_syscon,
+                                          OMAP4_DSIPHY_SYSCON_OFFSET,
+                                          &reg);
+        if (ret)
+                return ret;
 
         reg &= ~enable_mask;
         reg &= ~pipd_mask;
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index fc5fb776a710..17558be4bf0a 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -50,6 +50,9 @@
 #define OMAP4_NR_BANKS          4
 #define OMAP4_NR_IRQS           128
 
+#define SYS_NIRQ1_EXT_SYS_IRQ_1 7
+#define SYS_NIRQ2_EXT_SYS_IRQ_2 119
+
 static void __iomem *wakeupgen_base;
 static void __iomem *sar_base;
 static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
@@ -153,6 +156,37 @@ static void wakeupgen_unmask(struct irq_data *d)
         irq_chip_unmask_parent(d);
 }
 
+/*
+ * The sys_nirq pins bypass peripheral modules and are wired directly
+ * to MPUSS wakeupgen. They get automatically inverted for GIC.
+ */
+static int wakeupgen_irq_set_type(struct irq_data *d, unsigned int type)
+{
+        bool inverted = false;
+
+        switch (type) {
+        case IRQ_TYPE_LEVEL_LOW:
+                type &= ~IRQ_TYPE_LEVEL_MASK;
+                type |= IRQ_TYPE_LEVEL_HIGH;
+                inverted = true;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                type &= ~IRQ_TYPE_EDGE_BOTH;
+                type |= IRQ_TYPE_EDGE_RISING;
+                inverted = true;
+                break;
+        default:
+                break;
+        }
+
+        if (inverted && d->hwirq != SYS_NIRQ1_EXT_SYS_IRQ_1 &&
+            d->hwirq != SYS_NIRQ2_EXT_SYS_IRQ_2)
+                pr_warn("wakeupgen: irq%li polarity inverted in dts\n",
+                        d->hwirq);
+
+        return irq_chip_set_type_parent(d, type);
+}
+
 #ifdef CONFIG_HOTPLUG_CPU
 static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
 
@@ -446,7 +480,7 @@ static struct irq_chip wakeupgen_chip = {
         .irq_mask               = wakeupgen_mask,
         .irq_unmask             = wakeupgen_unmask,
         .irq_retrigger          = irq_chip_retrigger_hierarchy,
-        .irq_set_type           = irq_chip_set_type_parent,
+        .irq_set_type           = wakeupgen_irq_set_type,
         .flags                  = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
 #ifdef CONFIG_SMP
         .irq_set_affinity       = irq_chip_set_affinity_parent,
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index f1e2922e447c..1e3e08a1c456 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -2390,4 +2390,6 @@ void arch_teardown_dma_ops(struct device *dev)
                 return;
 
         arm_teardown_iommu_dma_ops(dev);
+        /* Let arch_setup_dma_ops() start again from scratch upon re-probe */
+        set_dma_ops(dev, NULL);
 }
diff --git a/arch/arm/probes/kprobes/opt-arm.c b/arch/arm/probes/kprobes/opt-arm.c
index 2c118a6ab358..0dc23fc227ed 100644
--- a/arch/arm/probes/kprobes/opt-arm.c
+++ b/arch/arm/probes/kprobes/opt-arm.c
@@ -247,7 +247,7 @@ int arch_prepare_optimized_kprobe(struct optimized_kprobe *op, struct kprobe *or
         }
 
         /* Copy arch-dep-instance from template. */
-        memcpy(code, (unsigned char *)optprobe_template_entry,
+        memcpy(code, (unsigned long *)&optprobe_template_entry,
                         TMPL_END_IDX * sizeof(kprobe_opcode_t));
 
         /* Adjust buffer according to instruction. */
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 64acccc4bfcb..f74b13aa5aa5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -227,34 +227,34 @@
 
         pinctrl_usdhc1_100mhz: usdhc1-100grp {
                 fsl,pins = <
-                        MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x85
-                        MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc5
-                        MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xc5
-                        MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xc5
-                        MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xc5
-                        MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xc5
-                        MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xc5
-                        MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xc5
-                        MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xc5
-                        MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xc5
-                        MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x85
+                        MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x8d
+                        MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xcd
+                        MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xcd
+                        MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xcd
+                        MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xcd
+                        MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xcd
+                        MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xcd
+                        MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xcd
+                        MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xcd
+                        MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xcd
+                        MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x8d
                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
                 >;
         };
 
         pinctrl_usdhc1_200mhz: usdhc1-200grp {
                 fsl,pins = <
-                        MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x87
-                        MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc7
-                        MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xc7
-                        MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xc7
-                        MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xc7
-                        MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xc7
-                        MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xc7
-                        MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xc7
-                        MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xc7
-                        MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xc7
-                        MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x87
+                        MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x9f
+                        MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xdf
+                        MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xdf
+                        MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xdf
+                        MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xdf
+                        MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xdf
+                        MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xdf
+                        MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xdf
+                        MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xdf
+                        MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xdf
+                        MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x9f
                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
                 >;
         };
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 8e9d6d5ed7b2..b6d31499fb43 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -360,6 +360,8 @@
                                          <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
                                          <&clk IMX8MQ_CLK_USDHC1_ROOT>;
                                 clock-names = "ipg", "ahb", "per";
+                                assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
+                                assigned-clock-rates = <400000000>;
                                 fsl,tuning-start-tap = <20>;
                                 fsl,tuning-step = <2>;
                                 bus-width = <4>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
index bd937d68ca3b..040b36ef0dd2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
@@ -40,6 +40,7 @@
                 pinctrl-0 = <&usb30_host_drv>;
                 regulator-name = "vcc_host_5v";
                 regulator-always-on;
+                regulator-boot-on;
                 vin-supply = <&vcc_sys>;
         };
 
@@ -51,6 +52,7 @@
                 pinctrl-0 = <&usb20_host_drv>;
                 regulator-name = "vcc_host1_5v";
                 regulator-always-on;
+                regulator-boot-on;
                 vin-supply = <&vcc_sys>;
         };
 
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts
index 1ee0dc0d9f10..d1cf404b8708 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts
@@ -22,7 +22,7 @@
                 backlight = <&backlight>;
                 power-supply = <&pp3300_disp>;
 
-                ports {
+                port {
                         panel_in_edp: endpoint {
                                 remote-endpoint = <&edp_out_panel>;
                         };
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
index 81e73103fa78..15e254a77391 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
@@ -43,7 +43,7 @@
                 backlight = <&backlight>;
                 power-supply = <&pp3300_disp>;
 
-                ports {
+                port {
                         panel_in_edp: endpoint {
                                 remote-endpoint = <&edp_out_panel>;
                         };
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
index 0b8f1edbd746..b48a63c3efc3 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
@@ -91,7 +91,7 @@
                 pinctrl-0 = <&lcd_panel_reset>;
                 power-supply = <&vcc3v3_s0>;
 
-                ports {
+                port {
                         panel_in_edp: endpoint {
                                 remote-endpoint = <&edp_out_panel>;
                         };
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 7732d0ba4e60..da3fc7324d68 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -48,6 +48,7 @@
 #define KVM_REQ_SLEEP \
         KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
 #define KVM_REQ_IRQ_PENDING     KVM_ARCH_REQ(1)
+#define KVM_REQ_VCPU_RESET      KVM_ARCH_REQ(2)
 
 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
 
@@ -208,6 +209,13 @@ struct kvm_cpu_context {
 
 typedef struct kvm_cpu_context kvm_cpu_context_t;
 
+struct vcpu_reset_state {
+        unsigned long   pc;
+        unsigned long   r0;
+        bool            be;
+        bool            reset;
+};
+
 struct kvm_vcpu_arch {
         struct kvm_cpu_context ctxt;
 
@@ -297,6 +305,9 @@ struct kvm_vcpu_arch {
         /* Virtual SError ESR to restore when HCR_EL2.VSE is set */
         u64 vsesr_el2;
 
+        /* Additional reset state */
+        struct vcpu_reset_state reset_state;
+
         /* True when deferrable sysregs are loaded on the physical CPU,
          * see kvm_vcpu_load_sysregs and kvm_vcpu_put_sysregs. */
         bool sysregs_loaded_on_cpu;
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index e1ec947e7c0c..0c656850eeea 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -332,6 +332,17 @@ static inline void *phys_to_virt(phys_addr_t x)
 #define virt_addr_valid(kaddr)          \
         (_virt_addr_is_linear(kaddr) && _virt_addr_valid(kaddr))
 
+/*
+ * Given that the GIC architecture permits ITS implementations that can only be
+ * configured with a LPI table address once, GICv3 systems with many CPUs may
+ * end up reserving a lot of different regions after a kexec for their LPI
+ * tables (one per CPU), as we are forced to reuse the same memory after kexec
+ * (and thus reserve it persistently with EFI beforehand)
+ */
+#if defined(CONFIG_EFI) && defined(CONFIG_ARM_GIC_V3_ITS)
+# define INIT_MEMBLOCK_RESERVED_REGIONS (INIT_MEMBLOCK_REGIONS + NR_CPUS + 1)
+#endif
+
 #include <asm-generic/memory_model.h>
 
 #endif
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index 4b0e1231625c..d09ec76f08cf 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -313,7 +313,6 @@ void __init setup_arch(char **cmdline_p)
         arm64_memblock_init();
 
         paging_init();
-        efi_apply_persistent_mem_reservations();
 
         acpi_table_upgrade();
 
diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
index b0b1478094b4..421ebf6f7086 100644
--- a/arch/arm64/kvm/hyp/switch.c
+++ b/arch/arm64/kvm/hyp/switch.c
@@ -23,6 +23,7 @@
 #include <kvm/arm_psci.h>
 
 #include <asm/cpufeature.h>
+#include <asm/kprobes.h>
 #include <asm/kvm_asm.h>
 #include <asm/kvm_emulate.h>
 #include <asm/kvm_host.h>
@@ -107,6 +108,7 @@ static void activate_traps_vhe(struct kvm_vcpu *vcpu)
 
         write_sysreg(kvm_get_hyp_vector(), vbar_el1);
 }
+NOKPROBE_SYMBOL(activate_traps_vhe);
 
 static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu)
 {
@@ -154,6 +156,7 @@ static void deactivate_traps_vhe(void)
         write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1);
         write_sysreg(vectors, vbar_el1);
 }
+NOKPROBE_SYMBOL(deactivate_traps_vhe);
 
 static void __hyp_text __deactivate_traps_nvhe(void)
 {
@@ -513,6 +516,7 @@ int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
 
         return exit_code;
 }
+NOKPROBE_SYMBOL(kvm_vcpu_run_vhe);
 
 /* Switch to the guest for legacy non-VHE systems */
 int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu)
@@ -620,6 +624,7 @@ static void __hyp_call_panic_vhe(u64 spsr, u64 elr, u64 par,
               read_sysreg_el2(esr),   read_sysreg_el2(far),
               read_sysreg(hpfar_el2), par, vcpu);
 }
+NOKPROBE_SYMBOL(__hyp_call_panic_vhe);
 
 void __hyp_text __noreturn hyp_panic(struct kvm_cpu_context *host_ctxt)
 {
diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c b/arch/arm64/kvm/hyp/sysreg-sr.c
index 68d6f7c3b237..b426e2cf973c 100644
--- a/arch/arm64/kvm/hyp/sysreg-sr.c
+++ b/arch/arm64/kvm/hyp/sysreg-sr.c
@@ -18,6 +18,7 @@
 #include <linux/compiler.h>
 #include <linux/kvm_host.h>
 
+#include <asm/kprobes.h>
 #include <asm/kvm_asm.h>
 #include <asm/kvm_emulate.h>
 #include <asm/kvm_hyp.h>
@@ -98,12 +99,14 @@ void sysreg_save_host_state_vhe(struct kvm_cpu_context *ctxt)
 {
         __sysreg_save_common_state(ctxt);
 }
+NOKPROBE_SYMBOL(sysreg_save_host_state_vhe);
 
 void sysreg_save_guest_state_vhe(struct kvm_cpu_context *ctxt)
 {
         __sysreg_save_common_state(ctxt);
         __sysreg_save_el2_return_state(ctxt);
 }
+NOKPROBE_SYMBOL(sysreg_save_guest_state_vhe);
 
 static void __hyp_text __sysreg_restore_common_state(struct kvm_cpu_context *ctxt)
 {
@@ -188,12 +191,14 @@ void sysreg_restore_host_state_vhe(struct kvm_cpu_context *ctxt)
 {
         __sysreg_restore_common_state(ctxt);
 }
+NOKPROBE_SYMBOL(sysreg_restore_host_state_vhe);
 
 void sysreg_restore_guest_state_vhe(struct kvm_cpu_context *ctxt)
 {
         __sysreg_restore_common_state(ctxt);
         __sysreg_restore_el2_return_state(ctxt);
 }
+NOKPROBE_SYMBOL(sysreg_restore_guest_state_vhe);
 
 void __hyp_text __sysreg32_save_state(struct kvm_vcpu *vcpu)
 {
diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
index b72a3dd56204..f16a5f8ff2b4 100644
--- a/arch/arm64/kvm/reset.c
+++ b/arch/arm64/kvm/reset.c
@@ -32,6 +32,7 @@
 #include <asm/kvm_arm.h>
 #include <asm/kvm_asm.h>
 #include <asm/kvm_coproc.h>
+#include <asm/kvm_emulate.h>
 #include <asm/kvm_mmu.h>
 
 /* Maximum phys_shift supported for any VM on this host */
@@ -105,16 +106,33 @@ int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext)
  * This function finds the right table above and sets the registers on
  * the virtual CPU struct to their architecturally defined reset
  * values.
+ *
+ * Note: This function can be called from two paths: The KVM_ARM_VCPU_INIT
+ * ioctl or as part of handling a request issued by another VCPU in the PSCI
+ * handling code.  In the first case, the VCPU will not be loaded, and in the
+ * second case the VCPU will be loaded.  Because this function operates purely
+ * on the memory-backed valus of system registers, we want to do a full put if
+ * we were loaded (handling a request) and load the values back at the end of
+ * the function.  Otherwise we leave the state alone.  In both cases, we
+ * disable preemption around the vcpu reset as we would otherwise race with
+ * preempt notifiers which also call put/load.
  */
 int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
 {
         const struct kvm_regs *cpu_reset;
+        int ret = -EINVAL;
+        bool loaded;
+
+        preempt_disable();
+        loaded = (vcpu->cpu != -1);
+        if (loaded)
+                kvm_arch_vcpu_put(vcpu);
 
         switch (vcpu->arch.target) {
         default:
                 if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) {
                         if (!cpu_has_32bit_el1())
-                                return -EINVAL;
+                                goto out;
                         cpu_reset = &default_regs_reset32;
                 } else {
                         cpu_reset = &default_regs_reset;
@@ -129,6 +147,29 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
         /* Reset system registers */
         kvm_reset_sys_regs(vcpu);
 
+        /*
+         * Additional reset state handling that PSCI may have imposed on us.
+         * Must be done after all the sys_reg reset.
+         */
+        if (vcpu->arch.reset_state.reset) {
+                unsigned long target_pc = vcpu->arch.reset_state.pc;
+
+                /* Gracefully handle Thumb2 entry point */
+                if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) {
+                        target_pc &= ~1UL;
+                        vcpu_set_thumb(vcpu);
+                }
+
+                /* Propagate caller endianness */
+                if (vcpu->arch.reset_state.be)
+                        kvm_vcpu_set_be(vcpu);
+
+                *vcpu_pc(vcpu) = target_pc;
+                vcpu_set_reg(vcpu, 0, vcpu->arch.reset_state.r0);
+
+                vcpu->arch.reset_state.reset = false;
+        }
+
         /* Reset PMU */
         kvm_pmu_vcpu_reset(vcpu);
 
@@ -137,7 +178,12 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
                 vcpu->arch.workaround_flags |= VCPU_WORKAROUND_2_FLAG;
 
         /* Reset timer */
-        return kvm_timer_vcpu_reset(vcpu);
+        ret = kvm_timer_vcpu_reset(vcpu);
+out:
+        if (loaded)
+                kvm_arch_vcpu_load(vcpu, smp_processor_id());
+        preempt_enable();
+        return ret;
 }
 
 void kvm_set_ipa_limit(void)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index e3e37228ae4e..c936aa40c3f4 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -314,12 +314,29 @@ static bool trap_raz_wi(struct kvm_vcpu *vcpu,
                 return read_zero(vcpu, p);
 }
 
-static bool trap_undef(struct kvm_vcpu *vcpu,
-                       struct sys_reg_params *p,
-                       const struct sys_reg_desc *r)
+/*
+ * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
+ * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
+ * system, these registers should UNDEF. LORID_EL1 being a RO register, we
+ * treat it separately.
+ */
+static bool trap_loregion(struct kvm_vcpu *vcpu,
+                          struct sys_reg_params *p,
+                          const struct sys_reg_desc *r)
 {
-        kvm_inject_undefined(vcpu);
-        return false;
+        u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
+        u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1,
+                         (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
+
+        if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
+                kvm_inject_undefined(vcpu);
+                return false;
+        }
+
+        if (p->is_write && sr == SYS_LORID_EL1)
+                return write_to_read_only(vcpu, p, r);
+
+        return trap_raz_wi(vcpu, p, r);
 }
 
 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
@@ -1048,11 +1065,6 @@ static u64 read_id_reg(struct sys_reg_desc const *r, bool raz)
                 if (val & ptrauth_mask)
                         kvm_debug("ptrauth unsupported for guests, suppressing\n");
                 val &= ~ptrauth_mask;
-        } else if (id == SYS_ID_AA64MMFR1_EL1) {
-                if (val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))
-                        kvm_debug("LORegions unsupported for guests, suppressing\n");
-
-                val &= ~(0xfUL << ID_AA64MMFR1_LOR_SHIFT);
         }
 
         return val;
@@ -1338,11 +1350,11 @@ static const struct sys_reg_desc sys_reg_descs[] = {
         { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
         { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
 
-        { SYS_DESC(SYS_LORSA_EL1), trap_undef },
-        { SYS_DESC(SYS_LOREA_EL1), trap_undef },
-        { SYS_DESC(SYS_LORN_EL1), trap_undef },
-        { SYS_DESC(SYS_LORC_EL1), trap_undef },
-        { SYS_DESC(SYS_LORID_EL1), trap_undef },
+        { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
+        { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
+        { SYS_DESC(SYS_LORN_EL1), trap_loregion },
+        { SYS_DESC(SYS_LORC_EL1), trap_loregion },
+        { SYS_DESC(SYS_LORID_EL1), trap_loregion },
 
         { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
         { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
@@ -2596,7 +2608,9 @@ void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
         table = get_target_table(vcpu->arch.target, true, &num);
         reset_sys_reg_descs(vcpu, table, num);
 
-        for (num = 1; num < NR_SYS_REGS; num++)
-                if (__vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
-                        panic("Didn't reset __vcpu_sys_reg(%zi)", num);
+        for (num = 1; num < NR_SYS_REGS; num++) {
+                if (WARN(__vcpu_sys_reg(vcpu, num) == 0x4242424242424242,
+                         "Didn't reset __vcpu_sys_reg(%zi)\n", num))
+                        break;
+        }
 }
diff --git a/arch/csky/include/asm/pgtable.h b/arch/csky/include/asm/pgtable.h
index edfcbb25fd9f..dcea277c09ae 100644
--- a/arch/csky/include/asm/pgtable.h
+++ b/arch/csky/include/asm/pgtable.h
@@ -45,8 +45,8 @@
         ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset_t(address))
 #define pmd_page(pmd)   (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
 #define pte_clear(mm, addr, ptep)       set_pte((ptep), \
-                        (((unsigned int)addr&0x80000000)?__pte(1):__pte(0)))
-#define pte_none(pte)   (!(pte_val(pte)&0xfffffffe))
+        (((unsigned int) addr & PAGE_OFFSET) ? __pte(_PAGE_GLOBAL) : __pte(0)))
+#define pte_none(pte)           (!(pte_val(pte) & ~_PAGE_GLOBAL))
 #define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
 #define pte_pfn(x)      ((unsigned long)((x).pte_low >> PAGE_SHIFT))
 #define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) \
@@ -241,6 +241,11 @@ static inline pte_t pte_mkyoung(pte_t pte)
 
 #define pgd_index(address)      ((address) >> PGDIR_SHIFT)
 
+#define __HAVE_PHYS_MEM_ACCESS_PROT
+struct file;
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+                                     unsigned long size, pgprot_t vma_prot);
+
 /*
  * Macro to make mark a page protection value as "uncacheable".  Note
  * that "protection" is really a misnomer here as the protection value
diff --git a/arch/csky/include/asm/processor.h b/arch/csky/include/asm/processor.h
index 8f454810514f..21e0bd5293dd 100644
--- a/arch/csky/include/asm/processor.h
+++ b/arch/csky/include/asm/processor.h
@@ -49,7 +49,7 @@ struct thread_struct {
 };
 
 #define INIT_THREAD  { \
-        .ksp = (unsigned long) init_thread_union.stack + THREAD_SIZE, \
+        .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
         .sr = DEFAULT_PSR_VALUE, \
 }
 
@@ -95,7 +95,7 @@ unsigned long get_wchan(struct task_struct *p);
 #define KSTK_ESP(tsk)           (task_pt_regs(tsk)->usp)
 
 #define task_pt_regs(p) \
-        ((struct pt_regs *)(THREAD_SIZE + p->stack) - 1)
+        ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
 
 #define cpu_relax() barrier()
 
diff --git a/arch/csky/kernel/dumpstack.c b/arch/csky/kernel/dumpstack.c
index 659253e9989c..d67f9777cfd9 100644
--- a/arch/csky/kernel/dumpstack.c
+++ b/arch/csky/kernel/dumpstack.c
@@ -38,7 +38,11 @@ void show_stack(struct task_struct *task, unsigned long *stack)
                 if (task)
                         stack = (unsigned long *)thread_saved_fp(task);
                 else
+#ifdef CONFIG_STACKTRACE
+                        asm volatile("mov %0, r8\n":"=r"(stack)::"memory");
+#else
                         stack = (unsigned long *)&stack;
+#endif
         }
 
         show_trace(stack);
diff --git a/arch/csky/kernel/ptrace.c b/arch/csky/kernel/ptrace.c
index 57f1afe19a52..f2f12fff36f7 100644
--- a/arch/csky/kernel/ptrace.c
+++ b/arch/csky/kernel/ptrace.c
@@ -8,6 +8,7 @@
 #include <linux/ptrace.h>
 #include <linux/regset.h>
 #include <linux/sched.h>
+#include <linux/sched/task_stack.h>
 #include <linux/signal.h>
 #include <linux/smp.h>
 #include <linux/uaccess.h>
@@ -159,7 +160,7 @@ static int fpr_set(struct task_struct *target,
 static const struct user_regset csky_regsets[] = {
         [REGSET_GPR] = {
                 .core_note_type = NT_PRSTATUS,
-                .n = ELF_NGREG,
+                .n = sizeof(struct pt_regs) / sizeof(u32),
                 .size = sizeof(u32),
                 .align = sizeof(u32),
                 .get = &gpr_get,
diff --git a/arch/csky/kernel/smp.c b/arch/csky/kernel/smp.c
index ddc4dd79f282..b07a534b3062 100644
--- a/arch/csky/kernel/smp.c
+++ b/arch/csky/kernel/smp.c
@@ -160,7 +160,8 @@ int __cpu_up(unsigned int cpu, struct task_struct *tidle)
 {
         unsigned long mask = 1 << cpu;
 
-        secondary_stack = (unsigned int)tidle->stack + THREAD_SIZE - 8;
+        secondary_stack =
+                (unsigned int) task_stack_page(tidle) + THREAD_SIZE - 8;
         secondary_hint = mfcr("cr31");
         secondary_ccr  = mfcr("cr18");
 
diff --git a/arch/csky/mm/ioremap.c b/arch/csky/mm/ioremap.c
index cb7c03e5cd21..8473b6bdf512 100644
--- a/arch/csky/mm/ioremap.c
+++ b/arch/csky/mm/ioremap.c
@@ -46,3 +46,17 @@ void iounmap(void __iomem *addr)
         vunmap((void *)((unsigned long)addr & PAGE_MASK));
 }
 EXPORT_SYMBOL(iounmap);
+
+pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+                              unsigned long size, pgprot_t vma_prot)
+{
+        if (!pfn_valid(pfn)) {
+                vma_prot.pgprot |= _PAGE_SO;
+                return pgprot_noncached(vma_prot);
+        } else if (file->f_flags & O_SYNC) {
+                return pgprot_noncached(vma_prot);
+        }
+
+        return vma_prot;
+}
+EXPORT_SYMBOL(phys_mem_access_prot);
diff --git a/arch/mips/net/ebpf_jit.c b/arch/mips/net/ebpf_jit.c
index b16710a8a9e7..76e9bf88d3b9 100644
--- a/arch/mips/net/ebpf_jit.c
+++ b/arch/mips/net/ebpf_jit.c
@@ -79,8 +79,6 @@ enum reg_val_type {
         REG_64BIT_32BIT,
         /* 32-bit compatible, need truncation for 64-bit ops. */
         REG_32BIT,
-        /* 32-bit zero extended. */
-        REG_32BIT_ZERO_EX,
         /* 32-bit no sign/zero extension needed. */
         REG_32BIT_POS
 };
@@ -343,12 +341,15 @@ static int build_int_epilogue(struct jit_ctx *ctx, int dest_reg)
         const struct bpf_prog *prog = ctx->skf;
         int stack_adjust = ctx->stack_size;
         int store_offset = stack_adjust - 8;
+        enum reg_val_type td;
         int r0 = MIPS_R_V0;
 
-        if (dest_reg == MIPS_R_RA &&
-            get_reg_val_type(ctx, prog->len, BPF_REG_0) == REG_32BIT_ZERO_EX)
+        if (dest_reg == MIPS_R_RA) {
                 /* Don't let zero extended value escape. */
-                emit_instr(ctx, sll, r0, r0, 0);
+                td = get_reg_val_type(ctx, prog->len, BPF_REG_0);
+                if (td == REG_64BIT)
+                        emit_instr(ctx, sll, r0, r0, 0);
+        }
 
         if (ctx->flags & EBPF_SAVE_RA) {
                 emit_instr(ctx, ld, MIPS_R_RA, store_offset, MIPS_R_SP);
@@ -692,7 +693,7 @@ static int build_one_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
                 if (dst < 0)
                         return dst;
                 td = get_reg_val_type(ctx, this_idx, insn->dst_reg);
-                if (td == REG_64BIT || td == REG_32BIT_ZERO_EX) {
+                if (td == REG_64BIT) {
                         /* sign extend */
                         emit_instr(ctx, sll, dst, dst, 0);
                 }
@@ -707,7 +708,7 @@ static int build_one_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
                 if (dst < 0)
                         return dst;
                 td = get_reg_val_type(ctx, this_idx, insn->dst_reg);
-                if (td == REG_64BIT || td == REG_32BIT_ZERO_EX) {
+                if (td == REG_64BIT) {
                         /* sign extend */
                         emit_instr(ctx, sll, dst, dst, 0);
                 }
@@ -721,7 +722,7 @@ static int build_one_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
                 if (dst < 0)
                         return dst;
                 td = get_reg_val_type(ctx, this_idx, insn->dst_reg);
-                if (td == REG_64BIT || td == REG_32BIT_ZERO_EX)
+                if (td == REG_64BIT)
                         /* sign extend */
                         emit_instr(ctx, sll, dst, dst, 0);
                 if (insn->imm == 1) {
@@ -860,13 +861,13 @@ static int build_one_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
                 if (src < 0 || dst < 0)
                         return -EINVAL;
                 td = get_reg_val_type(ctx, this_idx, insn->dst_reg);
-                if (td == REG_64BIT || td == REG_32BIT_ZERO_EX) {
+                if (td == REG_64BIT) {
                         /* sign extend */
                         emit_instr(ctx, sll, dst, dst, 0);
                 }
                 did_move = false;
                 ts = get_reg_val_type(ctx, this_idx, insn->src_reg);
-                if (ts == REG_64BIT || ts == REG_32BIT_ZERO_EX) {
+                if (ts == REG_64BIT) {
                         int tmp_reg = MIPS_R_AT;
 
                         if (bpf_op == BPF_MOV) {
@@ -1254,8 +1255,7 @@ jeq_common:
                 if (insn->imm == 64 && td == REG_32BIT)
                         emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32);
 
-                if (insn->imm != 64 &&
-                    (td == REG_64BIT || td == REG_32BIT_ZERO_EX)) {
+                if (insn->imm != 64 && td == REG_64BIT) {
                         /* sign extend */
                         emit_instr(ctx, sll, dst, dst, 0);
                 }
diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h
index c9bfe526ca9d..d8c8d7c9df15 100644
--- a/arch/powerpc/include/asm/book3s/64/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/64/pgtable.h
@@ -904,7 +904,7 @@ static inline int pud_none(pud_t pud)
 
 static inline int pud_present(pud_t pud)
 {
-        return (pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT));
+        return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT));
 }
 
 extern struct page *pud_page(pud_t pud);
@@ -951,7 +951,7 @@ static inline int pgd_none(pgd_t pgd)
 
 static inline int pgd_present(pgd_t pgd)
 {
-        return (pgd_raw(pgd) & cpu_to_be64(_PAGE_PRESENT));
+        return !!(pgd_raw(pgd) & cpu_to_be64(_PAGE_PRESENT));
 }
 
 static inline pte_t pgd_pte(pgd_t pgd)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 374a19712e20..b684f0294f35 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -2278,6 +2278,19 @@ void perf_check_microcode(void)
                 x86_pmu.check_microcode();
 }
 
+static int x86_pmu_check_period(struct perf_event *event, u64 value)
+{
+        if (x86_pmu.check_period && x86_pmu.check_period(event, value))
+                return -EINVAL;
+
+        if (value && x86_pmu.limit_period) {
+                if (x86_pmu.limit_period(event, value) > value)
+                        return -EINVAL;
+        }
+
+        return 0;
+}
+
 static struct pmu pmu = {
         .pmu_enable             = x86_pmu_enable,
         .pmu_disable            = x86_pmu_disable,
@@ -2302,6 +2315,7 @@ static struct pmu pmu = {
         .event_idx              = x86_pmu_event_idx,
         .sched_task             = x86_pmu_sched_task,
         .task_ctx_size          = sizeof(struct x86_perf_task_context),
+        .check_period           = x86_pmu_check_period,
 };
 
 void arch_perf_update_userpage(struct perf_event *event,
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index daafb893449b..730978dff63f 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3587,6 +3587,11 @@ static void intel_pmu_sched_task(struct perf_event_context *ctx,
         intel_pmu_lbr_sched_task(ctx, sched_in);
 }
 
+static int intel_pmu_check_period(struct perf_event *event, u64 value)
+{
+        return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
+}
+
 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
 
 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
@@ -3667,6 +3672,8 @@ static __initconst const struct x86_pmu core_pmu = {
         .cpu_starting           = intel_pmu_cpu_starting,
         .cpu_dying              = intel_pmu_cpu_dying,
         .cpu_dead               = intel_pmu_cpu_dead,
+
+        .check_period           = intel_pmu_check_period,
 };
 
 static struct attribute *intel_pmu_attrs[];
@@ -3711,6 +3718,8 @@ static __initconst const struct x86_pmu intel_pmu = {
 
         .guest_get_msrs         = intel_guest_get_msrs,
         .sched_task             = intel_pmu_sched_task,
+
+        .check_period           = intel_pmu_check_period,
 };
 
 static __init void intel_clovertown_quirk(void)
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 78d7b7031bfc..d46fd6754d92 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -646,6 +646,11 @@ struct x86_pmu {
          * Intel host/guest support (KVM)
          */
         struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
+
+        /*
+         * Check period value for PERF_EVENT_IOC_PERIOD ioctl.
+         */
+        int (*check_period) (struct perf_event *event, u64 period);
 };
 
 struct x86_perf_task_context {
@@ -857,7 +862,7 @@ static inline int amd_pmu_init(void)
 
 #ifdef CONFIG_CPU_SUP_INTEL
 
-static inline bool intel_pmu_has_bts(struct perf_event *event)
+static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period)
 {
         struct hw_perf_event *hwc = &event->hw;
         unsigned int hw_event, bts_event;
@@ -868,7 +873,14 @@ static inline bool intel_pmu_has_bts(struct perf_event *event)
         hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
         bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
 
-        return hw_event == bts_event && hwc->sample_period == 1;
+        return hw_event == bts_event && period == 1;
+}
+
+static inline bool intel_pmu_has_bts(struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+
+        return intel_pmu_has_bts_period(event, hwc->sample_period);
 }
 
 int intel_pmu_save_and_restart(struct perf_event *event);
diff --git a/arch/x86/ia32/ia32_aout.c b/arch/x86/ia32/ia32_aout.c
index f65b78d32f5e..7dbbe9ffda17 100644
--- a/arch/x86/ia32/ia32_aout.c
+++ b/arch/x86/ia32/ia32_aout.c
@@ -51,7 +51,7 @@ static unsigned long get_dr(int n)
 /*
  * fill in the user structure for a core dump..
  */
-static void dump_thread32(struct pt_regs *regs, struct user32 *dump)
+static void fill_dump(struct pt_regs *regs, struct user32 *dump)
 {
         u32 fs, gs;
         memset(dump, 0, sizeof(*dump));
@@ -157,10 +157,12 @@ static int aout_core_dump(struct coredump_params *cprm)
         fs = get_fs();
         set_fs(KERNEL_DS);
         has_dumped = 1;
+
+        fill_dump(cprm->regs, &dump);
+
         strncpy(dump.u_comm, current->comm, sizeof(current->comm));
         dump.u_ar0 = offsetof(struct user32, regs);
         dump.signal = cprm->siginfo->si_signo;
-        dump_thread32(cprm->regs, &dump);
 
         /*
          * If the size of the dump file exceeds the rlimit, then see
diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index d9a9993af882..9f15384c504a 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -52,6 +52,8 @@
 
 #define INTEL_FAM6_CANNONLAKE_MOBILE    0x66
 
+#define INTEL_FAM6_ICELAKE_MOBILE       0x7E
+
 /* "Small Core" Processors (Atom) */
 
 #define INTEL_FAM6_ATOM_BONNELL         0x1C /* Diamondville, Pineview */
diff --git a/arch/x86/include/asm/uv/bios.h b/arch/x86/include/asm/uv/bios.h
index e652a7cc6186..3f697a9e3f59 100644
--- a/arch/x86/include/asm/uv/bios.h
+++ b/arch/x86/include/asm/uv/bios.h
@@ -48,7 +48,8 @@ enum {
         BIOS_STATUS_SUCCESS             =  0,
         BIOS_STATUS_UNIMPLEMENTED       = -ENOSYS,
         BIOS_STATUS_EINVAL              = -EINVAL,
-        BIOS_STATUS_UNAVAIL             = -EBUSY
+        BIOS_STATUS_UNAVAIL             = -EBUSY,
+        BIOS_STATUS_ABORT               = -EINTR,
 };
 
 /* Address map parameters */
@@ -167,4 +168,9 @@ extern long system_serial_number;
 
 extern struct kobject *sgi_uv_kobj;     /* /sys/firmware/sgi_uv */
 
+/*
+ * EFI runtime lock; cf. firmware/efi/runtime-wrappers.c for details
+ */
+extern struct semaphore __efi_uv_runtime_lock;
+
 #endif /* _ASM_X86_UV_BIOS_H */
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index d8ea4ebd79e7..d737a51a53ca 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -2473,6 +2473,10 @@ static int nested_check_vm_execution_controls(struct kvm_vcpu *vcpu,
             (nested_cpu_has_vpid(vmcs12) && !vmcs12->virtual_processor_id))
                 return -EINVAL;
 
+        if (!nested_cpu_has_preemption_timer(vmcs12) &&
+            nested_cpu_has_save_preemption_timer(vmcs12))
+                return -EINVAL;
+
         if (nested_cpu_has_ept(vmcs12) &&
             !valid_ept_address(vcpu, vmcs12->ept_pointer))
                 return -EINVAL;
@@ -5557,9 +5561,11 @@ void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps,
          * secondary cpu-based controls.  Do not include those that
          * depend on CPUID bits, they are added later by vmx_cpuid_update.
          */
-        rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
-                msrs->secondary_ctls_low,
-                msrs->secondary_ctls_high);
+        if (msrs->procbased_ctls_high & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)
+                rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
+                      msrs->secondary_ctls_low,
+                      msrs->secondary_ctls_high);
+
         msrs->secondary_ctls_low = 0;
         msrs->secondary_ctls_high &=
                 SECONDARY_EXEC_DESC |
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 95d618045001..30a6bcd735ec 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -863,7 +863,8 @@ static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
         if (!entry_only)
                 j = find_msr(&m->host, msr);
 
-        if (i == NR_AUTOLOAD_MSRS || j == NR_AUTOLOAD_MSRS) {
+        if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) ||
+                (j < 0 &&  m->host.nr == NR_AUTOLOAD_MSRS)) {
                 printk_once(KERN_WARNING "Not enough msr switch entries. "
                                 "Can't add msr %x\n", msr);
                 return;
@@ -1193,21 +1194,6 @@ static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
                 return;
 
-        /*
-         * First handle the simple case where no cmpxchg is necessary; just
-         * allow posting non-urgent interrupts.
-         *
-         * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
-         * PI.NDST: pi_post_block will do it for us and the wakeup_handler
-         * expects the VCPU to be on the blocked_vcpu_list that matches
-         * PI.NDST.
-         */
-        if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
-            vcpu->cpu == cpu) {
-                pi_clear_sn(pi_desc);
-                return;
-        }
-
         /* The full case.  */
         do {
                 old.control = new.control = pi_desc->control;
@@ -1222,6 +1208,17 @@ static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
                 new.sn = 0;
         } while (cmpxchg64(&pi_desc->control, old.control,
                            new.control) != old.control);
+
+        /*
+         * Clear SN before reading the bitmap.  The VT-d firmware
+         * writes the bitmap and reads SN atomically (5.2.3 in the
+         * spec), so it doesn't really have a memory barrier that
+         * pairs with this, but we cannot do that and we need one.
+         */
+        smp_mb__after_atomic();
+
+        if (!bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS))
+                pi_set_on(pi_desc);
 }
 
 /*
diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h
index 99328954c2fc..0ac0a64c7790 100644
--- a/arch/x86/kvm/vmx/vmx.h
+++ b/arch/x86/kvm/vmx/vmx.h
@@ -337,16 +337,16 @@ static inline int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 }
 
-static inline void pi_clear_sn(struct pi_desc *pi_desc)
+static inline void pi_set_sn(struct pi_desc *pi_desc)
 {
-        return clear_bit(POSTED_INTR_SN,
+        return set_bit(POSTED_INTR_SN,
                         (unsigned long *)&pi_desc->control);
 }
 
-static inline void pi_set_sn(struct pi_desc *pi_desc)
+static inline void pi_set_on(struct pi_desc *pi_desc)
 {
-        return set_bit(POSTED_INTR_SN,
-                        (unsigned long *)&pi_desc->control);
+        set_bit(POSTED_INTR_ON,
+                (unsigned long *)&pi_desc->control);
 }
 
 static inline void pi_clear_on(struct pi_desc *pi_desc)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index e67ecf25e690..941f932373d0 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -7801,7 +7801,7 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
          * 1) We should set ->mode before checking ->requests.  Please see
          * the comment in kvm_vcpu_exiting_guest_mode().
          *
-         * 2) For APICv, we should set ->mode before checking PIR.ON.  This
+         * 2) For APICv, we should set ->mode before checking PID.ON. This
          * pairs with the memory barrier implicit in pi_test_and_set_on
          * (see vmx_deliver_posted_interrupt).
          *
diff --git a/arch/x86/platform/uv/bios_uv.c b/arch/x86/platform/uv/bios_uv.c
index 4a6a5a26c582..eb33432f2f24 100644
--- a/arch/x86/platform/uv/bios_uv.c
+++ b/arch/x86/platform/uv/bios_uv.c
@@ -29,7 +29,8 @@
 
 struct uv_systab *uv_systab;
 
-s64 uv_bios_call(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3, u64 a4, u64 a5)
+static s64 __uv_bios_call(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3,
+                        u64 a4, u64 a5)
 {
         struct uv_systab *tab = uv_systab;
         s64 ret;
@@ -51,6 +52,19 @@ s64 uv_bios_call(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3, u64 a4, u64 a5)
 
         return ret;
 }
+
+s64 uv_bios_call(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3, u64 a4, u64 a5)
+{
+        s64 ret;
+
+        if (down_interruptible(&__efi_uv_runtime_lock))
+                return BIOS_STATUS_ABORT;
+
+        ret = __uv_bios_call(which, a1, a2, a3, a4, a5);
+        up(&__efi_uv_runtime_lock);
+
+        return ret;
+}
 EXPORT_SYMBOL_GPL(uv_bios_call);
 
 s64 uv_bios_call_irqsave(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3,
@@ -59,10 +73,15 @@ s64 uv_bios_call_irqsave(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3,
         unsigned long bios_flags;
         s64 ret;
 
+        if (down_interruptible(&__efi_uv_runtime_lock))
+                return BIOS_STATUS_ABORT;
+
         local_irq_save(bios_flags);
-        ret = uv_bios_call(which, a1, a2, a3, a4, a5);
+        ret = __uv_bios_call(which, a1, a2, a3, a4, a5);
         local_irq_restore(bios_flags);
 
+        up(&__efi_uv_runtime_lock);
+
         return ret;
 }