diff options
author | Paul Burton <paul.burton@imgtec.com> | 2016-05-06 09:36:23 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2016-05-13 08:02:20 -0400 |
commit | 4edf00a46bee692f62578b5280c5774f9b65a08f (patch) | |
tree | 3536ce8de630a22e4ff20be455e95ab202bfc436 /arch/mips/lib/dump_tlb.c | |
parent | f1b711c638c7df56112eff8e9661c91202782516 (diff) |
MIPS: Retrieve ASID masks using function accepting struct cpuinfo_mips
In preparation for supporting variable ASID masks, retrieve ASID masks
using functions in asm/cpu-info.h which accept struct cpuinfo_mips. This
will allow those functions to determine the ASID mask based upon the CPU
in a later patch. This also allows for the r3k & r8k cases to be handled
in Kconfig, which is arguably cleaner than the previous #ifdefs.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13210/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/lib/dump_tlb.c')
-rw-r--r-- | arch/mips/lib/dump_tlb.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c index 92a37319efbe..3283aa7423e4 100644 --- a/arch/mips/lib/dump_tlb.c +++ b/arch/mips/lib/dump_tlb.c | |||
@@ -73,6 +73,8 @@ static void dump_tlb(int first, int last) | |||
73 | unsigned long s_entryhi, entryhi, asid; | 73 | unsigned long s_entryhi, entryhi, asid; |
74 | unsigned long long entrylo0, entrylo1, pa; | 74 | unsigned long long entrylo0, entrylo1, pa; |
75 | unsigned int s_index, s_pagemask, pagemask, c0, c1, i; | 75 | unsigned int s_index, s_pagemask, pagemask, c0, c1, i; |
76 | unsigned long asidmask = cpu_asid_mask(¤t_cpu_data); | ||
77 | int asidwidth = DIV_ROUND_UP(ilog2(asidmask) + 1, 4); | ||
76 | #ifdef CONFIG_32BIT | 78 | #ifdef CONFIG_32BIT |
77 | bool xpa = cpu_has_xpa && (read_c0_pagegrain() & PG_ELPA); | 79 | bool xpa = cpu_has_xpa && (read_c0_pagegrain() & PG_ELPA); |
78 | int pwidth = xpa ? 11 : 8; | 80 | int pwidth = xpa ? 11 : 8; |
@@ -86,7 +88,7 @@ static void dump_tlb(int first, int last) | |||
86 | s_pagemask = read_c0_pagemask(); | 88 | s_pagemask = read_c0_pagemask(); |
87 | s_entryhi = read_c0_entryhi(); | 89 | s_entryhi = read_c0_entryhi(); |
88 | s_index = read_c0_index(); | 90 | s_index = read_c0_index(); |
89 | asid = s_entryhi & 0xff; | 91 | asid = s_entryhi & asidmask; |
90 | 92 | ||
91 | for (i = first; i <= last; i++) { | 93 | for (i = first; i <= last; i++) { |
92 | write_c0_index(i); | 94 | write_c0_index(i); |
@@ -115,7 +117,7 @@ static void dump_tlb(int first, int last) | |||
115 | * due to duplicate TLB entry. | 117 | * due to duplicate TLB entry. |
116 | */ | 118 | */ |
117 | if (!((entrylo0 | entrylo1) & ENTRYLO_G) && | 119 | if (!((entrylo0 | entrylo1) & ENTRYLO_G) && |
118 | (entryhi & 0xff) != asid) | 120 | (entryhi & asidmask) != asid) |
119 | continue; | 121 | continue; |
120 | 122 | ||
121 | /* | 123 | /* |
@@ -126,9 +128,9 @@ static void dump_tlb(int first, int last) | |||
126 | c0 = (entrylo0 & ENTRYLO_C) >> ENTRYLO_C_SHIFT; | 128 | c0 = (entrylo0 & ENTRYLO_C) >> ENTRYLO_C_SHIFT; |
127 | c1 = (entrylo1 & ENTRYLO_C) >> ENTRYLO_C_SHIFT; | 129 | c1 = (entrylo1 & ENTRYLO_C) >> ENTRYLO_C_SHIFT; |
128 | 130 | ||
129 | printk("va=%0*lx asid=%02lx\n", | 131 | printk("va=%0*lx asid=%0*lx\n", |
130 | vwidth, (entryhi & ~0x1fffUL), | 132 | vwidth, (entryhi & ~0x1fffUL), |
131 | entryhi & 0xff); | 133 | asidwidth, entryhi & asidmask); |
132 | /* RI/XI are in awkward places, so mask them off separately */ | 134 | /* RI/XI are in awkward places, so mask them off separately */ |
133 | pa = entrylo0 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI); | 135 | pa = entrylo0 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI); |
134 | if (xpa) | 136 | if (xpa) |