diff options
-rw-r--r-- | arch/mips/Kconfig | 11 | ||||
-rw-r--r-- | arch/mips/include/asm/cpu-info.h | 10 | ||||
-rw-r--r-- | arch/mips/include/asm/mmu_context.h | 41 | ||||
-rw-r--r-- | arch/mips/kernel/traps.c | 2 | ||||
-rw-r--r-- | arch/mips/kvm/tlb.c | 30 | ||||
-rw-r--r-- | arch/mips/lib/dump_tlb.c | 10 | ||||
-rw-r--r-- | arch/mips/lib/r3k_dump_tlb.c | 9 | ||||
-rw-r--r-- | arch/mips/mm/tlb-r3k.c | 24 | ||||
-rw-r--r-- | arch/mips/mm/tlb-r4k.c | 2 | ||||
-rw-r--r-- | arch/mips/mm/tlb-r8k.c | 2 |
10 files changed, 86 insertions, 55 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 95f05826a16f..0cab0da2ab55 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig | |||
@@ -2449,6 +2449,17 @@ config CPU_R4000_WORKAROUNDS | |||
2449 | config CPU_R4400_WORKAROUNDS | 2449 | config CPU_R4400_WORKAROUNDS |
2450 | bool | 2450 | bool |
2451 | 2451 | ||
2452 | config MIPS_ASID_SHIFT | ||
2453 | int | ||
2454 | default 6 if CPU_R3000 || CPU_TX39XX | ||
2455 | default 4 if CPU_R8000 | ||
2456 | default 0 | ||
2457 | |||
2458 | config MIPS_ASID_BITS | ||
2459 | int | ||
2460 | default 6 if CPU_R3000 || CPU_TX39XX | ||
2461 | default 8 | ||
2462 | |||
2452 | # | 2463 | # |
2453 | # - Highmem only makes sense for the 32-bit kernel. | 2464 | # - Highmem only makes sense for the 32-bit kernel. |
2454 | # - The current highmem code will only work properly on physically indexed | 2465 | # - The current highmem code will only work properly on physically indexed |
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h index b090aa51d644..1ae26a393153 100644 --- a/arch/mips/include/asm/cpu-info.h +++ b/arch/mips/include/asm/cpu-info.h | |||
@@ -132,4 +132,14 @@ struct proc_cpuinfo_notifier_args { | |||
132 | # define cpu_vpe_id(cpuinfo) ({ (void)cpuinfo; 0; }) | 132 | # define cpu_vpe_id(cpuinfo) ({ (void)cpuinfo; 0; }) |
133 | #endif | 133 | #endif |
134 | 134 | ||
135 | static inline unsigned long cpu_asid_inc(void) | ||
136 | { | ||
137 | return 1 << CONFIG_MIPS_ASID_SHIFT; | ||
138 | } | ||
139 | |||
140 | static inline unsigned long cpu_asid_mask(struct cpuinfo_mips *cpuinfo) | ||
141 | { | ||
142 | return ((1 << CONFIG_MIPS_ASID_BITS) - 1) << CONFIG_MIPS_ASID_SHIFT; | ||
143 | } | ||
144 | |||
135 | #endif /* __ASM_CPU_INFO_H */ | 145 | #endif /* __ASM_CPU_INFO_H */ |
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index 45914b59824c..fc57e135cb0a 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h | |||
@@ -65,37 +65,32 @@ extern unsigned long pgd_current[]; | |||
65 | back_to_back_c0_hazard(); \ | 65 | back_to_back_c0_hazard(); \ |
66 | TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) | 66 | TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) |
67 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ | 67 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ |
68 | #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) | ||
69 | 68 | ||
70 | #define ASID_INC 0x40 | 69 | /* |
71 | #define ASID_MASK 0xfc0 | 70 | * All unused by hardware upper bits will be considered |
72 | 71 | * as a software asid extension. | |
73 | #elif defined(CONFIG_CPU_R8000) | 72 | */ |
74 | 73 | static unsigned long asid_version_mask(unsigned int cpu) | |
75 | #define ASID_INC 0x10 | 74 | { |
76 | #define ASID_MASK 0xff0 | 75 | unsigned long asid_mask = cpu_asid_mask(&cpu_data[cpu]); |
77 | |||
78 | #else /* FIXME: not correct for R6000 */ | ||
79 | 76 | ||
80 | #define ASID_INC 0x1 | 77 | return ~(asid_mask | (asid_mask - 1)); |
81 | #define ASID_MASK 0xff | 78 | } |
82 | 79 | ||
83 | #endif | 80 | static unsigned long asid_first_version(unsigned int cpu) |
81 | { | ||
82 | return ~asid_version_mask(cpu) + 1; | ||
83 | } | ||
84 | 84 | ||
85 | #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) | 85 | #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) |
86 | #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) | ||
87 | #define asid_cache(cpu) (cpu_data[cpu].asid_cache) | 86 | #define asid_cache(cpu) (cpu_data[cpu].asid_cache) |
87 | #define cpu_asid(cpu, mm) \ | ||
88 | (cpu_context((cpu), (mm)) & cpu_asid_mask(&cpu_data[cpu])) | ||
88 | 89 | ||
89 | static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) | 90 | static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) |
90 | { | 91 | { |
91 | } | 92 | } |
92 | 93 | ||
93 | /* | ||
94 | * All unused by hardware upper bits will be considered | ||
95 | * as a software asid extension. | ||
96 | */ | ||
97 | #define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1))) | ||
98 | #define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1) | ||
99 | 94 | ||
100 | /* Normal, classic MIPS get_new_mmu_context */ | 95 | /* Normal, classic MIPS get_new_mmu_context */ |
101 | static inline void | 96 | static inline void |
@@ -104,7 +99,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) | |||
104 | extern void kvm_local_flush_tlb_all(void); | 99 | extern void kvm_local_flush_tlb_all(void); |
105 | unsigned long asid = asid_cache(cpu); | 100 | unsigned long asid = asid_cache(cpu); |
106 | 101 | ||
107 | if (! ((asid += ASID_INC) & ASID_MASK) ) { | 102 | if (!((asid += cpu_asid_inc()) & cpu_asid_mask(&cpu_data[cpu]))) { |
108 | if (cpu_has_vtag_icache) | 103 | if (cpu_has_vtag_icache) |
109 | flush_icache_all(); | 104 | flush_icache_all(); |
110 | #ifdef CONFIG_KVM | 105 | #ifdef CONFIG_KVM |
@@ -113,7 +108,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) | |||
113 | local_flush_tlb_all(); /* start new asid cycle */ | 108 | local_flush_tlb_all(); /* start new asid cycle */ |
114 | #endif | 109 | #endif |
115 | if (!asid) /* fix version if needed */ | 110 | if (!asid) /* fix version if needed */ |
116 | asid = ASID_FIRST_VERSION; | 111 | asid = asid_first_version(cpu); |
117 | } | 112 | } |
118 | 113 | ||
119 | cpu_context(cpu, mm) = asid_cache(cpu) = asid; | 114 | cpu_context(cpu, mm) = asid_cache(cpu) = asid; |
@@ -145,7 +140,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, | |||
145 | 140 | ||
146 | htw_stop(); | 141 | htw_stop(); |
147 | /* Check if our ASID is of an older version and thus invalid */ | 142 | /* Check if our ASID is of an older version and thus invalid */ |
148 | if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK) | 143 | if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & asid_version_mask(cpu)) |
149 | get_new_mmu_context(next, cpu); | 144 | get_new_mmu_context(next, cpu); |
150 | write_c0_entryhi(cpu_asid(cpu, next)); | 145 | write_c0_entryhi(cpu_asid(cpu, next)); |
151 | TLBMISS_HANDLER_SETUP_PGD(next->pgd); | 146 | TLBMISS_HANDLER_SETUP_PGD(next->pgd); |
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index f586b8b23f60..56f4161b98b9 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c | |||
@@ -2136,7 +2136,7 @@ void per_cpu_trap_init(bool is_boot_cpu) | |||
2136 | } | 2136 | } |
2137 | 2137 | ||
2138 | if (!cpu_data[cpu].asid_cache) | 2138 | if (!cpu_data[cpu].asid_cache) |
2139 | cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; | 2139 | cpu_data[cpu].asid_cache = asid_first_version(cpu); |
2140 | 2140 | ||
2141 | atomic_inc(&init_mm.mm_count); | 2141 | atomic_inc(&init_mm.mm_count); |
2142 | current->active_mm = &init_mm; | 2142 | current->active_mm = &init_mm; |
diff --git a/arch/mips/kvm/tlb.c b/arch/mips/kvm/tlb.c index 52d87280f865..b9c52c1d35d6 100644 --- a/arch/mips/kvm/tlb.c +++ b/arch/mips/kvm/tlb.c | |||
@@ -49,12 +49,18 @@ EXPORT_SYMBOL_GPL(kvm_mips_is_error_pfn); | |||
49 | 49 | ||
50 | uint32_t kvm_mips_get_kernel_asid(struct kvm_vcpu *vcpu) | 50 | uint32_t kvm_mips_get_kernel_asid(struct kvm_vcpu *vcpu) |
51 | { | 51 | { |
52 | return vcpu->arch.guest_kernel_asid[smp_processor_id()] & ASID_MASK; | 52 | int cpu = smp_processor_id(); |
53 | |||
54 | return vcpu->arch.guest_kernel_asid[cpu] & | ||
55 | cpu_asid_mask(&cpu_data[cpu]); | ||
53 | } | 56 | } |
54 | 57 | ||
55 | uint32_t kvm_mips_get_user_asid(struct kvm_vcpu *vcpu) | 58 | uint32_t kvm_mips_get_user_asid(struct kvm_vcpu *vcpu) |
56 | { | 59 | { |
57 | return vcpu->arch.guest_user_asid[smp_processor_id()] & ASID_MASK; | 60 | int cpu = smp_processor_id(); |
61 | |||
62 | return vcpu->arch.guest_user_asid[cpu] & | ||
63 | cpu_asid_mask(&cpu_data[cpu]); | ||
58 | } | 64 | } |
59 | 65 | ||
60 | inline uint32_t kvm_mips_get_commpage_asid(struct kvm_vcpu *vcpu) | 66 | inline uint32_t kvm_mips_get_commpage_asid(struct kvm_vcpu *vcpu) |
@@ -78,7 +84,8 @@ void kvm_mips_dump_host_tlbs(void) | |||
78 | old_pagemask = read_c0_pagemask(); | 84 | old_pagemask = read_c0_pagemask(); |
79 | 85 | ||
80 | kvm_info("HOST TLBs:\n"); | 86 | kvm_info("HOST TLBs:\n"); |
81 | kvm_info("ASID: %#lx\n", read_c0_entryhi() & ASID_MASK); | 87 | kvm_info("ASID: %#lx\n", read_c0_entryhi() & |
88 | cpu_asid_mask(¤t_cpu_data)); | ||
82 | 89 | ||
83 | for (i = 0; i < current_cpu_data.tlbsize; i++) { | 90 | for (i = 0; i < current_cpu_data.tlbsize; i++) { |
84 | write_c0_index(i); | 91 | write_c0_index(i); |
@@ -564,15 +571,15 @@ void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu, | |||
564 | { | 571 | { |
565 | unsigned long asid = asid_cache(cpu); | 572 | unsigned long asid = asid_cache(cpu); |
566 | 573 | ||
567 | asid += ASID_INC; | 574 | asid += cpu_asid_inc(); |
568 | if (!(asid & ASID_MASK)) { | 575 | if (!(asid & cpu_asid_mask(&cpu_data[cpu]))) { |
569 | if (cpu_has_vtag_icache) | 576 | if (cpu_has_vtag_icache) |
570 | flush_icache_all(); | 577 | flush_icache_all(); |
571 | 578 | ||
572 | kvm_local_flush_tlb_all(); /* start new asid cycle */ | 579 | kvm_local_flush_tlb_all(); /* start new asid cycle */ |
573 | 580 | ||
574 | if (!asid) /* fix version if needed */ | 581 | if (!asid) /* fix version if needed */ |
575 | asid = ASID_FIRST_VERSION; | 582 | asid = asid_first_version(cpu); |
576 | } | 583 | } |
577 | 584 | ||
578 | cpu_context(cpu, mm) = asid_cache(cpu) = asid; | 585 | cpu_context(cpu, mm) = asid_cache(cpu) = asid; |
@@ -627,6 +634,7 @@ static void kvm_mips_migrate_count(struct kvm_vcpu *vcpu) | |||
627 | /* Restore ASID once we are scheduled back after preemption */ | 634 | /* Restore ASID once we are scheduled back after preemption */ |
628 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) | 635 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
629 | { | 636 | { |
637 | unsigned long asid_mask = cpu_asid_mask(&cpu_data[cpu]); | ||
630 | unsigned long flags; | 638 | unsigned long flags; |
631 | int newasid = 0; | 639 | int newasid = 0; |
632 | 640 | ||
@@ -637,7 +645,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) | |||
637 | local_irq_save(flags); | 645 | local_irq_save(flags); |
638 | 646 | ||
639 | if ((vcpu->arch.guest_kernel_asid[cpu] ^ asid_cache(cpu)) & | 647 | if ((vcpu->arch.guest_kernel_asid[cpu] ^ asid_cache(cpu)) & |
640 | ASID_VERSION_MASK) { | 648 | asid_version_mask(cpu)) { |
641 | kvm_get_new_mmu_context(&vcpu->arch.guest_kernel_mm, cpu, vcpu); | 649 | kvm_get_new_mmu_context(&vcpu->arch.guest_kernel_mm, cpu, vcpu); |
642 | vcpu->arch.guest_kernel_asid[cpu] = | 650 | vcpu->arch.guest_kernel_asid[cpu] = |
643 | vcpu->arch.guest_kernel_mm.context.asid[cpu]; | 651 | vcpu->arch.guest_kernel_mm.context.asid[cpu]; |
@@ -672,7 +680,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) | |||
672 | */ | 680 | */ |
673 | if (current->flags & PF_VCPU) { | 681 | if (current->flags & PF_VCPU) { |
674 | write_c0_entryhi(vcpu->arch. | 682 | write_c0_entryhi(vcpu->arch. |
675 | preempt_entryhi & ASID_MASK); | 683 | preempt_entryhi & asid_mask); |
676 | ehb(); | 684 | ehb(); |
677 | } | 685 | } |
678 | } else { | 686 | } else { |
@@ -687,11 +695,11 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) | |||
687 | if (KVM_GUEST_KERNEL_MODE(vcpu)) | 695 | if (KVM_GUEST_KERNEL_MODE(vcpu)) |
688 | write_c0_entryhi(vcpu->arch. | 696 | write_c0_entryhi(vcpu->arch. |
689 | guest_kernel_asid[cpu] & | 697 | guest_kernel_asid[cpu] & |
690 | ASID_MASK); | 698 | asid_mask); |
691 | else | 699 | else |
692 | write_c0_entryhi(vcpu->arch. | 700 | write_c0_entryhi(vcpu->arch. |
693 | guest_user_asid[cpu] & | 701 | guest_user_asid[cpu] & |
694 | ASID_MASK); | 702 | asid_mask); |
695 | ehb(); | 703 | ehb(); |
696 | } | 704 | } |
697 | } | 705 | } |
@@ -721,7 +729,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |||
721 | kvm_mips_callbacks->vcpu_get_regs(vcpu); | 729 | kvm_mips_callbacks->vcpu_get_regs(vcpu); |
722 | 730 | ||
723 | if (((cpu_context(cpu, current->mm) ^ asid_cache(cpu)) & | 731 | if (((cpu_context(cpu, current->mm) ^ asid_cache(cpu)) & |
724 | ASID_VERSION_MASK)) { | 732 | asid_version_mask(cpu))) { |
725 | kvm_debug("%s: Dropping MMU Context: %#lx\n", __func__, | 733 | kvm_debug("%s: Dropping MMU Context: %#lx\n", __func__, |
726 | cpu_context(cpu, current->mm)); | 734 | cpu_context(cpu, current->mm)); |
727 | drop_mmu_context(current->mm, cpu); | 735 | drop_mmu_context(current->mm, cpu); |
diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c index 92a37319efbe..3283aa7423e4 100644 --- a/arch/mips/lib/dump_tlb.c +++ b/arch/mips/lib/dump_tlb.c | |||
@@ -73,6 +73,8 @@ static void dump_tlb(int first, int last) | |||
73 | unsigned long s_entryhi, entryhi, asid; | 73 | unsigned long s_entryhi, entryhi, asid; |
74 | unsigned long long entrylo0, entrylo1, pa; | 74 | unsigned long long entrylo0, entrylo1, pa; |
75 | unsigned int s_index, s_pagemask, pagemask, c0, c1, i; | 75 | unsigned int s_index, s_pagemask, pagemask, c0, c1, i; |
76 | unsigned long asidmask = cpu_asid_mask(¤t_cpu_data); | ||
77 | int asidwidth = DIV_ROUND_UP(ilog2(asidmask) + 1, 4); | ||
76 | #ifdef CONFIG_32BIT | 78 | #ifdef CONFIG_32BIT |
77 | bool xpa = cpu_has_xpa && (read_c0_pagegrain() & PG_ELPA); | 79 | bool xpa = cpu_has_xpa && (read_c0_pagegrain() & PG_ELPA); |
78 | int pwidth = xpa ? 11 : 8; | 80 | int pwidth = xpa ? 11 : 8; |
@@ -86,7 +88,7 @@ static void dump_tlb(int first, int last) | |||
86 | s_pagemask = read_c0_pagemask(); | 88 | s_pagemask = read_c0_pagemask(); |
87 | s_entryhi = read_c0_entryhi(); | 89 | s_entryhi = read_c0_entryhi(); |
88 | s_index = read_c0_index(); | 90 | s_index = read_c0_index(); |
89 | asid = s_entryhi & 0xff; | 91 | asid = s_entryhi & asidmask; |
90 | 92 | ||
91 | for (i = first; i <= last; i++) { | 93 | for (i = first; i <= last; i++) { |
92 | write_c0_index(i); | 94 | write_c0_index(i); |
@@ -115,7 +117,7 @@ static void dump_tlb(int first, int last) | |||
115 | * due to duplicate TLB entry. | 117 | * due to duplicate TLB entry. |
116 | */ | 118 | */ |
117 | if (!((entrylo0 | entrylo1) & ENTRYLO_G) && | 119 | if (!((entrylo0 | entrylo1) & ENTRYLO_G) && |
118 | (entryhi & 0xff) != asid) | 120 | (entryhi & asidmask) != asid) |
119 | continue; | 121 | continue; |
120 | 122 | ||
121 | /* | 123 | /* |
@@ -126,9 +128,9 @@ static void dump_tlb(int first, int last) | |||
126 | c0 = (entrylo0 & ENTRYLO_C) >> ENTRYLO_C_SHIFT; | 128 | c0 = (entrylo0 & ENTRYLO_C) >> ENTRYLO_C_SHIFT; |
127 | c1 = (entrylo1 & ENTRYLO_C) >> ENTRYLO_C_SHIFT; | 129 | c1 = (entrylo1 & ENTRYLO_C) >> ENTRYLO_C_SHIFT; |
128 | 130 | ||
129 | printk("va=%0*lx asid=%02lx\n", | 131 | printk("va=%0*lx asid=%0*lx\n", |
130 | vwidth, (entryhi & ~0x1fffUL), | 132 | vwidth, (entryhi & ~0x1fffUL), |
131 | entryhi & 0xff); | 133 | asidwidth, entryhi & asidmask); |
132 | /* RI/XI are in awkward places, so mask them off separately */ | 134 | /* RI/XI are in awkward places, so mask them off separately */ |
133 | pa = entrylo0 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI); | 135 | pa = entrylo0 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI); |
134 | if (xpa) | 136 | if (xpa) |
diff --git a/arch/mips/lib/r3k_dump_tlb.c b/arch/mips/lib/r3k_dump_tlb.c index cfcbb5218b59..744f4a7bc49d 100644 --- a/arch/mips/lib/r3k_dump_tlb.c +++ b/arch/mips/lib/r3k_dump_tlb.c | |||
@@ -29,9 +29,10 @@ static void dump_tlb(int first, int last) | |||
29 | { | 29 | { |
30 | int i; | 30 | int i; |
31 | unsigned int asid; | 31 | unsigned int asid; |
32 | unsigned long entryhi, entrylo0; | 32 | unsigned long entryhi, entrylo0, asid_mask; |
33 | 33 | ||
34 | asid = read_c0_entryhi() & ASID_MASK; | 34 | asid_mask = cpu_asid_mask(¤t_cpu_data); |
35 | asid = read_c0_entryhi() & asid_mask; | ||
35 | 36 | ||
36 | for (i = first; i <= last; i++) { | 37 | for (i = first; i <= last; i++) { |
37 | write_c0_index(i<<8); | 38 | write_c0_index(i<<8); |
@@ -46,7 +47,7 @@ static void dump_tlb(int first, int last) | |||
46 | /* Unused entries have a virtual address of KSEG0. */ | 47 | /* Unused entries have a virtual address of KSEG0. */ |
47 | if ((entryhi & PAGE_MASK) != KSEG0 && | 48 | if ((entryhi & PAGE_MASK) != KSEG0 && |
48 | (entrylo0 & R3K_ENTRYLO_G || | 49 | (entrylo0 & R3K_ENTRYLO_G || |
49 | (entryhi & ASID_MASK) == asid)) { | 50 | (entryhi & asid_mask) == asid)) { |
50 | /* | 51 | /* |
51 | * Only print entries in use | 52 | * Only print entries in use |
52 | */ | 53 | */ |
@@ -55,7 +56,7 @@ static void dump_tlb(int first, int last) | |||
55 | printk("va=%08lx asid=%08lx" | 56 | printk("va=%08lx asid=%08lx" |
56 | " [pa=%06lx n=%d d=%d v=%d g=%d]", | 57 | " [pa=%06lx n=%d d=%d v=%d g=%d]", |
57 | entryhi & PAGE_MASK, | 58 | entryhi & PAGE_MASK, |
58 | entryhi & ASID_MASK, | 59 | entryhi & asid_mask, |
59 | entrylo0 & PAGE_MASK, | 60 | entrylo0 & PAGE_MASK, |
60 | (entrylo0 & R3K_ENTRYLO_N) ? 1 : 0, | 61 | (entrylo0 & R3K_ENTRYLO_N) ? 1 : 0, |
61 | (entrylo0 & R3K_ENTRYLO_D) ? 1 : 0, | 62 | (entrylo0 & R3K_ENTRYLO_D) ? 1 : 0, |
diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c index b4f366f7c0f5..1290b995695d 100644 --- a/arch/mips/mm/tlb-r3k.c +++ b/arch/mips/mm/tlb-r3k.c | |||
@@ -43,7 +43,7 @@ static void local_flush_tlb_from(int entry) | |||
43 | { | 43 | { |
44 | unsigned long old_ctx; | 44 | unsigned long old_ctx; |
45 | 45 | ||
46 | old_ctx = read_c0_entryhi() & ASID_MASK; | 46 | old_ctx = read_c0_entryhi() & cpu_asid_mask(¤t_cpu_data); |
47 | write_c0_entrylo0(0); | 47 | write_c0_entrylo0(0); |
48 | while (entry < current_cpu_data.tlbsize) { | 48 | while (entry < current_cpu_data.tlbsize) { |
49 | write_c0_index(entry << 8); | 49 | write_c0_index(entry << 8); |
@@ -81,6 +81,7 @@ void local_flush_tlb_mm(struct mm_struct *mm) | |||
81 | void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, | 81 | void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, |
82 | unsigned long end) | 82 | unsigned long end) |
83 | { | 83 | { |
84 | unsigned long asid_mask = cpu_asid_mask(¤t_cpu_data); | ||
84 | struct mm_struct *mm = vma->vm_mm; | 85 | struct mm_struct *mm = vma->vm_mm; |
85 | int cpu = smp_processor_id(); | 86 | int cpu = smp_processor_id(); |
86 | 87 | ||
@@ -89,13 +90,13 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, | |||
89 | 90 | ||
90 | #ifdef DEBUG_TLB | 91 | #ifdef DEBUG_TLB |
91 | printk("[tlbrange<%lu,0x%08lx,0x%08lx>]", | 92 | printk("[tlbrange<%lu,0x%08lx,0x%08lx>]", |
92 | cpu_context(cpu, mm) & ASID_MASK, start, end); | 93 | cpu_context(cpu, mm) & asid_mask, start, end); |
93 | #endif | 94 | #endif |
94 | local_irq_save(flags); | 95 | local_irq_save(flags); |
95 | size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; | 96 | size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; |
96 | if (size <= current_cpu_data.tlbsize) { | 97 | if (size <= current_cpu_data.tlbsize) { |
97 | int oldpid = read_c0_entryhi() & ASID_MASK; | 98 | int oldpid = read_c0_entryhi() & asid_mask; |
98 | int newpid = cpu_context(cpu, mm) & ASID_MASK; | 99 | int newpid = cpu_context(cpu, mm) & asid_mask; |
99 | 100 | ||
100 | start &= PAGE_MASK; | 101 | start &= PAGE_MASK; |
101 | end += PAGE_SIZE - 1; | 102 | end += PAGE_SIZE - 1; |
@@ -159,6 +160,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) | |||
159 | 160 | ||
160 | void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | 161 | void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) |
161 | { | 162 | { |
163 | unsigned long asid_mask = cpu_asid_mask(¤t_cpu_data); | ||
162 | int cpu = smp_processor_id(); | 164 | int cpu = smp_processor_id(); |
163 | 165 | ||
164 | if (cpu_context(cpu, vma->vm_mm) != 0) { | 166 | if (cpu_context(cpu, vma->vm_mm) != 0) { |
@@ -168,10 +170,10 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | |||
168 | #ifdef DEBUG_TLB | 170 | #ifdef DEBUG_TLB |
169 | printk("[tlbpage<%lu,0x%08lx>]", cpu_context(cpu, vma->vm_mm), page); | 171 | printk("[tlbpage<%lu,0x%08lx>]", cpu_context(cpu, vma->vm_mm), page); |
170 | #endif | 172 | #endif |
171 | newpid = cpu_context(cpu, vma->vm_mm) & ASID_MASK; | 173 | newpid = cpu_context(cpu, vma->vm_mm) & asid_mask; |
172 | page &= PAGE_MASK; | 174 | page &= PAGE_MASK; |
173 | local_irq_save(flags); | 175 | local_irq_save(flags); |
174 | oldpid = read_c0_entryhi() & ASID_MASK; | 176 | oldpid = read_c0_entryhi() & asid_mask; |
175 | write_c0_entryhi(page | newpid); | 177 | write_c0_entryhi(page | newpid); |
176 | BARRIER; | 178 | BARRIER; |
177 | tlb_probe(); | 179 | tlb_probe(); |
@@ -190,6 +192,7 @@ finish: | |||
190 | 192 | ||
191 | void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) | 193 | void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) |
192 | { | 194 | { |
195 | unsigned long asid_mask = cpu_asid_mask(¤t_cpu_data); | ||
193 | unsigned long flags; | 196 | unsigned long flags; |
194 | int idx, pid; | 197 | int idx, pid; |
195 | 198 | ||
@@ -199,10 +202,10 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) | |||
199 | if (current->active_mm != vma->vm_mm) | 202 | if (current->active_mm != vma->vm_mm) |
200 | return; | 203 | return; |
201 | 204 | ||
202 | pid = read_c0_entryhi() & ASID_MASK; | 205 | pid = read_c0_entryhi() & asid_mask; |
203 | 206 | ||
204 | #ifdef DEBUG_TLB | 207 | #ifdef DEBUG_TLB |
205 | if ((pid != (cpu_context(cpu, vma->vm_mm) & ASID_MASK)) || (cpu_context(cpu, vma->vm_mm) == 0)) { | 208 | if ((pid != (cpu_context(cpu, vma->vm_mm) & asid_mask)) || (cpu_context(cpu, vma->vm_mm) == 0)) { |
206 | printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%lu tlbpid=%d\n", | 209 | printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%lu tlbpid=%d\n", |
207 | (cpu_context(cpu, vma->vm_mm)), pid); | 210 | (cpu_context(cpu, vma->vm_mm)), pid); |
208 | } | 211 | } |
@@ -228,6 +231,7 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) | |||
228 | void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, | 231 | void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, |
229 | unsigned long entryhi, unsigned long pagemask) | 232 | unsigned long entryhi, unsigned long pagemask) |
230 | { | 233 | { |
234 | unsigned long asid_mask = cpu_asid_mask(¤t_cpu_data); | ||
231 | unsigned long flags; | 235 | unsigned long flags; |
232 | unsigned long old_ctx; | 236 | unsigned long old_ctx; |
233 | static unsigned long wired = 0; | 237 | static unsigned long wired = 0; |
@@ -243,7 +247,7 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, | |||
243 | 247 | ||
244 | local_irq_save(flags); | 248 | local_irq_save(flags); |
245 | /* Save old context and create impossible VPN2 value */ | 249 | /* Save old context and create impossible VPN2 value */ |
246 | old_ctx = read_c0_entryhi() & ASID_MASK; | 250 | old_ctx = read_c0_entryhi() & asid_mask; |
247 | old_pagemask = read_c0_pagemask(); | 251 | old_pagemask = read_c0_pagemask(); |
248 | w = read_c0_wired(); | 252 | w = read_c0_wired(); |
249 | write_c0_wired(w + 1); | 253 | write_c0_wired(w + 1); |
@@ -266,7 +270,7 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, | |||
266 | #endif | 270 | #endif |
267 | 271 | ||
268 | local_irq_save(flags); | 272 | local_irq_save(flags); |
269 | old_ctx = read_c0_entryhi() & ASID_MASK; | 273 | old_ctx = read_c0_entryhi() & asid_mask; |
270 | write_c0_entrylo0(entrylo0); | 274 | write_c0_entrylo0(entrylo0); |
271 | write_c0_entryhi(entryhi); | 275 | write_c0_entryhi(entryhi); |
272 | write_c0_index(wired); | 276 | write_c0_index(wired); |
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 4c3362b46066..61f1f1ba4a17 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c | |||
@@ -304,7 +304,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) | |||
304 | local_irq_save(flags); | 304 | local_irq_save(flags); |
305 | 305 | ||
306 | htw_stop(); | 306 | htw_stop(); |
307 | pid = read_c0_entryhi() & ASID_MASK; | 307 | pid = read_c0_entryhi() & cpu_asid_mask(¤t_cpu_data); |
308 | address &= (PAGE_MASK << 1); | 308 | address &= (PAGE_MASK << 1); |
309 | write_c0_entryhi(address | pid); | 309 | write_c0_entryhi(address | pid); |
310 | pgdp = pgd_offset(vma->vm_mm, address); | 310 | pgdp = pgd_offset(vma->vm_mm, address); |
diff --git a/arch/mips/mm/tlb-r8k.c b/arch/mips/mm/tlb-r8k.c index 138a2ec7cc6b..e86e2e55ad3e 100644 --- a/arch/mips/mm/tlb-r8k.c +++ b/arch/mips/mm/tlb-r8k.c | |||
@@ -194,7 +194,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) | |||
194 | if (current->active_mm != vma->vm_mm) | 194 | if (current->active_mm != vma->vm_mm) |
195 | return; | 195 | return; |
196 | 196 | ||
197 | pid = read_c0_entryhi() & ASID_MASK; | 197 | pid = read_c0_entryhi() & cpu_asid_mask(¤t_cpu_data); |
198 | 198 | ||
199 | local_irq_save(flags); | 199 | local_irq_save(flags); |
200 | address &= PAGE_MASK; | 200 | address &= PAGE_MASK; |