Merge branch '4.14-features' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:
 "This is the main pull request for 4.14 for MIPS; below a summary of
  the non-merge commits:

  CM:
   - Rename mips_cm_base to mips_gcr_base
   - Specify register size when generating accessors
   - Use BIT/GENMASK for register fields, order & drop shifts
   - Add cluster & block args to mips_cm_lock_other()

  CPC:
   - Use common CPS accessor generation macros
   - Use BIT/GENMASK for register fields, order & drop shifts
   - Introduce register modify (set/clear/change) accessors
   - Use change_*, set_* & clear_* where appropriate
   - Add CM/CPC 3.5 register definitions
   - Use GlobalNumber macros rather than magic numbers
   - Have asm/mips-cps.h include CM & CPC headers
   - Cluster support for topology functions
   - Detect CPUs in secondary clusters

  CPS:
   - Read GIC_VL_IDENT directly, not via irqchip driver

  DMA:
   - Consolidate coherent and non-coherent dma_alloc code
   - Don't use dma_cache_sync to implement fd_cacheflush

  FPU emulation / FP assist code:
   - Another series of 14 commits fixing corner cases such as NaN
     propgagation and other special input values.
   - Zero bits 32-63 of the result for a CLASS.D instruction.
   - Enhanced statics via debugfs
   - Do not use bools for arithmetic. GCC 7.1 moans about this.
   - Correct user fault_addr type

  Generic MIPS:
   - Enhancement of stack backtraces
   - Cleanup from non-existing options
   - Handle non word sized instructions when examining frame
   - Fix detection and decoding of ADDIUSP instruction
   - Fix decoding of SWSP16 instruction
   - Refactor handling of stack pointer in get_frame_info
   - Remove unreachable code from force_fcr31_sig()
   - Convert to using %pOF instead of full_name
   - Remove the R6000 support.
   - Move FP code from *_switch.S to *_fpu.S
   - Remove unused ST_OFF from r2300_switch.S
   - Allow platform to specify multiple its.S files
   - Add #includes to various files to ensure code builds reliable and
     without warning..
   - Remove __invalidate_kernel_vmap_range
   - Remove plat_timer_setup
   - Declare various variables & functions static
   - Abstract CPU core & VP(E) ID access through accessor functions
   - Store core & VP IDs in GlobalNumber-style variable
   - Unify checks for sibling CPUs
   - Add CPU cluster number accessors
   - Prevent direct use of generic_defconfig
   - Make CONFIG_MIPS_MT_SMP default y
   - Add __ioread64_copy
   - Remove unnecessary inclusions of linux/irqchip/mips-gic.h

  GIC:
   - Introduce asm/mips-gic.h with accessor functions
   - Use new GIC accessor functions in mips-gic-timer
   - Remove counter access functions from irq-mips-gic.c
   - Remove gic_read_local_vp_id() from irq-mips-gic.c
   - Simplify shared interrupt pending/mask reads in irq-mips-gic.c
   - Simplify gic_local_irq_domain_map() in irq-mips-gic.c
   - Drop gic_(re)set_mask() functions in irq-mips-gic.c
   - Remove gic_set_polarity(), gic_set_trigger(), gic_set_dual_edge(),
     gic_map_to_pin() and gic_map_to_vpe() from irq-mips-gic.c.
   - Convert remaining shared reg access, local int mask access and
     remaining local reg access to new accessors
   - Move GIC_LOCAL_INT_* to asm/mips-gic.h
   - Remove GIC_CPU_INT* macros from irq-mips-gic.c
   - Move various definitions to the driver
   - Remove gic_get_usm_range()
   - Remove __gic_irq_dispatch() forward declaration
   - Remove gic_init()
   - Use mips_gic_present() in place of gic_present and remove
     gic_present
   - Move gic_get_c0_*_int() to asm/mips-gic.h
   - Remove linux/irqchip/mips-gic.h
   - Inline __gic_init()
   - Inline gic_basic_init()
   - Make pcpu_masks a per-cpu variable
   - Use pcpu_masks to avoid reading GIC_SH_MASK*
   - Clean up mti, reserved-cpu-vectors handling
   - Use cpumask_first_and() in gic_set_affinity()
   - Let the core set struct irq_common_data affinity

  microMIPS:
   - Fix microMIPS stack unwinding on big endian systems

  MIPS-GIC:
   - SYNC after enabling GIC region

  NUMA:
   - Remove the unused parent_node() macro

  R6:
   - Constify r2_decoder_tables
   - Add accessor & bit definitions for GlobalNumber

  SMP:
   - Constify smp ops
   - Allow boot_secondary SMP op to return errors

  VDSO:
   - Drop gic_get_usm_range() usage
   - Avoid use of linux/irqchip/mips-gic.h

  Platform changes:

  Alchemy:
   - Add devboard machine type to cpuinfo
   - update cpu feature overrides
   - Threaded carddetect irqs for devboards

  AR7:
   - allow NULL clock for clk_get_rate

  BCM63xx:
   - Fix ENETDMA_6345_MAXBURST_REG offset
   - Allow NULL clock for clk_get_rate

  CI20:
   - Enable GPIO and RTC drivers in defconfig
   - Add ethernet and fixed-regulator nodes to DTS

  Generic platform:
   - Move Boston and NI 169445 FIT image source to their own files
   - Include asm/bootinfo.h for plat_fdt_relocated()
   - Include asm/time.h for get_c0_*_int()
   - Include asm/bootinfo.h for plat_fdt_relocated()
   - Include asm/time.h for get_c0_*_int()
   - Allow filtering enabled boards by requirements
   - Don't explicitly disable CONFIG_USB_SUPPORT
   - Bump default NR_CPUS to 16

  JZ4700:
   - Probe the jz4740-rtc driver from devicetree

  Lantiq:
   - Drop check of boot select from the spi-falcon driver.
   - Drop check of boot select from the lantiq-flash MTD driver.
   - Access boot cause register in the watchdog driver through regmap
   - Add device tree binding documentation for the watchdog driver
   - Add docs for the RCU DT bindings.
   - Convert the fpi bus driver to a platform_driver
   - Remove ltq_reset_cause() and ltq_boot_select(
   - Switch to a proper reset driver
   - Switch to a new drivers/soc GPHY driver
   - Add an USB PHY driver for the Lantiq SoCs using the RCU module
   - Use of_platform_default_populate instead of __dt_register_buses
   - Enable MFD_SYSCON to be able to use it for the RCU MFD
   - Replace ltq_boot_select() with dummy implementation.

  Loongson 2F:
   - Allow NULL clock for clk_get_rate

  Malta:
   - Use new GIC accessor functions

  NI 169445:
   - Add support for NI 169445 board.
   - Only include in 32r2el kernels

  Octeon:
   - Add support for watchdog of 78XX SOCs.
   - Add support for watchdog of CN68XX SOCs.
   - Expose support for mips32r1, mips32r2 and mips64r1
   - Enable more drivers in config file
   - Add support for accessing the boot vector.
   - Remove old boot vector code from watchdog driver
   - Define watchdog registers for 70xx, 73xx, 78xx, F75xx.
   - Make CSR functions node aware.
   - Allow access to CIU3 IRQ domains.
   - Misc cleanups in the watchdog driver

  Omega2+:
   - New board, add support and defconfig

  Pistachio:
   - Enable Root FS on NFS in defconfig

  Ralink:
   - Add Mediatek MT7628A SoC
   - Allow NULL clock for clk_get_rate
   - Explicitly request exclusive reset control in the pci-mt7620 PCI driver.

  SEAD3:
   - Only include in 32 bit kernels by default

  VoCore:
   - Add VoCore as a vendor t0 dt-bindings
   - Add defconfig file"

* '4.14-features' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (167 commits)
  MIPS: Refactor handling of stack pointer in get_frame_info
  MIPS: Stacktrace: Fix microMIPS stack unwinding on big endian systems
  MIPS: microMIPS: Fix decoding of swsp16 instruction
  MIPS: microMIPS: Fix decoding of addiusp instruction
  MIPS: microMIPS: Fix detection of addiusp instruction
  MIPS: Handle non word sized instructions when examining frame
  MIPS: ralink: allow NULL clock for clk_get_rate
  MIPS: Loongson 2F: allow NULL clock for clk_get_rate
  MIPS: BCM63XX: allow NULL clock for clk_get_rate
  MIPS: AR7: allow NULL clock for clk_get_rate
  MIPS: BCM63XX: fix ENETDMA_6345_MAXBURST_REG offset
  mips: Save all registers when saving the frame
  MIPS: Add DWARF unwinding to assembly
  MIPS: Make SAVE_SOME more standard
  MIPS: Fix issues in backtraces
  MIPS: jz4780: DTS: Probe the jz4740-rtc driver from devicetree
  MIPS: Ci20: Enable RTC driver
  watchdog: octeon-wdt: Add support for 78XX SOCs.
  watchdog: octeon-wdt: Add support for cn68XX SOCs.
  watchdog: octeon-wdt: File cleaning.
  ...

1 files changed, 168 insertions, 112 deletions

diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index eaa5a4d7d5e5..5d3563c55e0c 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -19,20 +19,43 @@
 #include <asm/asm-offsets.h>
 #include <asm/thread_info.h>
 
+/* Make the addition of cfi info a little easier. */
+        .macro cfi_rel_offset reg offset=0 docfi=0
+        .if \docfi
+        .cfi_rel_offset \reg, \offset
+        .endif
+        .endm
+
+        .macro cfi_st reg offset=0 docfi=0
+        LONG_S  \reg, \offset(sp)
+        cfi_rel_offset \reg, \offset, \docfi
+        .endm
+
+        .macro cfi_restore reg offset=0 docfi=0
+        .if \docfi
+        .cfi_restore \reg
+        .endif
+        .endm
+
+        .macro cfi_ld reg offset=0 docfi=0
+        LONG_L  \reg, \offset(sp)
+        cfi_restore \reg \offset \docfi
+        .endm
+
 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
 #define STATMASK 0x3f
 #else
 #define STATMASK 0x1f
 #endif
 
-                .macro  SAVE_AT
+                .macro  SAVE_AT docfi=0
                 .set    push
                 .set    noat
-                LONG_S  $1, PT_R1(sp)
+                cfi_st  $1, PT_R1, \docfi
                 .set    pop
                 .endm
 
-                .macro  SAVE_TEMP
+                .macro  SAVE_TEMP docfi=0
 #ifdef CONFIG_CPU_HAS_SMARTMIPS
                 mflhxu  v1
                 LONG_S  v1, PT_LO(sp)
@@ -44,20 +67,20 @@
                 mfhi    v1
 #endif
 #ifdef CONFIG_32BIT
-                LONG_S  $8, PT_R8(sp)
-                LONG_S  $9, PT_R9(sp)
+                cfi_st  $8, PT_R8, \docfi
+                cfi_st  $9, PT_R9, \docfi
 #endif
-                LONG_S  $10, PT_R10(sp)
-                LONG_S  $11, PT_R11(sp)
-                LONG_S  $12, PT_R12(sp)
+                cfi_st  $10, PT_R10, \docfi
+                cfi_st  $11, PT_R11, \docfi
+                cfi_st  $12, PT_R12, \docfi
 #if !defined(CONFIG_CPU_HAS_SMARTMIPS) && !defined(CONFIG_CPU_MIPSR6)
                 LONG_S  v1, PT_HI(sp)
                 mflo    v1
 #endif
-                LONG_S  $13, PT_R13(sp)
-                LONG_S  $14, PT_R14(sp)
-                LONG_S  $15, PT_R15(sp)
-                LONG_S  $24, PT_R24(sp)
+                cfi_st  $13, PT_R13, \docfi
+                cfi_st  $14, PT_R14, \docfi
+                cfi_st  $15, PT_R15, \docfi
+                cfi_st  $24, PT_R24, \docfi
 #if !defined(CONFIG_CPU_HAS_SMARTMIPS) && !defined(CONFIG_CPU_MIPSR6)
                 LONG_S  v1, PT_LO(sp)
 #endif
@@ -71,20 +94,28 @@
 #endif
                 .endm
 
-                .macro  SAVE_STATIC
-                LONG_S  $16, PT_R16(sp)
-                LONG_S  $17, PT_R17(sp)
-                LONG_S  $18, PT_R18(sp)
-                LONG_S  $19, PT_R19(sp)
-                LONG_S  $20, PT_R20(sp)
-                LONG_S  $21, PT_R21(sp)
-                LONG_S  $22, PT_R22(sp)
-                LONG_S  $23, PT_R23(sp)
-                LONG_S  $30, PT_R30(sp)
+                .macro  SAVE_STATIC docfi=0
+                cfi_st  $16, PT_R16, \docfi
+                cfi_st  $17, PT_R17, \docfi
+                cfi_st  $18, PT_R18, \docfi
+                cfi_st  $19, PT_R19, \docfi
+                cfi_st  $20, PT_R20, \docfi
+                cfi_st  $21, PT_R21, \docfi
+                cfi_st  $22, PT_R22, \docfi
+                cfi_st  $23, PT_R23, \docfi
+                cfi_st  $30, PT_R30, \docfi
                 .endm
 
+/*
+ * get_saved_sp returns the SP for the current CPU by looking in the
+ * kernelsp array for it.  If tosp is set, it stores the current sp in
+ * k0 and loads the new value in sp.  If not, it clobbers k0 and
+ * stores the new value in k1, leaving sp unaffected.
+ */
 #ifdef CONFIG_SMP
-                .macro  get_saved_sp    /* SMP variation */
+
+                /* SMP variation */
+                .macro  get_saved_sp docfi=0 tosp=0
                 ASM_CPUID_MFC0  k0, ASM_SMP_CPUID_REG
 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
                 lui     k1, %hi(kernelsp)
@@ -97,7 +128,15 @@
 #endif
                 LONG_SRL        k0, SMP_CPUID_PTRSHIFT
                 LONG_ADDU       k1, k0
+                .if \tosp
+                move    k0, sp
+                .if \docfi
+                .cfi_register sp, k0
+                .endif
+                LONG_L  sp, %lo(kernelsp)(k1)
+                .else
                 LONG_L  k1, %lo(kernelsp)(k1)
+                .endif
                 .endm
 
                 .macro  set_saved_sp stackp temp temp2
@@ -106,7 +145,8 @@
                 LONG_S  \stackp, kernelsp(\temp)
                 .endm
 #else /* !CONFIG_SMP */
-                .macro  get_saved_sp    /* Uniprocessor variation */
+                /* Uniprocessor variation */
+                .macro  get_saved_sp docfi=0 tosp=0
 #ifdef CONFIG_CPU_JUMP_WORKAROUNDS
                 /*
                  * Clear BTB (branch target buffer), forbid RAS (return address
@@ -135,7 +175,15 @@
                 daddiu  k1, %hi(kernelsp)
                 dsll    k1, k1, 16
 #endif
+                .if \tosp
+                move    k0, sp
+                .if \docfi
+                .cfi_register sp, k0
+                .endif
+                LONG_L  sp, %lo(kernelsp)(k1)
+                .else
                 LONG_L  k1, %lo(kernelsp)(k1)
+                .endif
                 .endm
 
                 .macro  set_saved_sp stackp temp temp2
@@ -143,7 +191,7 @@
                 .endm
 #endif
 
-                .macro  SAVE_SOME
+                .macro  SAVE_SOME docfi=0
                 .set    push
                 .set    noat
                 .set    reorder
@@ -151,7 +199,6 @@
                 sll     k0, 3           /* extract cu0 bit */
                 .set    noreorder
                 bltz    k0, 8f
-                 move   k1, sp
 #ifdef CONFIG_EVA
                 /*
                  * Flush interAptiv's Return Prediction Stack (RPS) by writing
@@ -178,20 +225,26 @@
                 MTC0    k0, CP0_ENTRYHI
 #endif
                 .set    reorder
+                 move   k0, sp
+                .if \docfi
+                .cfi_register sp, k0
+                .endif
                 /* Called from user mode, new stack. */
-                get_saved_sp
-#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
-8:              move    k0, sp
-                PTR_SUBU sp, k1, PT_SIZE
-#else
-                .set    at=k0
-8:              PTR_SUBU k1, PT_SIZE
+                get_saved_sp docfi=\docfi tosp=1
+8:
+#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
+                .set    at=k1
+#endif
+                PTR_SUBU sp, PT_SIZE
+#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
                 .set    noat
-                move    k0, sp
-                move    sp, k1
 #endif
-                LONG_S  k0, PT_R29(sp)
-                LONG_S  $3, PT_R3(sp)
+                .if \docfi
+                .cfi_def_cfa sp,0
+                .endif
+                cfi_st  k0, PT_R29, \docfi
+                cfi_rel_offset  sp, PT_R29, \docfi
+                cfi_st  v1, PT_R3, \docfi
                 /*
                  * You might think that you don't need to save $0,
                  * but the FPU emulator and gdb remote debug stub
@@ -199,23 +252,26 @@
                  */
                 LONG_S  $0, PT_R0(sp)
                 mfc0    v1, CP0_STATUS
-                LONG_S  $2, PT_R2(sp)
+                cfi_st  v0, PT_R2, \docfi
                 LONG_S  v1, PT_STATUS(sp)
-                LONG_S  $4, PT_R4(sp)
+                cfi_st  $4, PT_R4, \docfi
                 mfc0    v1, CP0_CAUSE
-                LONG_S  $5, PT_R5(sp)
+                cfi_st  $5, PT_R5, \docfi
                 LONG_S  v1, PT_CAUSE(sp)
-                LONG_S  $6, PT_R6(sp)
-                MFC0    v1, CP0_EPC
-                LONG_S  $7, PT_R7(sp)
+                cfi_st  $6, PT_R6, \docfi
+                cfi_st  ra, PT_R31, \docfi
+                MFC0    ra, CP0_EPC
+                cfi_st  $7, PT_R7, \docfi
 #ifdef CONFIG_64BIT
-                LONG_S  $8, PT_R8(sp)
-                LONG_S  $9, PT_R9(sp)
+                cfi_st  $8, PT_R8, \docfi
+                cfi_st  $9, PT_R9, \docfi
 #endif
-                LONG_S  v1, PT_EPC(sp)
-                LONG_S  $25, PT_R25(sp)
-                LONG_S  $28, PT_R28(sp)
-                LONG_S  $31, PT_R31(sp)
+                LONG_S  ra, PT_EPC(sp)
+                .if \docfi
+                .cfi_rel_offset ra, PT_EPC
+                .endif
+                cfi_st  $25, PT_R25, \docfi
+                cfi_st  $28, PT_R28, \docfi
 
                 /* Set thread_info if we're coming from user mode */
                 mfc0    k0, CP0_STATUS
@@ -232,21 +288,21 @@
                 .set    pop
                 .endm
 
-                .macro  SAVE_ALL
-                SAVE_SOME
-                SAVE_AT
-                SAVE_TEMP
-                SAVE_STATIC
+                .macro  SAVE_ALL docfi=0
+                SAVE_SOME \docfi
+                SAVE_AT \docfi
+                SAVE_TEMP \docfi
+                SAVE_STATIC \docfi
                 .endm
 
-                .macro  RESTORE_AT
+                .macro  RESTORE_AT docfi=0
                 .set    push
                 .set    noat
-                LONG_L  $1,  PT_R1(sp)
+                cfi_ld  $1, PT_R1, \docfi
                 .set    pop
                 .endm
 
-                .macro  RESTORE_TEMP
+                .macro  RESTORE_TEMP docfi=0
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
                 /* Restore the Octeon multiplier state */
                 jal     octeon_mult_restore
@@ -265,33 +321,37 @@
                 mthi    $24
 #endif
 #ifdef CONFIG_32BIT
-                LONG_L  $8, PT_R8(sp)
-                LONG_L  $9, PT_R9(sp)
+                cfi_ld  $8, PT_R8, \docfi
+                cfi_ld  $9, PT_R9, \docfi
 #endif
-                LONG_L  $10, PT_R10(sp)
-                LONG_L  $11, PT_R11(sp)
-                LONG_L  $12, PT_R12(sp)
-                LONG_L  $13, PT_R13(sp)
-                LONG_L  $14, PT_R14(sp)
-                LONG_L  $15, PT_R15(sp)
-                LONG_L  $24, PT_R24(sp)
+                cfi_ld  $10, PT_R10, \docfi
+                cfi_ld  $11, PT_R11, \docfi
+                cfi_ld  $12, PT_R12, \docfi
+                cfi_ld  $13, PT_R13, \docfi
+                cfi_ld  $14, PT_R14, \docfi
+                cfi_ld  $15, PT_R15, \docfi
+                cfi_ld  $24, PT_R24, \docfi
                 .endm
 
-                .macro  RESTORE_STATIC
-                LONG_L  $16, PT_R16(sp)
-                LONG_L  $17, PT_R17(sp)
-                LONG_L  $18, PT_R18(sp)
-                LONG_L  $19, PT_R19(sp)
-                LONG_L  $20, PT_R20(sp)
-                LONG_L  $21, PT_R21(sp)
-                LONG_L  $22, PT_R22(sp)
-                LONG_L  $23, PT_R23(sp)
-                LONG_L  $30, PT_R30(sp)
+                .macro  RESTORE_STATIC docfi=0
+                cfi_ld  $16, PT_R16, \docfi
+                cfi_ld  $17, PT_R17, \docfi
+                cfi_ld  $18, PT_R18, \docfi
+                cfi_ld  $19, PT_R19, \docfi
+                cfi_ld  $20, PT_R20, \docfi
+                cfi_ld  $21, PT_R21, \docfi
+                cfi_ld  $22, PT_R22, \docfi
+                cfi_ld  $23, PT_R23, \docfi
+                cfi_ld  $30, PT_R30, \docfi
+                .endm
+
+                .macro  RESTORE_SP docfi=0
+                cfi_ld  sp, PT_R29, \docfi
                 .endm
 
 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
 
-                .macro  RESTORE_SOME
+                .macro  RESTORE_SOME docfi=0
                 .set    push
                 .set    reorder
                 .set    noat
@@ -306,30 +366,30 @@
                 and     v0, v1
                 or      v0, a0
                 mtc0    v0, CP0_STATUS
-                LONG_L  $31, PT_R31(sp)
-                LONG_L  $28, PT_R28(sp)
-                LONG_L  $25, PT_R25(sp)
-                LONG_L  $7,  PT_R7(sp)
-                LONG_L  $6,  PT_R6(sp)
-                LONG_L  $5,  PT_R5(sp)
-                LONG_L  $4,  PT_R4(sp)
-                LONG_L  $3,  PT_R3(sp)
-                LONG_L  $2,  PT_R2(sp)
+                cfi_ld  $31, PT_R31, \docfi
+                cfi_ld  $28, PT_R28, \docfi
+                cfi_ld  $25, PT_R25, \docfi
+                cfi_ld  $7,  PT_R7, \docfi
+                cfi_ld  $6,  PT_R6, \docfi
+                cfi_ld  $5,  PT_R5, \docfi
+                cfi_ld  $4,  PT_R4, \docfi
+                cfi_ld  $3,  PT_R3, \docfi
+                cfi_ld  $2,  PT_R2, \docfi
                 .set    pop
                 .endm
 
-                .macro  RESTORE_SP_AND_RET
+                .macro  RESTORE_SP_AND_RET docfi=0
                 .set    push
                 .set    noreorder
                 LONG_L  k0, PT_EPC(sp)
-                LONG_L  sp, PT_R29(sp)
+                RESTORE_SP \docfi
                 jr      k0
                  rfe
                 .set    pop
                 .endm
 
 #else
-                .macro  RESTORE_SOME
+                .macro  RESTORE_SOME docfi=0
                 .set    push
                 .set    reorder
                 .set    noat
@@ -346,24 +406,24 @@
                 mtc0    v0, CP0_STATUS
                 LONG_L  v1, PT_EPC(sp)
                 MTC0    v1, CP0_EPC
-                LONG_L  $31, PT_R31(sp)
-                LONG_L  $28, PT_R28(sp)
-                LONG_L  $25, PT_R25(sp)
+                cfi_ld  $31, PT_R31, \docfi
+                cfi_ld  $28, PT_R28, \docfi
+                cfi_ld  $25, PT_R25, \docfi
 #ifdef CONFIG_64BIT
-                LONG_L  $8, PT_R8(sp)
-                LONG_L  $9, PT_R9(sp)
+                cfi_ld  $8, PT_R8, \docfi
+                cfi_ld  $9, PT_R9, \docfi
 #endif
-                LONG_L  $7,  PT_R7(sp)
-                LONG_L  $6,  PT_R6(sp)
-                LONG_L  $5,  PT_R5(sp)
-                LONG_L  $4,  PT_R4(sp)
-                LONG_L  $3,  PT_R3(sp)
-                LONG_L  $2,  PT_R2(sp)
+                cfi_ld  $7,  PT_R7, \docfi
+                cfi_ld  $6,  PT_R6, \docfi
+                cfi_ld  $5,  PT_R5, \docfi
+                cfi_ld  $4,  PT_R4, \docfi
+                cfi_ld  $3,  PT_R3, \docfi
+                cfi_ld  $2,  PT_R2, \docfi
                 .set    pop
                 .endm
 
-                .macro  RESTORE_SP_AND_RET
-                LONG_L  sp, PT_R29(sp)
+                .macro  RESTORE_SP_AND_RET docfi=0
+                RESTORE_SP \docfi
 #ifdef CONFIG_CPU_MIPSR6
                 eretnc
 #else
@@ -375,16 +435,12 @@
 
 #endif
 
-                .macro  RESTORE_SP
-                LONG_L  sp, PT_R29(sp)
-                .endm
-
-                .macro  RESTORE_ALL
-                RESTORE_TEMP
-                RESTORE_STATIC
-                RESTORE_AT
-                RESTORE_SOME
-                RESTORE_SP
+                .macro  RESTORE_ALL docfi=0
+                RESTORE_TEMP \docfi
+                RESTORE_STATIC \docfi
+                RESTORE_AT \docfi
+                RESTORE_SOME \docfi
+                RESTORE_SP \docfi
                 .endm
 
 /*