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authorArnd Bergmann <arnd@arndb.de>2018-03-07 15:36:19 -0500
committerArnd Bergmann <arnd@arndb.de>2018-03-09 17:20:00 -0500
commit553b085c2075f6a4a2591108554f830fa61e881f (patch)
tree68d63911f2c12e0fb9fa23498df9300442a88f92 /arch/m32r/kernel/sys_m32r.c
parentfd8773f9f544955f6f47dc2ac3ab85ad64376b7f (diff)
arch: remove m32r port
The Mitsubishi/Renesas m32r architecture has been around for many years, but the Linux port has been obsolete for a very long time as well, with the last significant updates done for linux-2.6.14. While some m32r microcontrollers are still being marketed by Renesas, those are apparently no longer possible to support, mainly due to the lack of an external memory interface. Hirokazu Takata was the maintainer until the architecture got marked Orphaned in 2014. Link: http://www.linux-m32r.org/ Link: https://www.renesas.com/en-eu/products/microcontrollers-microprocessors/m32r.html Cc: Hirokazu Takata <takata@linux-m32r.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/m32r/kernel/sys_m32r.c')
-rw-r--r--arch/m32r/kernel/sys_m32r.c91
1 files changed, 0 insertions, 91 deletions
diff --git a/arch/m32r/kernel/sys_m32r.c b/arch/m32r/kernel/sys_m32r.c
deleted file mode 100644
index 22a50fc49ab7..000000000000
--- a/arch/m32r/kernel/sys_m32r.c
+++ /dev/null
@@ -1,91 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * linux/arch/m32r/kernel/sys_m32r.c
4 *
5 * This file contains various random system calls that
6 * have a non-standard calling sequence on the Linux/M32R platform.
7 *
8 * Taken from i386 version.
9 */
10
11#include <linux/errno.h>
12#include <linux/sched.h>
13#include <linux/mm.h>
14#include <linux/fs.h>
15#include <linux/smp.h>
16#include <linux/sem.h>
17#include <linux/msg.h>
18#include <linux/shm.h>
19#include <linux/stat.h>
20#include <linux/syscalls.h>
21#include <linux/mman.h>
22#include <linux/file.h>
23#include <linux/utsname.h>
24#include <linux/ipc.h>
25
26#include <linux/uaccess.h>
27#include <asm/cachectl.h>
28#include <asm/cacheflush.h>
29#include <asm/syscall.h>
30#include <asm/unistd.h>
31
32/*
33 * sys_tas() - test-and-set
34 */
35asmlinkage int sys_tas(int __user *addr)
36{
37 int oldval;
38
39 if (!access_ok(VERIFY_WRITE, addr, sizeof (int)))
40 return -EFAULT;
41
42 /* atomic operation:
43 * oldval = *addr; *addr = 1;
44 */
45 __asm__ __volatile__ (
46 DCACHE_CLEAR("%0", "r4", "%1")
47 " .fillinsn\n"
48 "1:\n"
49 " lock %0, @%1 -> unlock %2, @%1\n"
50 "2:\n"
51 /* NOTE:
52 * The m32r processor can accept interrupts only
53 * at the 32-bit instruction boundary.
54 * So, in the above code, the "unlock" instruction
55 * can be executed continuously after the "lock"
56 * instruction execution without any interruptions.
57 */
58 ".section .fixup,\"ax\"\n"
59 " .balign 4\n"
60 "3: ldi %0, #%3\n"
61 " seth r14, #high(2b)\n"
62 " or3 r14, r14, #low(2b)\n"
63 " jmp r14\n"
64 ".previous\n"
65 ".section __ex_table,\"a\"\n"
66 " .balign 4\n"
67 " .long 1b,3b\n"
68 ".previous\n"
69 : "=&r" (oldval)
70 : "r" (addr), "r" (1), "i"(-EFAULT)
71 : "r14", "memory"
72#ifdef CONFIG_CHIP_M32700_TS1
73 , "r4"
74#endif /* CONFIG_CHIP_M32700_TS1 */
75 );
76
77 return oldval;
78}
79
80asmlinkage int sys_cacheflush(void *addr, int bytes, int cache)
81{
82 /* This should flush more selectively ... */
83 _flush_cache_all();
84 return 0;
85}
86
87asmlinkage int sys_cachectl(char *addr, int nbytes, int op)
88{
89 /* Not implemented yet. */
90 return -ENOSYS;
91}