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authorKefeng Wang <wangkefeng.wang@huawei.com>2016-08-15 03:03:44 -0400
committerWei Xu <xuwei5@hisilicon.com>2016-08-24 11:19:39 -0400
commit7e01e7a109515718fe89a137a68de3ccff660954 (patch)
tree0671bca5821f5926ef4365a3acbd256b4a82526a /arch/arm64/boot/dts
parent5350419fbaab0cf962ccd9de93e0fed1113d33e9 (diff)
arm64: dts: hip06: Append sas node
This patch adds sas and relevant nodes for Hip06 D03 board. Cc: Xiang Chen <chenxiang66@hisilicon.com> Cc: John Garry <john.garry@huawei.com> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Diffstat (limited to 'arch/arm64/boot/dts')
-rw-r--r--arch/arm64/boot/dts/hisilicon/hip06-d03.dts12
-rw-r--r--arch/arm64/boot/dts/hisilicon/hip06.dtsi150
2 files changed, 162 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
index 5562cf41df17..f54b28359607 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
+++ b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
@@ -41,6 +41,18 @@
41 status = "ok"; 41 status = "ok";
42}; 42};
43 43
44&sas0 {
45 status = "ok";
46};
47
48&sas1 {
49 status = "ok";
50};
51
52&sas2 {
53 status = "ok";
54};
55
44&usb_ohci { 56&usb_ohci {
45 status = "ok"; 57 status = "ok";
46}; 58};
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index ddbff81522a0..b548763366dd 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -277,6 +277,20 @@
277 #interrupt-cells = <2>; 277 #interrupt-cells = <2>;
278 num-pins = <2>; 278 num-pins = <2>;
279 }; 279 };
280
281 mbigen_sas1: intc_sas1 {
282 msi-parent = <&its_dsa 0x40000>;
283 interrupt-controller;
284 #interrupt-cells = <2>;
285 num-pins = <128>;
286 };
287
288 mbigen_sas2: intc_sas2 {
289 msi-parent = <&its_dsa 0x40040>;
290 interrupt-controller;
291 #interrupt-cells = <2>;
292 num-pins = <128>;
293 };
280 }; 294 };
281 295
282 mbigen_dsa@c0080000 { 296 mbigen_dsa@c0080000 {
@@ -289,6 +303,13 @@
289 #interrupt-cells = <2>; 303 #interrupt-cells = <2>;
290 num-pins = <409>; 304 num-pins = <409>;
291 }; 305 };
306
307 mbigen_sas0: intc-sas0 {
308 msi-parent = <&its_dsa 0x40900>;
309 interrupt-controller;
310 #interrupt-cells = <2>;
311 num-pins = <128>;
312 };
292 }; 313 };
293 314
294 soc { 315 soc {
@@ -325,6 +346,11 @@
325 reg = <0x0 0xc0000000 0x0 0x10000>; 346 reg = <0x0 0xc0000000 0x0 0x10000>;
326 }; 347 };
327 348
349 pcie_subctl: pcie_subctl@a0000000 {
350 compatible = "hisilicon,pcie-sas-subctrl", "syscon";
351 reg = <0x0 0xa0000000 0x0 0x10000>;
352 };
353
328 serdes_ctrl: sds_ctrl@c2200000 { 354 serdes_ctrl: sds_ctrl@c2200000 {
329 compatible = "syscon"; 355 compatible = "syscon";
330 reg = <0 0xc2200000 0x0 0x80000>; 356 reg = <0 0xc2200000 0x0 0x80000>;
@@ -517,6 +543,130 @@
517 status = "disabled"; 543 status = "disabled";
518 dma-coherent; 544 dma-coherent;
519 }; 545 };
546
547 sas0: sas@c3000000 {
548 compatible = "hisilicon,hip06-sas-v2";
549 reg = <0 0xc3000000 0 0x10000>;
550 sas-addr = [50 01 88 20 16 00 00 00];
551 hisilicon,sas-syscon = <&dsa_subctrl>;
552 ctrl-reset-reg = <0xa60>;
553 ctrl-reset-sts-reg = <0x5a30>;
554 ctrl-clock-ena-reg = <0x338>;
555 queue-count = <16>;
556 phy-count = <8>;
557 dma-coherent;
558 interrupt-parent = <&mbigen_sas0>;
559 interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
560 <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
561 <75 4>,<76 4>,<77 4>,<78 4>,<79 4>,
562 <80 4>,<81 4>,<82 4>,<83 4>,<84 4>,
563 <85 4>,<86 4>,<87 4>,<88 4>,<89 4>,
564 <90 4>,<91 4>,<92 4>,<93 4>,<94 4>,
565 <95 4>,<96 4>,<97 4>,<98 4>,<99 4>,
566 <100 4>,<101 4>,<102 4>,<103 4>,<104 4>,
567 <105 4>,<106 4>,<107 4>,<108 4>,<109 4>,
568 <110 4>,<111 4>,<112 4>,<113 4>,<114 4>,
569 <115 4>,<116 4>,<117 4>,<118 4>,<119 4>,
570 <120 4>,<121 4>,<122 4>,<123 4>,<124 4>,
571 <125 4>,<126 4>,<127 4>,<128 4>,<129 4>,
572 <130 4>,<131 4>,<132 4>,<133 4>,<134 4>,
573 <135 4>,<136 4>,<137 4>,<138 4>,<139 4>,
574 <140 4>,<141 4>,<142 4>,<143 4>,<144 4>,
575 <145 4>,<146 4>,<147 4>,<148 4>,<149 4>,
576 <150 4>,<151 4>,<152 4>,<153 4>,<154 4>,
577 <155 4>,<156 4>,<157 4>,<158 4>,<159 4>,
578 <160 4>,<601 1>,<602 1>,<603 1>,<604 1>,
579 <605 1>,<606 1>,<607 1>,<608 1>,<609 1>,
580 <610 1>,<611 1>,<612 1>,<613 1>,<614 1>,
581 <615 1>,<616 1>,<617 1>,<618 1>,<619 1>,
582 <620 1>,<621 1>,<622 1>,<623 1>,<624 1>,
583 <625 1>,<626 1>,<627 1>,<628 1>,<629 1>,
584 <630 1>,<631 1>,<632 1>;
585 status = "disabled";
586 };
587
588 sas1: sas@a2000000 {
589 compatible = "hisilicon,hip06-sas-v2";
590 reg = <0 0xa2000000 0 0x10000>;
591 sas-addr = [50 01 88 20 16 00 00 00];
592 hisilicon,sas-syscon = <&pcie_subctl>;
593 am-max-trans;
594 ctrl-reset-reg = <0xa18>;
595 ctrl-reset-sts-reg = <0x5a0c>;
596 ctrl-clock-ena-reg = <0x318>;
597 queue-count = <16>;
598 phy-count = <8>;
599 dma-coherent;
600 interrupt-parent = <&mbigen_sas1>;
601 interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
602 <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
603 <74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
604 <79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
605 <84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
606 <89 4>,<90 4>,<91 4>,<92 4>,<93 4>,
607 <94 4>,<95 4>,<96 4>,<97 4>,<98 4>,
608 <99 4>,<100 4>,<101 4>,<102 4>,<103 4>,
609 <104 4>,<105 4>,<106 4>,<107 4>,<108 4>,
610 <109 4>,<110 4>,<111 4>,<112 4>,<113 4>,
611 <114 4>,<115 4>,<116 4>,<117 4>,<118 4>,
612 <119 4>,<120 4>,<121 4>,<122 4>,<123 4>,
613 <124 4>,<125 4>,<126 4>,<127 4>,<128 4>,
614 <129 4>,<130 4>,<131 4>,<132 4>,<133 4>,
615 <134 4>,<135 4>,<136 4>,<137 4>,<138 4>,
616 <139 4>,<140 4>,<141 4>,<142 4>,<143 4>,
617 <144 4>,<145 4>,<146 4>,<147 4>,<148 4>,
618 <149 4>,<150 4>,<151 4>,<152 4>,<153 4>,
619 <154 4>,<155 4>,<156 4>,<157 4>,<158 4>,
620 <159 4>,<576 1>,<577 1>,<578 1>,<579 1>,
621 <580 1>,<581 1>,<582 1>,<583 1>,<584 1>,
622 <585 1>,<586 1>,<587 1>,<588 1>,<589 1>,
623 <590 1>,<591 1>,<592 1>,<593 1>,<594 1>,
624 <595 1>,<596 1>,<597 1>,<598 1>,<599 1>,
625 <600 1>,<601 1>,<602 1>,<603 1>,<604 1>,
626 <605 1>,<606 1>,<607 1>;
627 status = "disabled";
628 };
629
630 sas2: sas@a3000000 {
631 compatible = "hisilicon,hip06-sas-v2";
632 reg = <0 0xa3000000 0 0x10000>;
633 sas-addr = [50 01 88 20 16 00 00 00];
634 hisilicon,sas-syscon = <&pcie_subctl>;
635 ctrl-reset-reg = <0xae0>;
636 ctrl-reset-sts-reg = <0x5a70>;
637 ctrl-clock-ena-reg = <0x3a8>;
638 queue-count = <16>;
639 phy-count = <9>;
640 dma-coherent;
641 interrupt-parent = <&mbigen_sas2>;
642 interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>,
643 <197 4>,<198 4>,<199 4>,<200 4>,<201 4>,
644 <202 4>,<203 4>,<204 4>,<205 4>,<206 4>,
645 <207 4>,<208 4>,<209 4>,<210 4>,<211 4>,
646 <212 4>,<213 4>,<214 4>,<215 4>,<216 4>,
647 <217 4>,<218 4>,<219 4>,<220 4>,<221 4>,
648 <222 4>,<223 4>,<224 4>,<225 4>,<226 4>,
649 <227 4>,<228 4>,<229 4>,<230 4>,<231 4>,
650 <232 4>,<233 4>,<234 4>,<235 4>,<236 4>,
651 <237 4>,<238 4>,<239 4>,<240 4>,<241 4>,
652 <242 4>,<243 4>,<244 4>,<245 4>,<246 4>,
653 <247 4>,<248 4>,<249 4>,<250 4>,<251 4>,
654 <252 4>,<253 4>,<254 4>,<255 4>,<256 4>,
655 <257 4>,<258 4>,<259 4>,<260 4>,<261 4>,
656 <262 4>,<263 4>,<264 4>,<265 4>,<266 4>,
657 <267 4>,<268 4>,<269 4>,<270 4>,<271 4>,
658 <272 4>,<273 4>,<274 4>,<275 4>,<276 4>,
659 <277 4>,<278 4>,<279 4>,<280 4>,<281 4>,
660 <282 4>,<283 4>,<284 4>,<285 4>,<286 4>,
661 <287 4>,<608 1>,<609 1>,<610 1>,<611 1>,
662 <612 1>,<613 1>,<614 1>,<615 1>,<616 1>,
663 <617 1>,<618 1>,<619 1>,<620 1>,<621 1>,
664 <622 1>,<623 1>,<624 1>,<625 1>,<626 1>,
665 <627 1>,<628 1>,<629 1>,<630 1>,<631 1>,
666 <632 1>,<633 1>,<634 1>,<635 1>,<636 1>,
667 <637 1>,<638 1>,<639 1>;
668 status = "disabled";
669 };
520 }; 670 };
521 671
522}; 672};
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