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authorKefeng Wang <wangkefeng.wang@huawei.com>2016-08-15 03:03:43 -0400
committerWei Xu <xuwei5@hisilicon.com>2016-08-24 11:19:38 -0400
commit5350419fbaab0cf962ccd9de93e0fed1113d33e9 (patch)
tree64d1d0101eb09d0ddcdcce12052330f217d937b0 /arch/arm64/boot/dts
parent9f67f1185c550b88e6c75d005e2f26f5c7fde480 (diff)
arm64: dts: hip06: Append hns node
There are four ports(2 GE, 2 XGE) in D03 board, append relevant nodes for them. Cc: Kejian Yan <yankejian@huawei.com> Cc: Yisen Zhuang <yisen.zhuang@huawei.com> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Diffstat (limited to 'arch/arm64/boot/dts')
-rw-r--r--arch/arm64/boot/dts/hisilicon/hip06-d03.dts16
-rw-r--r--arch/arm64/boot/dts/hisilicon/hip06.dtsi215
2 files changed, 231 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
index f3e5323e430b..5562cf41df17 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
+++ b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
@@ -25,6 +25,22 @@
25 chosen { }; 25 chosen { };
26}; 26};
27 27
28&eth0 {
29 status = "ok";
30};
31
32&eth1 {
33 status = "ok";
34};
35
36&eth2 {
37 status = "ok";
38};
39
40&eth3 {
41 status = "ok";
42};
43
28&usb_ohci { 44&usb_ohci {
29 status = "ok"; 45 status = "ok";
30}; 46};
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 5927bc472f1b..ddbff81522a0 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -279,6 +279,18 @@
279 }; 279 };
280 }; 280 };
281 281
282 mbigen_dsa@c0080000 {
283 compatible = "hisilicon,mbigen-v2";
284 reg = <0x0 0xc0080000 0x0 0x10000>;
285
286 mbigen_dsaf0: intc_dsaf0 {
287 msi-parent = <&its_dsa 0x40800>;
288 interrupt-controller;
289 #interrupt-cells = <2>;
290 num-pins = <409>;
291 };
292 };
293
282 soc { 294 soc {
283 compatible = "simple-bus"; 295 compatible = "simple-bus";
284 #address-cells = <2>; 296 #address-cells = <2>;
@@ -302,6 +314,209 @@
302 dma-coherent; 314 dma-coherent;
303 status = "disabled"; 315 status = "disabled";
304 }; 316 };
317
318 peri_c_subctrl: sub_ctrl_c@60000000 {
319 compatible = "hisilicon,peri-subctrl","syscon";
320 reg = <0 0x60000000 0x0 0x10000>;
321 };
322
323 dsa_subctrl: dsa_subctrl@c0000000 {
324 compatible = "hisilicon,dsa-subctrl", "syscon";
325 reg = <0x0 0xc0000000 0x0 0x10000>;
326 };
327
328 serdes_ctrl: sds_ctrl@c2200000 {
329 compatible = "syscon";
330 reg = <0 0xc2200000 0x0 0x80000>;
331 };
332
333 mdio@603c0000 {
334 compatible = "hisilicon,hns-mdio";
335 reg = <0x0 0x603c0000 0x0 0x1000>;
336 subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>;
337 #address-cells = <1>;
338 #size-cells = <0>;
339
340 phy0: ethernet-phy@0 {
341 compatible = "ethernet-phy-ieee802.3-c22";
342 reg = <0>;
343 };
344
345 phy1: ethernet-phy@1 {
346 compatible = "ethernet-phy-ieee802.3-c22";
347 reg = <1>;
348 };
349 };
350
351 dsaf0: dsa@c7000000 {
352 #address-cells = <1>;
353 #size-cells = <0>;
354 compatible = "hisilicon,hns-dsaf-v2";
355 mode = "6port-16rss";
356 reg = <0x0 0xc5000000 0x0 0x890000
357 0x0 0xc7000000 0x0 0x600000>;
358 reg-names = "ppe-base", "dsaf-base";
359 interrupt-parent = <&mbigen_dsaf0>;
360 subctrl-syscon = <&dsa_subctrl>;
361 reset-field-offset = <0>;
362 interrupts =
363 <576 1>, <577 1>, <578 1>, <579 1>, <580 1>,
364 <581 1>, <582 1>, <583 1>, <584 1>, <585 1>,
365 <586 1>, <587 1>, <588 1>, <589 1>, <590 1>,
366 <591 1>, <592 1>, <593 1>, <594 1>, <595 1>,
367 <596 1>, <597 1>, <598 1>, <599 1>, <600 1>,
368 <960 1>, <961 1>, <962 1>, <963 1>, <964 1>,
369 <965 1>, <966 1>, <967 1>, <968 1>, <969 1>,
370 <970 1>, <971 1>, <972 1>, <973 1>, <974 1>,
371 <975 1>, <976 1>, <977 1>, <978 1>, <979 1>,
372 <980 1>, <981 1>, <982 1>, <983 1>, <984 1>,
373 <985 1>, <986 1>, <987 1>, <988 1>, <989 1>,
374 <990 1>, <991 1>, <992 1>, <993 1>, <994 1>,
375 <995 1>, <996 1>, <997 1>, <998 1>, <999 1>,
376 <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>,
377 <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>,
378 <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>,
379 <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>,
380 <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>,
381 <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>,
382 <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>,
383 <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>,
384 <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>,
385 <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>,
386 <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>,
387 <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>,
388 <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>,
389 <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>,
390 <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>,
391 <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>,
392 <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>,
393 <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>,
394 <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>,
395 <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>,
396 <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>,
397 <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>,
398 <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>,
399 <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>,
400 <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>,
401 <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>,
402 <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>,
403 <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>,
404 <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>,
405 <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>,
406 <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>,
407 <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>,
408 <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>,
409 <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>,
410 <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>,
411 <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>,
412 <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>,
413 <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>,
414 <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>,
415 <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>,
416 <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>,
417 <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>,
418 <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>,
419 <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>,
420 <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>,
421 <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>,
422 <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>,
423 <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>,
424 <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>,
425 <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>,
426 <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>,
427 <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>,
428 <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>,
429 <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>,
430 <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>,
431 <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>,
432 <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>,
433 <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>,
434 <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>,
435 <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>,
436 <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>,
437 <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>,
438 <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>,
439 <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>,
440 <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>,
441 <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>,
442 <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>,
443 <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>,
444 <1340 1>, <1341 1>, <1342 1>, <1343 1>;
445
446 desc-num = <0x400>;
447 buf-size = <0x1000>;
448 dma-coherent;
449
450 port@0 {
451 reg = <0>;
452 serdes-syscon = <&serdes_ctrl>;
453 port-rst-offset = <0>;
454 port-mode-offset = <0>;
455 media-type = "fiber";
456 };
457
458 port@1 {
459 reg = <1>;
460 serdes-syscon= <&serdes_ctrl>;
461 port-rst-offset = <1>;
462 port-mode-offset = <1>;
463 media-type = "fiber";
464 };
465
466 port@4 {
467 reg = <4>;
468 phy-handle = <&phy0>;
469 serdes-syscon= <&serdes_ctrl>;
470 port-rst-offset = <4>;
471 port-mode-offset = <2>;
472 media-type = "copper";
473 };
474
475 port@5 {
476 reg = <5>;
477 phy-handle = <&phy1>;
478 serdes-syscon= <&serdes_ctrl>;
479 port-rst-offset = <5>;
480 port-mode-offset = <3>;
481 media-type = "copper";
482 };
483 };
484
485 eth0: ethernet@4{
486 compatible = "hisilicon,hns-nic-v2";
487 ae-handle = <&dsaf0>;
488 port-idx-in-ae = <4>;
489 local-mac-address = [00 00 00 00 00 00];
490 status = "disabled";
491 dma-coherent;
492 };
493
494 eth1: ethernet@5{
495 compatible = "hisilicon,hns-nic-v2";
496 ae-handle = <&dsaf0>;
497 port-idx-in-ae = <5>;
498 local-mac-address = [00 00 00 00 00 00];
499 status = "disabled";
500 dma-coherent;
501 };
502
503 eth2: ethernet@0{
504 compatible = "hisilicon,hns-nic-v2";
505 ae-handle = <&dsaf0>;
506 port-idx-in-ae = <0>;
507 local-mac-address = [00 00 00 00 00 00];
508 status = "disabled";
509 dma-coherent;
510 };
511
512 eth3: ethernet@1{
513 compatible = "hisilicon,hns-nic-v2";
514 ae-handle = <&dsaf0>;
515 port-idx-in-ae = <1>;
516 local-mac-address = [00 00 00 00 00 00];
517 status = "disabled";
518 dma-coherent;
519 };
305 }; 520 };
306 521
307}; 522};
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 00:10:13 -0400