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authorMichael Turquette <mturquette@linaro.org>2015-01-30 13:57:21 -0500
committerMichael Turquette <mturquette@linaro.org>2015-02-02 17:23:33 -0500
commitfe767560523d7556cb11fef466adf4b10141d73b (patch)
treed70e4a3b6539f21eb675adce10ad965b95ed4dfe /arch/arm/mach-omap2
parent035a61c314eb3dab5bcc5683afaf4d412689858a (diff)
parentd6540b1937192271a11ee02c3d197ddc39090257 (diff)
Merge branch 'clk-omap-legacy' into clk-next
Conflicts: arch/arm/mach-omap2/cclock3xxx_data.c
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/Makefile2
-rw-r--r--arch/arm/mach-omap2/cclock3xxx_data.c3727
-rw-r--r--arch/arm/mach-omap2/io.c28
-rw-r--r--arch/arm/mach-omap2/prm.h1
-rw-r--r--arch/arm/mach-omap2/prm_common.c11
5 files changed, 32 insertions, 3737 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 5d27dfdef66b..d2a6b271e85b 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -187,7 +187,7 @@ obj-$(CONFIG_SOC_OMAP2430) += clock2430.o
187obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o 187obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
188obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o 188obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
189obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o 189obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
190obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o 190obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o
191obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o 191obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
192obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) 192obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
193obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o 193obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
deleted file mode 100644
index adb4e6437204..000000000000
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ /dev/null
@@ -1,3727 +0,0 @@
1/*
2 * OMAP3 clock data
3 *
4 * Copyright (C) 2007-2012 Texas Instruments, Inc.
5 * Copyright (C) 2007-2011 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * Updated to COMMON clk data format by Rajendra Nayak <rnayak@ti.com>
9 * With many device clock fixes by Kevin Hilman and Jouni Högander
10 * DPLL bypass clock support added by Roman Tereshonkov
11 *
12 */
13
14/*
15 * Virtual clocks are introduced as convenient tools.
16 * They are sources for other clocks and not supposed
17 * to be requested from drivers directly.
18 */
19
20#include <linux/kernel.h>
21#include <linux/clk.h>
22#include <linux/clk-private.h>
23#include <linux/list.h>
24#include <linux/io.h>
25
26#include "soc.h"
27#include "iomap.h"
28#include "clock.h"
29#include "clock3xxx.h"
30#include "clock34xx.h"
31#include "clock36xx.h"
32#include "clock3517.h"
33#include "cm3xxx.h"
34#include "cm-regbits-34xx.h"
35#include "prm3xxx.h"
36#include "prm-regbits-34xx.h"
37#include "control.h"
38
39/*
40 * clocks
41 */
42
43#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
44
45/* Maximum DPLL multiplier, divider values for OMAP3 */
46#define OMAP3_MAX_DPLL_MULT 2047
47#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
48#define OMAP3_MAX_DPLL_DIV 128
49
50DEFINE_CLK_FIXED_RATE(dummy_apb_pclk, CLK_IS_ROOT, 0x0, 0x0);
51
52DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
53
54DEFINE_CLK_FIXED_RATE(omap_32k_fck, CLK_IS_ROOT, 32768, 0x0);
55
56DEFINE_CLK_FIXED_RATE(pclk_ck, CLK_IS_ROOT, 27000000, 0x0);
57
58DEFINE_CLK_FIXED_RATE(rmii_ck, CLK_IS_ROOT, 50000000, 0x0);
59
60DEFINE_CLK_FIXED_RATE(secure_32k_fck, CLK_IS_ROOT, 32768, 0x0);
61
62DEFINE_CLK_FIXED_RATE(sys_altclk, CLK_IS_ROOT, 0x0, 0x0);
63
64DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0);
65
66DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0);
67
68DEFINE_CLK_FIXED_RATE(virt_16_8m_ck, CLK_IS_ROOT, 16800000, 0x0);
69
70DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
71
72DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
73
74DEFINE_CLK_FIXED_RATE(virt_38_4m_ck, CLK_IS_ROOT, 38400000, 0x0);
75
76static const char *osc_sys_ck_parent_names[] = {
77 "virt_12m_ck", "virt_13m_ck", "virt_19200000_ck", "virt_26000000_ck",
78 "virt_38_4m_ck", "virt_16_8m_ck",
79};
80
81DEFINE_CLK_MUX(osc_sys_ck, osc_sys_ck_parent_names, NULL, 0x0,
82 OMAP3430_PRM_CLKSEL, OMAP3430_SYS_CLKIN_SEL_SHIFT,
83 OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0, NULL);
84
85DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck_core, 0x0,
86 OMAP3430_PRM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
87 OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
88
89static struct dpll_data dpll3_dd = {
90 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
91 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
92 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
93 .clk_bypass = &sys_ck,
94 .clk_ref = &sys_ck,
95 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
96 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
97 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
98 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
99 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
100 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
101 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
102 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
103 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
104 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
105 .max_multiplier = OMAP3_MAX_DPLL_MULT,
106 .min_divider = 1,
107 .max_divider = OMAP3_MAX_DPLL_DIV,
108};
109
110static struct clk dpll3_ck;
111
112static const char *dpll3_ck_parent_names[] = {
113 "sys_ck",
114 "sys_ck",
115};
116
117static const struct clk_ops dpll3_ck_ops = {
118 .init = &omap2_init_clk_clkdm,
119 .get_parent = &omap2_init_dpll_parent,
120 .recalc_rate = &omap3_dpll_recalc,
121 .round_rate = &omap2_dpll_round_rate,
122};
123
124static struct clk_hw_omap dpll3_ck_hw = {
125 .hw = {
126 .clk = &dpll3_ck,
127 },
128 .ops = &clkhwops_omap3_dpll,
129 .dpll_data = &dpll3_dd,
130 .clkdm_name = "dpll3_clkdm",
131};
132
133DEFINE_STRUCT_CLK(dpll3_ck, dpll3_ck_parent_names, dpll3_ck_ops);
134
135DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck_core, 0x0,
136 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
137 OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT,
138 OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH,
139 CLK_DIVIDER_ONE_BASED, NULL);
140
141static struct clk core_ck;
142
143static const char *core_ck_parent_names[] = {
144 "dpll3_m2_ck",
145};
146
147static const struct clk_ops core_ck_ops = {};
148
149DEFINE_STRUCT_CLK_HW_OMAP(core_ck, NULL);
150DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
151
152DEFINE_CLK_DIVIDER(l3_ick, "core_ck", &core_ck_core, 0x0,
153 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
154 OMAP3430_CLKSEL_L3_SHIFT, OMAP3430_CLKSEL_L3_WIDTH,
155 CLK_DIVIDER_ONE_BASED, NULL);
156
157DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick_core, 0x0,
158 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
159 OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH,
160 CLK_DIVIDER_ONE_BASED, NULL);
161
162static struct clk security_l4_ick2;
163
164static const char *security_l4_ick2_parent_names[] = {
165 "l4_ick",
166};
167
168DEFINE_STRUCT_CLK_HW_OMAP(security_l4_ick2, NULL);
169DEFINE_STRUCT_CLK(security_l4_ick2, security_l4_ick2_parent_names, core_ck_ops);
170
171static struct clk aes1_ick;
172
173static const char *aes1_ick_parent_names[] = {
174 "security_l4_ick2",
175};
176
177static const struct clk_ops aes1_ick_ops = {
178 .enable = &omap2_dflt_clk_enable,
179 .disable = &omap2_dflt_clk_disable,
180 .is_enabled = &omap2_dflt_clk_is_enabled,
181};
182
183static struct clk_hw_omap aes1_ick_hw = {
184 .hw = {
185 .clk = &aes1_ick,
186 },
187 .ops = &clkhwops_iclk_wait,
188 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
189 .enable_bit = OMAP3430_EN_AES1_SHIFT,
190};
191
192DEFINE_STRUCT_CLK(aes1_ick, aes1_ick_parent_names, aes1_ick_ops);
193
194static struct clk core_l4_ick;
195
196static const struct clk_ops core_l4_ick_ops = {
197 .init = &omap2_init_clk_clkdm,
198};
199
200DEFINE_STRUCT_CLK_HW_OMAP(core_l4_ick, "core_l4_clkdm");
201DEFINE_STRUCT_CLK(core_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
202
203static struct clk aes2_ick;
204
205static const char *aes2_ick_parent_names[] = {
206 "core_l4_ick",
207};
208
209static const struct clk_ops aes2_ick_ops = {
210 .init = &omap2_init_clk_clkdm,
211 .enable = &omap2_dflt_clk_enable,
212 .disable = &omap2_dflt_clk_disable,
213 .is_enabled = &omap2_dflt_clk_is_enabled,
214};
215
216static struct clk_hw_omap aes2_ick_hw = {
217 .hw = {
218 .clk = &aes2_ick,
219 },
220 .ops = &clkhwops_iclk_wait,
221 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
222 .enable_bit = OMAP3430_EN_AES2_SHIFT,
223 .clkdm_name = "core_l4_clkdm",
224};
225
226DEFINE_STRUCT_CLK(aes2_ick, aes2_ick_parent_names, aes2_ick_ops);
227
228static struct clk dpll1_fck;
229
230static struct dpll_data dpll1_dd = {
231 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
232 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
233 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
234 .clk_bypass = &dpll1_fck,
235 .clk_ref = &sys_ck,
236 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
237 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
238 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
239 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
240 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
241 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
242 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
243 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
244 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
245 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
246 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
247 .max_multiplier = OMAP3_MAX_DPLL_MULT,
248 .min_divider = 1,
249 .max_divider = OMAP3_MAX_DPLL_DIV,
250};
251
252static struct clk dpll1_ck;
253
254static const struct clk_ops dpll1_ck_ops = {
255 .init = &omap2_init_clk_clkdm,
256 .enable = &omap3_noncore_dpll_enable,
257 .disable = &omap3_noncore_dpll_disable,
258 .get_parent = &omap2_init_dpll_parent,
259 .recalc_rate = &omap3_dpll_recalc,
260 .set_rate = &omap3_noncore_dpll_set_rate,
261 .set_parent = &omap3_noncore_dpll_set_parent,
262 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
263 .determine_rate = &omap3_noncore_dpll_determine_rate,
264 .round_rate = &omap2_dpll_round_rate,
265};
266
267static struct clk_hw_omap dpll1_ck_hw = {
268 .hw = {
269 .clk = &dpll1_ck,
270 },
271 .ops = &clkhwops_omap3_dpll,
272 .dpll_data = &dpll1_dd,
273 .clkdm_name = "dpll1_clkdm",
274};
275
276DEFINE_STRUCT_CLK(dpll1_ck, dpll3_ck_parent_names, dpll1_ck_ops);
277
278DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck, "dpll1_ck", &dpll1_ck_core, 0x0, 2, 1);
279
280DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck_core, 0x0,
281 OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
282 OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT,
283 OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH,
284 CLK_DIVIDER_ONE_BASED, NULL);
285
286static struct clk mpu_ck;
287
288static const char *mpu_ck_parent_names[] = {
289 "dpll1_x2m2_ck",
290};
291
292DEFINE_STRUCT_CLK_HW_OMAP(mpu_ck, "mpu_clkdm");
293DEFINE_STRUCT_CLK(mpu_ck, mpu_ck_parent_names, core_l4_ick_ops);
294
295DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck_core, 0x0,
296 OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
297 OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH,
298 0x0, NULL);
299
300static struct clk cam_ick;
301
302static struct clk_hw_omap cam_ick_hw = {
303 .hw = {
304 .clk = &cam_ick,
305 },
306 .ops = &clkhwops_iclk,
307 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
308 .enable_bit = OMAP3430_EN_CAM_SHIFT,
309 .clkdm_name = "cam_clkdm",
310};
311
312DEFINE_STRUCT_CLK(cam_ick, security_l4_ick2_parent_names, aes2_ick_ops);
313
314/* DPLL4 */
315/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
316/* Type: DPLL */
317static struct dpll_data dpll4_dd;
318
319static struct dpll_data dpll4_dd_34xx __initdata = {
320 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
321 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
322 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
323 .clk_bypass = &sys_ck,
324 .clk_ref = &sys_ck,
325 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
326 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
327 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
328 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
329 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
330 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
331 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
332 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
333 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
334 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
335 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
336 .max_multiplier = OMAP3_MAX_DPLL_MULT,
337 .min_divider = 1,
338 .max_divider = OMAP3_MAX_DPLL_DIV,
339};
340
341static struct dpll_data dpll4_dd_3630 __initdata = {
342 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
343 .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
344 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
345 .clk_bypass = &sys_ck,
346 .clk_ref = &sys_ck,
347 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
348 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
349 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
350 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
351 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
352 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
353 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
354 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
355 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
356 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
357 .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
358 .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
359 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
360 .min_divider = 1,
361 .max_divider = OMAP3_MAX_DPLL_DIV,
362 .flags = DPLL_J_TYPE
363};
364
365static struct clk dpll4_ck;
366
367static const struct clk_ops dpll4_ck_ops = {
368 .init = &omap2_init_clk_clkdm,
369 .enable = &omap3_noncore_dpll_enable,
370 .disable = &omap3_noncore_dpll_disable,
371 .get_parent = &omap2_init_dpll_parent,
372 .recalc_rate = &omap3_dpll_recalc,
373 .set_rate = &omap3_dpll4_set_rate,
374 .set_parent = &omap3_noncore_dpll_set_parent,
375 .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent,
376 .determine_rate = &omap3_noncore_dpll_determine_rate,
377 .round_rate = &omap2_dpll_round_rate,
378};
379
380static struct clk_hw_omap dpll4_ck_hw = {
381 .hw = {
382 .clk = &dpll4_ck,
383 },
384 .dpll_data = &dpll4_dd,
385 .ops = &clkhwops_omap3_dpll,
386 .clkdm_name = "dpll4_clkdm",
387};
388
389DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops);
390
391static const struct clk_div_table dpll4_mx_ck_div_table[] = {
392 { .div = 1, .val = 1 },
393 { .div = 2, .val = 2 },
394 { .div = 3, .val = 3 },
395 { .div = 4, .val = 4 },
396 { .div = 5, .val = 5 },
397 { .div = 6, .val = 6 },
398 { .div = 7, .val = 7 },
399 { .div = 8, .val = 8 },
400 { .div = 9, .val = 9 },
401 { .div = 10, .val = 10 },
402 { .div = 11, .val = 11 },
403 { .div = 12, .val = 12 },
404 { .div = 13, .val = 13 },
405 { .div = 14, .val = 14 },
406 { .div = 15, .val = 15 },
407 { .div = 16, .val = 16 },
408 { .div = 17, .val = 17 },
409 { .div = 18, .val = 18 },
410 { .div = 19, .val = 19 },
411 { .div = 20, .val = 20 },
412 { .div = 21, .val = 21 },
413 { .div = 22, .val = 22 },
414 { .div = 23, .val = 23 },
415 { .div = 24, .val = 24 },
416 { .div = 25, .val = 25 },
417 { .div = 26, .val = 26 },
418 { .div = 27, .val = 27 },
419 { .div = 28, .val = 28 },
420 { .div = 29, .val = 29 },
421 { .div = 30, .val = 30 },
422 { .div = 31, .val = 31 },
423 { .div = 32, .val = 32 },
424 { .div = 0 },
425};
426
427DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck_core, 0x0,
428 OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
429 OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH,
430 CLK_DIVIDER_ONE_BASED, NULL);
431
432static struct clk dpll4_m5x2_ck;
433
434static const char *dpll4_m5x2_ck_parent_names[] = {
435 "dpll4_m5_ck",
436};
437
438static const struct clk_ops dpll4_m5x2_ck_ops = {
439 .init = &omap2_init_clk_clkdm,
440 .enable = &omap2_dflt_clk_enable,
441 .disable = &omap2_dflt_clk_disable,
442 .is_enabled = &omap2_dflt_clk_is_enabled,
443 .set_rate = &omap3_clkoutx2_set_rate,
444 .recalc_rate = &omap3_clkoutx2_recalc,
445 .round_rate = &omap3_clkoutx2_round_rate,
446};
447
448static const struct clk_ops dpll4_m5x2_ck_3630_ops = {
449 .init = &omap2_init_clk_clkdm,
450 .enable = &omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
451 .disable = &omap2_dflt_clk_disable,
452 .recalc_rate = &omap3_clkoutx2_recalc,
453};
454
455static struct clk_hw_omap dpll4_m5x2_ck_hw = {
456 .hw = {
457 .clk = &dpll4_m5x2_ck,
458 },
459 .ops = &clkhwops_wait,
460 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
461 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
462 .flags = INVERT_ENABLE,
463 .clkdm_name = "dpll4_clkdm",
464};
465
466DEFINE_STRUCT_CLK_FLAGS(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names,
467 dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
468
469static struct clk_core dpll4_m5x2_ck_3630_core = {
470 .name = "dpll4_m5x2_ck",
471 .hw = &dpll4_m5x2_ck_hw.hw,
472 .parent_names = dpll4_m5x2_ck_parent_names,
473 .num_parents = ARRAY_SIZE(dpll4_m5x2_ck_parent_names),
474 .ops = &dpll4_m5x2_ck_3630_ops,
475 .flags = CLK_SET_RATE_PARENT,
476};
477
478static struct clk dpll4_m5x2_ck_3630 = {
479 .core = &dpll4_m5x2_ck_3630_core,
480};
481
482static struct clk cam_mclk;
483
484static const char *cam_mclk_parent_names[] = {
485 "dpll4_m5x2_ck",
486};
487
488static struct clk_hw_omap cam_mclk_hw = {
489 .hw = {
490 .clk = &cam_mclk,
491 },
492 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
493 .enable_bit = OMAP3430_EN_CAM_SHIFT,
494 .clkdm_name = "cam_clkdm",
495};
496
497static struct clk_core cam_mclk_core = {
498 .name = "cam_mclk",
499 .hw = &cam_mclk_hw.hw,
500 .parent_names = cam_mclk_parent_names,
501 .num_parents = ARRAY_SIZE(cam_mclk_parent_names),
502 .ops = &aes2_ick_ops,
503 .flags = CLK_SET_RATE_PARENT,
504};
505
506static struct clk cam_mclk = {
507 .core = &cam_mclk_core,
508};
509
510static const struct clksel_rate clkout2_src_core_rates[] = {
511 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
512 { .div = 0 }
513};
514
515static const struct clksel_rate clkout2_src_sys_rates[] = {
516 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
517 { .div = 0 }
518};
519
520static const struct clksel_rate clkout2_src_96m_rates[] = {
521 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
522 { .div = 0 }
523};
524
525DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck_core, 0x0,
526 OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
527 OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH,
528 CLK_DIVIDER_ONE_BASED, NULL);
529
530static struct clk dpll4_m2x2_ck;
531
532static const char *dpll4_m2x2_ck_parent_names[] = {
533 "dpll4_m2_ck",
534};
535
536static struct clk_hw_omap dpll4_m2x2_ck_hw = {
537 .hw = {
538 .clk = &dpll4_m2x2_ck,
539 },
540 .ops = &clkhwops_wait,
541 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
542 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
543 .flags = INVERT_ENABLE,
544 .clkdm_name = "dpll4_clkdm",
545};
546
547DEFINE_STRUCT_CLK(dpll4_m2x2_ck, dpll4_m2x2_ck_parent_names, dpll4_m5x2_ck_ops);
548
549static struct clk_core dpll4_m2x2_ck_3630_core = {
550 .name = "dpll4_m2x2_ck",
551 .hw = &dpll4_m2x2_ck_hw.hw,
552 .parent_names = dpll4_m2x2_ck_parent_names,
553 .num_parents = ARRAY_SIZE(dpll4_m2x2_ck_parent_names),
554 .ops = &dpll4_m5x2_ck_3630_ops,
555};
556
557static struct clk dpll4_m2x2_ck_3630 = {
558 .core = &dpll4_m2x2_ck_3630_core,
559};
560
561static struct clk omap_96m_alwon_fck;
562
563static const char *omap_96m_alwon_fck_parent_names[] = {
564 "dpll4_m2x2_ck",
565};
566
567DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck, NULL);
568DEFINE_STRUCT_CLK(omap_96m_alwon_fck, omap_96m_alwon_fck_parent_names,
569 core_ck_ops);
570
571static struct clk cm_96m_fck;
572
573static const char *cm_96m_fck_parent_names[] = {
574 "omap_96m_alwon_fck",
575};
576
577DEFINE_STRUCT_CLK_HW_OMAP(cm_96m_fck, NULL);
578DEFINE_STRUCT_CLK(cm_96m_fck, cm_96m_fck_parent_names, core_ck_ops);
579
580static const struct clksel_rate clkout2_src_54m_rates[] = {
581 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
582 { .div = 0 }
583};
584
585DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck, "dpll4_ck", &dpll4_ck_core, 0x0,
586 OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
587 OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,
588 0, dpll4_mx_ck_div_table, NULL);
589
590static struct clk dpll4_m3x2_ck;
591
592static const char *dpll4_m3x2_ck_parent_names[] = {
593 "dpll4_m3_ck",
594};
595
596static struct clk_hw_omap dpll4_m3x2_ck_hw = {
597 .hw = {
598 .clk = &dpll4_m3x2_ck,
599 },
600 .ops = &clkhwops_wait,
601 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
602 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
603 .flags = INVERT_ENABLE,
604 .clkdm_name = "dpll4_clkdm",
605};
606
607DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
608
609static struct clk_core dpll4_m3x2_ck_3630_core = {
610 .name = "dpll4_m3x2_ck",
611 .hw = &dpll4_m3x2_ck_hw.hw,
612 .parent_names = dpll4_m3x2_ck_parent_names,
613 .num_parents = ARRAY_SIZE(dpll4_m3x2_ck_parent_names),
614 .ops = &dpll4_m5x2_ck_3630_ops,
615};
616
617static struct clk dpll4_m3x2_ck_3630 = {
618 .core = &dpll4_m3x2_ck_3630_core,
619};
620
621static const char *omap_54m_fck_parent_names[] = {
622 "dpll4_m3x2_ck", "sys_altclk",
623};
624
625DEFINE_CLK_MUX(omap_54m_fck, omap_54m_fck_parent_names, NULL, 0x0,
626 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP3430_SOURCE_54M_SHIFT,
627 OMAP3430_SOURCE_54M_WIDTH, 0x0, NULL);
628
629static const struct clksel clkout2_src_clksel[] = {
630 { .parent = &core_ck, .rates = clkout2_src_core_rates },
631 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
632 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
633 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
634 { .parent = NULL },
635};
636
637static const char *clkout2_src_ck_parent_names[] = {
638 "core_ck", "sys_ck", "cm_96m_fck", "omap_54m_fck",
639};
640
641static const struct clk_ops clkout2_src_ck_ops = {
642 .init = &omap2_init_clk_clkdm,
643 .enable = &omap2_dflt_clk_enable,
644 .disable = &omap2_dflt_clk_disable,
645 .is_enabled = &omap2_dflt_clk_is_enabled,
646 .recalc_rate = &omap2_clksel_recalc,
647 .get_parent = &omap2_clksel_find_parent_index,
648 .set_parent = &omap2_clksel_set_parent,
649};
650
651DEFINE_CLK_OMAP_MUX_GATE(clkout2_src_ck, "core_clkdm",
652 clkout2_src_clksel, OMAP3430_CM_CLKOUT_CTRL,
653 OMAP3430_CLKOUT2SOURCE_MASK,
654 OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_EN_SHIFT,
655 NULL, clkout2_src_ck_parent_names, clkout2_src_ck_ops);
656
657static const struct clksel_rate omap_48m_cm96m_rates[] = {
658 { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
659 { .div = 0 }
660};
661
662static const struct clksel_rate omap_48m_alt_rates[] = {
663 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
664 { .div = 0 }
665};
666
667static const struct clksel omap_48m_clksel[] = {
668 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
669 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
670 { .parent = NULL },
671};
672
673static const char *omap_48m_fck_parent_names[] = {
674 "cm_96m_fck", "sys_altclk",
675};
676
677static struct clk omap_48m_fck;
678
679static const struct clk_ops omap_48m_fck_ops = {
680 .recalc_rate = &omap2_clksel_recalc,
681 .get_parent = &omap2_clksel_find_parent_index,
682 .set_parent = &omap2_clksel_set_parent,
683};
684
685static struct clk_hw_omap omap_48m_fck_hw = {
686 .hw = {
687 .clk = &omap_48m_fck,
688 },
689 .clksel = omap_48m_clksel,
690 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
691 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
692};
693
694DEFINE_STRUCT_CLK(omap_48m_fck, omap_48m_fck_parent_names, omap_48m_fck_ops);
695
696DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck_core, 0x0,
697 1, 4);
698
699static struct clk core_12m_fck;
700
701static const char *core_12m_fck_parent_names[] = {
702 "omap_12m_fck",
703};
704
705DEFINE_STRUCT_CLK_HW_OMAP(core_12m_fck, "core_l4_clkdm");
706DEFINE_STRUCT_CLK(core_12m_fck, core_12m_fck_parent_names, core_l4_ick_ops);
707
708static struct clk core_48m_fck;
709
710static const char *core_48m_fck_parent_names[] = {
711 "omap_48m_fck",
712};
713
714DEFINE_STRUCT_CLK_HW_OMAP(core_48m_fck, "core_l4_clkdm");
715DEFINE_STRUCT_CLK(core_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
716
717static const char *omap_96m_fck_parent_names[] = {
718 "cm_96m_fck", "sys_ck",
719};
720
721DEFINE_CLK_MUX(omap_96m_fck, omap_96m_fck_parent_names, NULL, 0x0,
722 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
723 OMAP3430_SOURCE_96M_SHIFT, OMAP3430_SOURCE_96M_WIDTH, 0x0, NULL);
724
725static struct clk core_96m_fck;
726
727static const char *core_96m_fck_parent_names[] = {
728 "omap_96m_fck",
729};
730
731DEFINE_STRUCT_CLK_HW_OMAP(core_96m_fck, "core_l4_clkdm");
732DEFINE_STRUCT_CLK(core_96m_fck, core_96m_fck_parent_names, core_l4_ick_ops);
733
734static struct clk core_l3_ick;
735
736static const char *core_l3_ick_parent_names[] = {
737 "l3_ick",
738};
739
740DEFINE_STRUCT_CLK_HW_OMAP(core_l3_ick, "core_l3_clkdm");
741DEFINE_STRUCT_CLK(core_l3_ick, core_l3_ick_parent_names, core_l4_ick_ops);
742
743DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck_core, 0x0,
744 2, 1);
745
746static struct clk corex2_fck;
747
748static const char *corex2_fck_parent_names[] = {
749 "dpll3_m2x2_ck",
750};
751
752DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL);
753DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops);
754
755static const char *cpefuse_fck_parent_names[] = {
756 "sys_ck",
757};
758
759static struct clk cpefuse_fck;
760
761static struct clk_hw_omap cpefuse_fck_hw = {
762 .hw = {
763 .clk = &cpefuse_fck,
764 },
765 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
766 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
767 .clkdm_name = "core_l4_clkdm",
768};
769
770DEFINE_STRUCT_CLK(cpefuse_fck, cpefuse_fck_parent_names, aes2_ick_ops);
771
772static struct clk csi2_96m_fck;
773
774static const char *csi2_96m_fck_parent_names[] = {
775 "core_96m_fck",
776};
777
778static struct clk_hw_omap csi2_96m_fck_hw = {
779 .hw = {
780 .clk = &csi2_96m_fck,
781 },
782 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
783 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
784 .clkdm_name = "cam_clkdm",
785};
786
787DEFINE_STRUCT_CLK(csi2_96m_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
788
789static struct clk d2d_26m_fck;
790
791static struct clk_hw_omap d2d_26m_fck_hw = {
792 .hw = {
793 .clk = &d2d_26m_fck,
794 },
795 .ops = &clkhwops_wait,
796 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
797 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
798 .clkdm_name = "d2d_clkdm",
799};
800
801DEFINE_STRUCT_CLK(d2d_26m_fck, cpefuse_fck_parent_names, aes2_ick_ops);
802
803static struct clk des1_ick;
804
805static struct clk_hw_omap des1_ick_hw = {
806 .hw = {
807 .clk = &des1_ick,
808 },
809 .ops = &clkhwops_iclk_wait,
810 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
811 .enable_bit = OMAP3430_EN_DES1_SHIFT,
812};
813
814DEFINE_STRUCT_CLK(des1_ick, aes1_ick_parent_names, aes1_ick_ops);
815
816static struct clk des2_ick;
817
818static struct clk_hw_omap des2_ick_hw = {
819 .hw = {
820 .clk = &des2_ick,
821 },
822 .ops = &clkhwops_iclk_wait,
823 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
824 .enable_bit = OMAP3430_EN_DES2_SHIFT,
825 .clkdm_name = "core_l4_clkdm",
826};
827
828DEFINE_STRUCT_CLK(des2_ick, aes2_ick_parent_names, aes2_ick_ops);
829
830DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck_core, 0x0,
831 OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
832 OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH,
833 CLK_DIVIDER_ONE_BASED, NULL);
834
835static struct clk dpll2_fck;
836
837static struct dpll_data dpll2_dd = {
838 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
839 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
840 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
841 .clk_bypass = &dpll2_fck,
842 .clk_ref = &sys_ck,
843 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
844 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
845 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
846 .modes = ((1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
847 (1 << DPLL_LOW_POWER_BYPASS)),
848 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
849 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
850 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
851 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
852 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
853 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
854 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
855 .max_multiplier = OMAP3_MAX_DPLL_MULT,
856 .min_divider = 1,
857 .max_divider = OMAP3_MAX_DPLL_DIV,
858};
859
860static struct clk dpll2_ck;
861
862static struct clk_hw_omap dpll2_ck_hw = {
863 .hw = {
864 .clk = &dpll2_ck,
865 },
866 .ops = &clkhwops_omap3_dpll,
867 .dpll_data = &dpll2_dd,
868 .clkdm_name = "dpll2_clkdm",
869};
870
871DEFINE_STRUCT_CLK(dpll2_ck, dpll3_ck_parent_names, dpll1_ck_ops);
872
873DEFINE_CLK_DIVIDER(dpll2_fck, "core_ck", &core_ck_core, 0x0,
874 OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
875 OMAP3430_IVA2_CLK_SRC_SHIFT, OMAP3430_IVA2_CLK_SRC_WIDTH,
876 CLK_DIVIDER_ONE_BASED, NULL);
877
878DEFINE_CLK_DIVIDER(dpll2_m2_ck, "dpll2_ck", &dpll2_ck_core, 0x0,
879 OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
880 OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT,
881 OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH,
882 CLK_DIVIDER_ONE_BASED, NULL);
883
884DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck_core, 0x0,
885 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
886 OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH,
887 CLK_DIVIDER_ONE_BASED, NULL);
888
889static struct clk dpll3_m3x2_ck;
890
891static const char *dpll3_m3x2_ck_parent_names[] = {
892 "dpll3_m3_ck",
893};
894
895static struct clk_hw_omap dpll3_m3x2_ck_hw = {
896 .hw = {
897 .clk = &dpll3_m3x2_ck,
898 },
899 .ops = &clkhwops_wait,
900 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
901 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
902 .flags = INVERT_ENABLE,
903 .clkdm_name = "dpll3_clkdm",
904};
905
906DEFINE_STRUCT_CLK(dpll3_m3x2_ck, dpll3_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
907
908static struct clk_core dpll3_m3x2_ck_3630_core = {
909 .name = "dpll3_m3x2_ck",
910 .hw = &dpll3_m3x2_ck_hw.hw,
911 .parent_names = dpll3_m3x2_ck_parent_names,
912 .num_parents = ARRAY_SIZE(dpll3_m3x2_ck_parent_names),
913 .ops = &dpll4_m5x2_ck_3630_ops,
914};
915
916static struct clk dpll3_m3x2_ck_3630 = {
917 .core = &dpll3_m3x2_ck_3630_core,
918};
919
920DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck_core, 0x0, 2, 1);
921
922DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck, "dpll4_ck", &dpll4_ck_core, 0x0,
923 OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
924 OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH,
925 0, dpll4_mx_ck_div_table, NULL);
926
927static struct clk dpll4_m4x2_ck;
928
929static const char *dpll4_m4x2_ck_parent_names[] = {
930 "dpll4_m4_ck",
931};
932
933static struct clk_hw_omap dpll4_m4x2_ck_hw = {
934 .hw = {
935 .clk = &dpll4_m4x2_ck,
936 },
937 .ops = &clkhwops_wait,
938 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
939 .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
940 .flags = INVERT_ENABLE,
941 .clkdm_name = "dpll4_clkdm",
942};
943
944DEFINE_STRUCT_CLK_FLAGS(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names,
945 dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
946
947static struct clk_core dpll4_m4x2_ck_3630_core = {
948 .name = "dpll4_m4x2_ck",
949 .hw = &dpll4_m4x2_ck_hw.hw,
950 .parent_names = dpll4_m4x2_ck_parent_names,
951 .num_parents = ARRAY_SIZE(dpll4_m4x2_ck_parent_names),
952 .ops = &dpll4_m5x2_ck_3630_ops,
953 .flags = CLK_SET_RATE_PARENT,
954};
955
956static struct clk dpll4_m4x2_ck_3630 = {
957 .core = &dpll4_m4x2_ck_3630_core,
958};
959
960DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck_core, 0x0,
961 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
962 OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH,
963 CLK_DIVIDER_ONE_BASED, NULL);
964
965static struct clk dpll4_m6x2_ck;
966
967static const char *dpll4_m6x2_ck_parent_names[] = {
968 "dpll4_m6_ck",
969};
970
971static struct clk_hw_omap dpll4_m6x2_ck_hw = {
972 .hw = {
973 .clk = &dpll4_m6x2_ck,
974 },
975 .ops = &clkhwops_wait,
976 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
977 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
978 .flags = INVERT_ENABLE,
979 .clkdm_name = "dpll4_clkdm",
980};
981
982DEFINE_STRUCT_CLK(dpll4_m6x2_ck, dpll4_m6x2_ck_parent_names, dpll4_m5x2_ck_ops);
983
984static struct clk_core dpll4_m6x2_ck_3630_core = {
985 .name = "dpll4_m6x2_ck",
986 .hw = &dpll4_m6x2_ck_hw.hw,
987 .parent_names = dpll4_m6x2_ck_parent_names,
988 .num_parents = ARRAY_SIZE(dpll4_m6x2_ck_parent_names),
989 .ops = &dpll4_m5x2_ck_3630_ops,
990};
991
992static struct clk dpll4_m6x2_ck_3630 = {
993 .core = &dpll4_m6x2_ck_3630_core,
994};
995
996DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck, "dpll4_ck", &dpll4_ck_core, 0x0, 2, 1);
997
998static struct dpll_data dpll5_dd = {
999 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
1000 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
1001 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
1002 .clk_bypass = &sys_ck,
1003 .clk_ref = &sys_ck,
1004 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
1005 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
1006 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
1007 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
1008 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
1009 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
1010 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
1011 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
1012 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
1013 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
1014 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
1015 .max_multiplier = OMAP3_MAX_DPLL_MULT,
1016 .min_divider = 1,
1017 .max_divider = OMAP3_MAX_DPLL_DIV,
1018};
1019
1020static struct clk dpll5_ck;
1021
1022static struct clk_hw_omap dpll5_ck_hw = {
1023 .hw = {
1024 .clk = &dpll5_ck,
1025 },
1026 .ops = &clkhwops_omap3_dpll,
1027 .dpll_data = &dpll5_dd,
1028 .clkdm_name = "dpll5_clkdm",
1029};
1030
1031DEFINE_STRUCT_CLK(dpll5_ck, dpll3_ck_parent_names, dpll1_ck_ops);
1032
1033DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck_core, 0x0,
1034 OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
1035 OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH,
1036 CLK_DIVIDER_ONE_BASED, NULL);
1037
1038static struct clk dss1_alwon_fck_3430es1;
1039
1040static const char *dss1_alwon_fck_3430es1_parent_names[] = {
1041 "dpll4_m4x2_ck",
1042};
1043
1044static struct clk_hw_omap dss1_alwon_fck_3430es1_hw = {
1045 .hw = {
1046 .clk = &dss1_alwon_fck_3430es1,
1047 },
1048 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1049 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
1050 .clkdm_name = "dss_clkdm",
1051};
1052
1053DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es1,
1054 dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops,
1055 CLK_SET_RATE_PARENT);
1056
1057static struct clk dss1_alwon_fck_3430es2;
1058
1059static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = {
1060 .hw = {
1061 .clk = &dss1_alwon_fck_3430es2,
1062 },
1063 .ops = &clkhwops_omap3430es2_dss_usbhost_wait,
1064 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1065 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
1066 .clkdm_name = "dss_clkdm",
1067};
1068
1069DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es2,
1070 dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops,
1071 CLK_SET_RATE_PARENT);
1072
1073static struct clk dss2_alwon_fck;
1074
1075static struct clk_hw_omap dss2_alwon_fck_hw = {
1076 .hw = {
1077 .clk = &dss2_alwon_fck,
1078 },
1079 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1080 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
1081 .clkdm_name = "dss_clkdm",
1082};
1083
1084DEFINE_STRUCT_CLK(dss2_alwon_fck, cpefuse_fck_parent_names, aes2_ick_ops);
1085
1086static struct clk dss_96m_fck;
1087
1088static struct clk_hw_omap dss_96m_fck_hw = {
1089 .hw = {
1090 .clk = &dss_96m_fck,
1091 },
1092 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1093 .enable_bit = OMAP3430_EN_TV_SHIFT,
1094 .clkdm_name = "dss_clkdm",
1095};
1096
1097DEFINE_STRUCT_CLK(dss_96m_fck, core_96m_fck_parent_names, aes2_ick_ops);
1098
1099static struct clk dss_ick_3430es1;
1100
1101static struct clk_hw_omap dss_ick_3430es1_hw = {
1102 .hw = {
1103 .clk = &dss_ick_3430es1,
1104 },
1105 .ops = &clkhwops_iclk,
1106 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1107 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1108 .clkdm_name = "dss_clkdm",
1109};
1110
1111DEFINE_STRUCT_CLK(dss_ick_3430es1, security_l4_ick2_parent_names, aes2_ick_ops);
1112
1113static struct clk dss_ick_3430es2;
1114
1115static struct clk_hw_omap dss_ick_3430es2_hw = {
1116 .hw = {
1117 .clk = &dss_ick_3430es2,
1118 },
1119 .ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
1120 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1121 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1122 .clkdm_name = "dss_clkdm",
1123};
1124
1125DEFINE_STRUCT_CLK(dss_ick_3430es2, security_l4_ick2_parent_names, aes2_ick_ops);
1126
1127static struct clk dss_tv_fck;
1128
1129static const char *dss_tv_fck_parent_names[] = {
1130 "omap_54m_fck",
1131};
1132
1133static struct clk_hw_omap dss_tv_fck_hw = {
1134 .hw = {
1135 .clk = &dss_tv_fck,
1136 },
1137 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1138 .enable_bit = OMAP3430_EN_TV_SHIFT,
1139 .clkdm_name = "dss_clkdm",
1140};
1141
1142DEFINE_STRUCT_CLK(dss_tv_fck, dss_tv_fck_parent_names, aes2_ick_ops);
1143
1144static struct clk emac_fck;
1145
1146static const char *emac_fck_parent_names[] = {
1147 "rmii_ck",
1148};
1149
1150static struct clk_hw_omap emac_fck_hw = {
1151 .hw = {
1152 .clk = &emac_fck,
1153 },
1154 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1155 .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
1156};
1157
1158DEFINE_STRUCT_CLK(emac_fck, emac_fck_parent_names, aes1_ick_ops);
1159
1160static struct clk ipss_ick;
1161
1162static const char *ipss_ick_parent_names[] = {
1163 "core_l3_ick",
1164};
1165
1166static struct clk_hw_omap ipss_ick_hw = {
1167 .hw = {
1168 .clk = &ipss_ick,
1169 },
1170 .ops = &clkhwops_am35xx_ipss_wait,
1171 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1172 .enable_bit = AM35XX_EN_IPSS_SHIFT,
1173 .clkdm_name = "core_l3_clkdm",
1174};
1175
1176DEFINE_STRUCT_CLK(ipss_ick, ipss_ick_parent_names, aes2_ick_ops);
1177
1178static struct clk emac_ick;
1179
1180static const char *emac_ick_parent_names[] = {
1181 "ipss_ick",
1182};
1183
1184static struct clk_hw_omap emac_ick_hw = {
1185 .hw = {
1186 .clk = &emac_ick,
1187 },
1188 .ops = &clkhwops_am35xx_ipss_module_wait,
1189 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1190 .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
1191 .clkdm_name = "core_l3_clkdm",
1192};
1193
1194DEFINE_STRUCT_CLK(emac_ick, emac_ick_parent_names, aes2_ick_ops);
1195
1196static struct clk emu_core_alwon_ck;
1197
1198static const char *emu_core_alwon_ck_parent_names[] = {
1199 "dpll3_m3x2_ck",
1200};
1201
1202DEFINE_STRUCT_CLK_HW_OMAP(emu_core_alwon_ck, "dpll3_clkdm");
1203DEFINE_STRUCT_CLK(emu_core_alwon_ck, emu_core_alwon_ck_parent_names,
1204 core_l4_ick_ops);
1205
1206static struct clk emu_mpu_alwon_ck;
1207
1208static const char *emu_mpu_alwon_ck_parent_names[] = {
1209 "mpu_ck",
1210};
1211
1212DEFINE_STRUCT_CLK_HW_OMAP(emu_mpu_alwon_ck, NULL);
1213DEFINE_STRUCT_CLK(emu_mpu_alwon_ck, emu_mpu_alwon_ck_parent_names, core_ck_ops);
1214
1215static struct clk emu_per_alwon_ck;
1216
1217static const char *emu_per_alwon_ck_parent_names[] = {
1218 "dpll4_m6x2_ck",
1219};
1220
1221DEFINE_STRUCT_CLK_HW_OMAP(emu_per_alwon_ck, "dpll4_clkdm");
1222DEFINE_STRUCT_CLK(emu_per_alwon_ck, emu_per_alwon_ck_parent_names,
1223 core_l4_ick_ops);
1224
1225static const char *emu_src_ck_parent_names[] = {
1226 "sys_ck", "emu_core_alwon_ck", "emu_per_alwon_ck", "emu_mpu_alwon_ck",
1227};
1228
1229static const struct clksel_rate emu_src_sys_rates[] = {
1230 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1231 { .div = 0 },
1232};
1233
1234static const struct clksel_rate emu_src_core_rates[] = {
1235 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1236 { .div = 0 },
1237};
1238
1239static const struct clksel_rate emu_src_per_rates[] = {
1240 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
1241 { .div = 0 },
1242};
1243
1244static const struct clksel_rate emu_src_mpu_rates[] = {
1245 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1246 { .div = 0 },
1247};
1248
1249static const struct clksel emu_src_clksel[] = {
1250 { .parent = &sys_ck, .rates = emu_src_sys_rates },
1251 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
1252 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
1253 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
1254 { .parent = NULL },
1255};
1256
1257static const struct clk_ops emu_src_ck_ops = {
1258 .init = &omap2_init_clk_clkdm,
1259 .recalc_rate = &omap2_clksel_recalc,
1260 .get_parent = &omap2_clksel_find_parent_index,
1261 .set_parent = &omap2_clksel_set_parent,
1262 .enable = &omap2_clkops_enable_clkdm,
1263 .disable = &omap2_clkops_disable_clkdm,
1264};
1265
1266static struct clk emu_src_ck;
1267
1268static struct clk_hw_omap emu_src_ck_hw = {
1269 .hw = {
1270 .clk = &emu_src_ck,
1271 },
1272 .clksel = emu_src_clksel,
1273 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1274 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
1275 .clkdm_name = "emu_clkdm",
1276};
1277
1278DEFINE_STRUCT_CLK(emu_src_ck, emu_src_ck_parent_names, emu_src_ck_ops);
1279
1280DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck_core, 0x0,
1281 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1282 OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH,
1283 CLK_DIVIDER_ONE_BASED, NULL);
1284
1285static struct clk fac_ick;
1286
1287static struct clk_hw_omap fac_ick_hw = {
1288 .hw = {
1289 .clk = &fac_ick,
1290 },
1291 .ops = &clkhwops_iclk_wait,
1292 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1293 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1294 .clkdm_name = "core_l4_clkdm",
1295};
1296
1297DEFINE_STRUCT_CLK(fac_ick, aes2_ick_parent_names, aes2_ick_ops);
1298
1299static struct clk fshostusb_fck;
1300
1301static const char *fshostusb_fck_parent_names[] = {
1302 "core_48m_fck",
1303};
1304
1305static struct clk_hw_omap fshostusb_fck_hw = {
1306 .hw = {
1307 .clk = &fshostusb_fck,
1308 },
1309 .ops = &clkhwops_wait,
1310 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1311 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1312 .clkdm_name = "core_l4_clkdm",
1313};
1314
1315DEFINE_STRUCT_CLK(fshostusb_fck, fshostusb_fck_parent_names, aes2_ick_ops);
1316
1317static struct clk gfx_l3_ck;
1318
1319static struct clk_hw_omap gfx_l3_ck_hw = {
1320 .hw = {
1321 .clk = &gfx_l3_ck,
1322 },
1323 .ops = &clkhwops_wait,
1324 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1325 .enable_bit = OMAP_EN_GFX_SHIFT,
1326 .clkdm_name = "gfx_3430es1_clkdm",
1327};
1328
1329DEFINE_STRUCT_CLK(gfx_l3_ck, core_l3_ick_parent_names, aes1_ick_ops);
1330
1331DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick_core, 0x0,
1332 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1333 OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH,
1334 CLK_DIVIDER_ONE_BASED, NULL);
1335
1336static struct clk gfx_cg1_ck;
1337
1338static const char *gfx_cg1_ck_parent_names[] = {
1339 "gfx_l3_fck",
1340};
1341
1342static struct clk_hw_omap gfx_cg1_ck_hw = {
1343 .hw = {
1344 .clk = &gfx_cg1_ck,
1345 },
1346 .ops = &clkhwops_wait,
1347 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1348 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1349 .clkdm_name = "gfx_3430es1_clkdm",
1350};
1351
1352DEFINE_STRUCT_CLK(gfx_cg1_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1353
1354static struct clk gfx_cg2_ck;
1355
1356static struct clk_hw_omap gfx_cg2_ck_hw = {
1357 .hw = {
1358 .clk = &gfx_cg2_ck,
1359 },
1360 .ops = &clkhwops_wait,
1361 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1362 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1363 .clkdm_name = "gfx_3430es1_clkdm",
1364};
1365
1366DEFINE_STRUCT_CLK(gfx_cg2_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1367
1368static struct clk gfx_l3_ick;
1369
1370static const char *gfx_l3_ick_parent_names[] = {
1371 "gfx_l3_ck",
1372};
1373
1374DEFINE_STRUCT_CLK_HW_OMAP(gfx_l3_ick, "gfx_3430es1_clkdm");
1375DEFINE_STRUCT_CLK(gfx_l3_ick, gfx_l3_ick_parent_names, core_l4_ick_ops);
1376
1377static struct clk wkup_32k_fck;
1378
1379static const char *wkup_32k_fck_parent_names[] = {
1380 "omap_32k_fck",
1381};
1382
1383DEFINE_STRUCT_CLK_HW_OMAP(wkup_32k_fck, "wkup_clkdm");
1384DEFINE_STRUCT_CLK(wkup_32k_fck, wkup_32k_fck_parent_names, core_l4_ick_ops);
1385
1386static struct clk gpio1_dbck;
1387
1388static const char *gpio1_dbck_parent_names[] = {
1389 "wkup_32k_fck",
1390};
1391
1392static struct clk_hw_omap gpio1_dbck_hw = {
1393 .hw = {
1394 .clk = &gpio1_dbck,
1395 },
1396 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1397 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
1398 .clkdm_name = "wkup_clkdm",
1399};
1400
1401DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops);
1402
1403static struct clk wkup_l4_ick;
1404
1405DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm");
1406DEFINE_STRUCT_CLK(wkup_l4_ick, cpefuse_fck_parent_names, core_l4_ick_ops);
1407
1408static struct clk gpio1_ick;
1409
1410static const char *gpio1_ick_parent_names[] = {
1411 "wkup_l4_ick",
1412};
1413
1414static struct clk_hw_omap gpio1_ick_hw = {
1415 .hw = {
1416 .clk = &gpio1_ick,
1417 },
1418 .ops = &clkhwops_iclk_wait,
1419 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1420 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
1421 .clkdm_name = "wkup_clkdm",
1422};
1423
1424DEFINE_STRUCT_CLK(gpio1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1425
1426static struct clk per_32k_alwon_fck;
1427
1428DEFINE_STRUCT_CLK_HW_OMAP(per_32k_alwon_fck, "per_clkdm");
1429DEFINE_STRUCT_CLK(per_32k_alwon_fck, wkup_32k_fck_parent_names,
1430 core_l4_ick_ops);
1431
1432static struct clk gpio2_dbck;
1433
1434static const char *gpio2_dbck_parent_names[] = {
1435 "per_32k_alwon_fck",
1436};
1437
1438static struct clk_hw_omap gpio2_dbck_hw = {
1439 .hw = {
1440 .clk = &gpio2_dbck,
1441 },
1442 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1443 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
1444 .clkdm_name = "per_clkdm",
1445};
1446
1447DEFINE_STRUCT_CLK(gpio2_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1448
1449static struct clk per_l4_ick;
1450
1451DEFINE_STRUCT_CLK_HW_OMAP(per_l4_ick, "per_clkdm");
1452DEFINE_STRUCT_CLK(per_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
1453
1454static struct clk gpio2_ick;
1455
1456static const char *gpio2_ick_parent_names[] = {
1457 "per_l4_ick",
1458};
1459
1460static struct clk_hw_omap gpio2_ick_hw = {
1461 .hw = {
1462 .clk = &gpio2_ick,
1463 },
1464 .ops = &clkhwops_iclk_wait,
1465 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1466 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
1467 .clkdm_name = "per_clkdm",
1468};
1469
1470DEFINE_STRUCT_CLK(gpio2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1471
1472static struct clk gpio3_dbck;
1473
1474static struct clk_hw_omap gpio3_dbck_hw = {
1475 .hw = {
1476 .clk = &gpio3_dbck,
1477 },
1478 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1479 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
1480 .clkdm_name = "per_clkdm",
1481};
1482
1483DEFINE_STRUCT_CLK(gpio3_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1484
1485static struct clk gpio3_ick;
1486
1487static struct clk_hw_omap gpio3_ick_hw = {
1488 .hw = {
1489 .clk = &gpio3_ick,
1490 },
1491 .ops = &clkhwops_iclk_wait,
1492 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1493 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
1494 .clkdm_name = "per_clkdm",
1495};
1496
1497DEFINE_STRUCT_CLK(gpio3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1498
1499static struct clk gpio4_dbck;
1500
1501static struct clk_hw_omap gpio4_dbck_hw = {
1502 .hw = {
1503 .clk = &gpio4_dbck,
1504 },
1505 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1506 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
1507 .clkdm_name = "per_clkdm",
1508};
1509
1510DEFINE_STRUCT_CLK(gpio4_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1511
1512static struct clk gpio4_ick;
1513
1514static struct clk_hw_omap gpio4_ick_hw = {
1515 .hw = {
1516 .clk = &gpio4_ick,
1517 },
1518 .ops = &clkhwops_iclk_wait,
1519 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1520 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
1521 .clkdm_name = "per_clkdm",
1522};
1523
1524DEFINE_STRUCT_CLK(gpio4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1525
1526static struct clk gpio5_dbck;
1527
1528static struct clk_hw_omap gpio5_dbck_hw = {
1529 .hw = {
1530 .clk = &gpio5_dbck,
1531 },
1532 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1533 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
1534 .clkdm_name = "per_clkdm",
1535};
1536
1537DEFINE_STRUCT_CLK(gpio5_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1538
1539static struct clk gpio5_ick;
1540
1541static struct clk_hw_omap gpio5_ick_hw = {
1542 .hw = {
1543 .clk = &gpio5_ick,
1544 },
1545 .ops = &clkhwops_iclk_wait,
1546 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1547 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
1548 .clkdm_name = "per_clkdm",
1549};
1550
1551DEFINE_STRUCT_CLK(gpio5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1552
1553static struct clk gpio6_dbck;
1554
1555static struct clk_hw_omap gpio6_dbck_hw = {
1556 .hw = {
1557 .clk = &gpio6_dbck,
1558 },
1559 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1560 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
1561 .clkdm_name = "per_clkdm",
1562};
1563
1564DEFINE_STRUCT_CLK(gpio6_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1565
1566static struct clk gpio6_ick;
1567
1568static struct clk_hw_omap gpio6_ick_hw = {
1569 .hw = {
1570 .clk = &gpio6_ick,
1571 },
1572 .ops = &clkhwops_iclk_wait,
1573 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1574 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
1575 .clkdm_name = "per_clkdm",
1576};
1577
1578DEFINE_STRUCT_CLK(gpio6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1579
1580static struct clk gpmc_fck;
1581
1582static struct clk_hw_omap gpmc_fck_hw = {
1583 .hw = {
1584 .clk = &gpmc_fck,
1585 },
1586 .flags = ENABLE_ON_INIT,
1587 .clkdm_name = "core_l3_clkdm",
1588};
1589
1590DEFINE_STRUCT_CLK(gpmc_fck, ipss_ick_parent_names, core_l4_ick_ops);
1591
1592static const struct clksel omap343x_gpt_clksel[] = {
1593 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1594 { .parent = &sys_ck, .rates = gpt_sys_rates },
1595 { .parent = NULL },
1596};
1597
1598static const char *gpt10_fck_parent_names[] = {
1599 "omap_32k_fck", "sys_ck",
1600};
1601
1602DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1603 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1604 OMAP3430_CLKSEL_GPT10_MASK,
1605 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1606 OMAP3430_EN_GPT10_SHIFT, &clkhwops_wait,
1607 gpt10_fck_parent_names, clkout2_src_ck_ops);
1608
1609static struct clk gpt10_ick;
1610
1611static struct clk_hw_omap gpt10_ick_hw = {
1612 .hw = {
1613 .clk = &gpt10_ick,
1614 },
1615 .ops = &clkhwops_iclk_wait,
1616 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1617 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1618 .clkdm_name = "core_l4_clkdm",
1619};
1620
1621DEFINE_STRUCT_CLK(gpt10_ick, aes2_ick_parent_names, aes2_ick_ops);
1622
1623DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1624 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1625 OMAP3430_CLKSEL_GPT11_MASK,
1626 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1627 OMAP3430_EN_GPT11_SHIFT, &clkhwops_wait,
1628 gpt10_fck_parent_names, clkout2_src_ck_ops);
1629
1630static struct clk gpt11_ick;
1631
1632static struct clk_hw_omap gpt11_ick_hw = {
1633 .hw = {
1634 .clk = &gpt11_ick,
1635 },
1636 .ops = &clkhwops_iclk_wait,
1637 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1638 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1639 .clkdm_name = "core_l4_clkdm",
1640};
1641
1642DEFINE_STRUCT_CLK(gpt11_ick, aes2_ick_parent_names, aes2_ick_ops);
1643
1644static struct clk gpt12_fck;
1645
1646static const char *gpt12_fck_parent_names[] = {
1647 "secure_32k_fck",
1648};
1649
1650DEFINE_STRUCT_CLK_HW_OMAP(gpt12_fck, "wkup_clkdm");
1651DEFINE_STRUCT_CLK(gpt12_fck, gpt12_fck_parent_names, core_l4_ick_ops);
1652
1653static struct clk gpt12_ick;
1654
1655static struct clk_hw_omap gpt12_ick_hw = {
1656 .hw = {
1657 .clk = &gpt12_ick,
1658 },
1659 .ops = &clkhwops_iclk_wait,
1660 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1661 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
1662 .clkdm_name = "wkup_clkdm",
1663};
1664
1665DEFINE_STRUCT_CLK(gpt12_ick, gpio1_ick_parent_names, aes2_ick_ops);
1666
1667DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "wkup_clkdm", omap343x_gpt_clksel,
1668 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1669 OMAP3430_CLKSEL_GPT1_MASK,
1670 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1671 OMAP3430_EN_GPT1_SHIFT, &clkhwops_wait,
1672 gpt10_fck_parent_names, clkout2_src_ck_ops);
1673
1674static struct clk gpt1_ick;
1675
1676static struct clk_hw_omap gpt1_ick_hw = {
1677 .hw = {
1678 .clk = &gpt1_ick,
1679 },
1680 .ops = &clkhwops_iclk_wait,
1681 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1682 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
1683 .clkdm_name = "wkup_clkdm",
1684};
1685
1686DEFINE_STRUCT_CLK(gpt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1687
1688DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "per_clkdm", omap343x_gpt_clksel,
1689 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1690 OMAP3430_CLKSEL_GPT2_MASK,
1691 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1692 OMAP3430_EN_GPT2_SHIFT, &clkhwops_wait,
1693 gpt10_fck_parent_names, clkout2_src_ck_ops);
1694
1695static struct clk gpt2_ick;
1696
1697static struct clk_hw_omap gpt2_ick_hw = {
1698 .hw = {
1699 .clk = &gpt2_ick,
1700 },
1701 .ops = &clkhwops_iclk_wait,
1702 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1703 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
1704 .clkdm_name = "per_clkdm",
1705};
1706
1707DEFINE_STRUCT_CLK(gpt2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1708
1709DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "per_clkdm", omap343x_gpt_clksel,
1710 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1711 OMAP3430_CLKSEL_GPT3_MASK,
1712 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1713 OMAP3430_EN_GPT3_SHIFT, &clkhwops_wait,
1714 gpt10_fck_parent_names, clkout2_src_ck_ops);
1715
1716static struct clk gpt3_ick;
1717
1718static struct clk_hw_omap gpt3_ick_hw = {
1719 .hw = {
1720 .clk = &gpt3_ick,
1721 },
1722 .ops = &clkhwops_iclk_wait,
1723 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1724 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
1725 .clkdm_name = "per_clkdm",
1726};
1727
1728DEFINE_STRUCT_CLK(gpt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1729
1730DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "per_clkdm", omap343x_gpt_clksel,
1731 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1732 OMAP3430_CLKSEL_GPT4_MASK,
1733 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1734 OMAP3430_EN_GPT4_SHIFT, &clkhwops_wait,
1735 gpt10_fck_parent_names, clkout2_src_ck_ops);
1736
1737static struct clk gpt4_ick;
1738
1739static struct clk_hw_omap gpt4_ick_hw = {
1740 .hw = {
1741 .clk = &gpt4_ick,
1742 },
1743 .ops = &clkhwops_iclk_wait,
1744 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1745 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
1746 .clkdm_name = "per_clkdm",
1747};
1748
1749DEFINE_STRUCT_CLK(gpt4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1750
1751DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "per_clkdm", omap343x_gpt_clksel,
1752 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1753 OMAP3430_CLKSEL_GPT5_MASK,
1754 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1755 OMAP3430_EN_GPT5_SHIFT, &clkhwops_wait,
1756 gpt10_fck_parent_names, clkout2_src_ck_ops);
1757
1758static struct clk gpt5_ick;
1759
1760static struct clk_hw_omap gpt5_ick_hw = {
1761 .hw = {
1762 .clk = &gpt5_ick,
1763 },
1764 .ops = &clkhwops_iclk_wait,
1765 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1766 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
1767 .clkdm_name = "per_clkdm",
1768};
1769
1770DEFINE_STRUCT_CLK(gpt5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1771
1772DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "per_clkdm", omap343x_gpt_clksel,
1773 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1774 OMAP3430_CLKSEL_GPT6_MASK,
1775 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1776 OMAP3430_EN_GPT6_SHIFT, &clkhwops_wait,
1777 gpt10_fck_parent_names, clkout2_src_ck_ops);
1778
1779static struct clk gpt6_ick;
1780
1781static struct clk_hw_omap gpt6_ick_hw = {
1782 .hw = {
1783 .clk = &gpt6_ick,
1784 },
1785 .ops = &clkhwops_iclk_wait,
1786 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1787 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
1788 .clkdm_name = "per_clkdm",
1789};
1790
1791DEFINE_STRUCT_CLK(gpt6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1792
1793DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "per_clkdm", omap343x_gpt_clksel,
1794 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1795 OMAP3430_CLKSEL_GPT7_MASK,
1796 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1797 OMAP3430_EN_GPT7_SHIFT, &clkhwops_wait,
1798 gpt10_fck_parent_names, clkout2_src_ck_ops);
1799
1800static struct clk gpt7_ick;
1801
1802static struct clk_hw_omap gpt7_ick_hw = {
1803 .hw = {
1804 .clk = &gpt7_ick,
1805 },
1806 .ops = &clkhwops_iclk_wait,
1807 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1808 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
1809 .clkdm_name = "per_clkdm",
1810};
1811
1812DEFINE_STRUCT_CLK(gpt7_ick, gpio2_ick_parent_names, aes2_ick_ops);
1813
1814DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "per_clkdm", omap343x_gpt_clksel,
1815 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1816 OMAP3430_CLKSEL_GPT8_MASK,
1817 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1818 OMAP3430_EN_GPT8_SHIFT, &clkhwops_wait,
1819 gpt10_fck_parent_names, clkout2_src_ck_ops);
1820
1821static struct clk gpt8_ick;
1822
1823static struct clk_hw_omap gpt8_ick_hw = {
1824 .hw = {
1825 .clk = &gpt8_ick,
1826 },
1827 .ops = &clkhwops_iclk_wait,
1828 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1829 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
1830 .clkdm_name = "per_clkdm",
1831};
1832
1833DEFINE_STRUCT_CLK(gpt8_ick, gpio2_ick_parent_names, aes2_ick_ops);
1834
1835DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "per_clkdm", omap343x_gpt_clksel,
1836 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1837 OMAP3430_CLKSEL_GPT9_MASK,
1838 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1839 OMAP3430_EN_GPT9_SHIFT, &clkhwops_wait,
1840 gpt10_fck_parent_names, clkout2_src_ck_ops);
1841
1842static struct clk gpt9_ick;
1843
1844static struct clk_hw_omap gpt9_ick_hw = {
1845 .hw = {
1846 .clk = &gpt9_ick,
1847 },
1848 .ops = &clkhwops_iclk_wait,
1849 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1850 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
1851 .clkdm_name = "per_clkdm",
1852};
1853
1854DEFINE_STRUCT_CLK(gpt9_ick, gpio2_ick_parent_names, aes2_ick_ops);
1855
1856static struct clk hdq_fck;
1857
1858static const char *hdq_fck_parent_names[] = {
1859 "core_12m_fck",
1860};
1861
1862static struct clk_hw_omap hdq_fck_hw = {
1863 .hw = {
1864 .clk = &hdq_fck,
1865 },
1866 .ops = &clkhwops_wait,
1867 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1868 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1869 .clkdm_name = "core_l4_clkdm",
1870};
1871
1872DEFINE_STRUCT_CLK(hdq_fck, hdq_fck_parent_names, aes2_ick_ops);
1873
1874static struct clk hdq_ick;
1875
1876static struct clk_hw_omap hdq_ick_hw = {
1877 .hw = {
1878 .clk = &hdq_ick,
1879 },
1880 .ops = &clkhwops_iclk_wait,
1881 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1882 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1883 .clkdm_name = "core_l4_clkdm",
1884};
1885
1886DEFINE_STRUCT_CLK(hdq_ick, aes2_ick_parent_names, aes2_ick_ops);
1887
1888static struct clk hecc_ck;
1889
1890static struct clk_hw_omap hecc_ck_hw = {
1891 .hw = {
1892 .clk = &hecc_ck,
1893 },
1894 .ops = &clkhwops_am35xx_ipss_module_wait,
1895 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1896 .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
1897 .clkdm_name = "core_l3_clkdm",
1898};
1899
1900DEFINE_STRUCT_CLK(hecc_ck, cpefuse_fck_parent_names, aes2_ick_ops);
1901
1902static struct clk hsotgusb_fck_am35xx;
1903
1904static struct clk_hw_omap hsotgusb_fck_am35xx_hw = {
1905 .hw = {
1906 .clk = &hsotgusb_fck_am35xx,
1907 },
1908 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1909 .enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
1910 .clkdm_name = "core_l3_clkdm",
1911};
1912
1913DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, cpefuse_fck_parent_names, aes2_ick_ops);
1914
1915static struct clk hsotgusb_ick_3430es1;
1916
1917static struct clk_hw_omap hsotgusb_ick_3430es1_hw = {
1918 .hw = {
1919 .clk = &hsotgusb_ick_3430es1,
1920 },
1921 .ops = &clkhwops_iclk,
1922 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1923 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1924 .clkdm_name = "core_l3_clkdm",
1925};
1926
1927DEFINE_STRUCT_CLK(hsotgusb_ick_3430es1, ipss_ick_parent_names, aes2_ick_ops);
1928
1929static struct clk hsotgusb_ick_3430es2;
1930
1931static struct clk_hw_omap hsotgusb_ick_3430es2_hw = {
1932 .hw = {
1933 .clk = &hsotgusb_ick_3430es2,
1934 },
1935 .ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait,
1936 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1937 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1938 .clkdm_name = "core_l3_clkdm",
1939};
1940
1941DEFINE_STRUCT_CLK(hsotgusb_ick_3430es2, ipss_ick_parent_names, aes2_ick_ops);
1942
1943static struct clk hsotgusb_ick_am35xx;
1944
1945static struct clk_hw_omap hsotgusb_ick_am35xx_hw = {
1946 .hw = {
1947 .clk = &hsotgusb_ick_am35xx,
1948 },
1949 .ops = &clkhwops_am35xx_ipss_module_wait,
1950 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1951 .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
1952 .clkdm_name = "core_l3_clkdm",
1953};
1954
1955DEFINE_STRUCT_CLK(hsotgusb_ick_am35xx, emac_ick_parent_names, aes2_ick_ops);
1956
1957static struct clk i2c1_fck;
1958
1959static struct clk_hw_omap i2c1_fck_hw = {
1960 .hw = {
1961 .clk = &i2c1_fck,
1962 },
1963 .ops = &clkhwops_wait,
1964 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1965 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1966 .clkdm_name = "core_l4_clkdm",
1967};
1968
1969DEFINE_STRUCT_CLK(i2c1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1970
1971static struct clk i2c1_ick;
1972
1973static struct clk_hw_omap i2c1_ick_hw = {
1974 .hw = {
1975 .clk = &i2c1_ick,
1976 },
1977 .ops = &clkhwops_iclk_wait,
1978 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1979 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1980 .clkdm_name = "core_l4_clkdm",
1981};
1982
1983DEFINE_STRUCT_CLK(i2c1_ick, aes2_ick_parent_names, aes2_ick_ops);
1984
1985static struct clk i2c2_fck;
1986
1987static struct clk_hw_omap i2c2_fck_hw = {
1988 .hw = {
1989 .clk = &i2c2_fck,
1990 },
1991 .ops = &clkhwops_wait,
1992 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1993 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1994 .clkdm_name = "core_l4_clkdm",
1995};
1996
1997DEFINE_STRUCT_CLK(i2c2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1998
1999static struct clk i2c2_ick;
2000
2001static struct clk_hw_omap i2c2_ick_hw = {
2002 .hw = {
2003 .clk = &i2c2_ick,
2004 },
2005 .ops = &clkhwops_iclk_wait,
2006 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2007 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
2008 .clkdm_name = "core_l4_clkdm",
2009};
2010
2011DEFINE_STRUCT_CLK(i2c2_ick, aes2_ick_parent_names, aes2_ick_ops);
2012
2013static struct clk i2c3_fck;
2014
2015static struct clk_hw_omap i2c3_fck_hw = {
2016 .hw = {
2017 .clk = &i2c3_fck,
2018 },
2019 .ops = &clkhwops_wait,
2020 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2021 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
2022 .clkdm_name = "core_l4_clkdm",
2023};
2024
2025DEFINE_STRUCT_CLK(i2c3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2026
2027static struct clk i2c3_ick;
2028
2029static struct clk_hw_omap i2c3_ick_hw = {
2030 .hw = {
2031 .clk = &i2c3_ick,
2032 },
2033 .ops = &clkhwops_iclk_wait,
2034 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2035 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
2036 .clkdm_name = "core_l4_clkdm",
2037};
2038
2039DEFINE_STRUCT_CLK(i2c3_ick, aes2_ick_parent_names, aes2_ick_ops);
2040
2041static struct clk icr_ick;
2042
2043static struct clk_hw_omap icr_ick_hw = {
2044 .hw = {
2045 .clk = &icr_ick,
2046 },
2047 .ops = &clkhwops_iclk_wait,
2048 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2049 .enable_bit = OMAP3430_EN_ICR_SHIFT,
2050 .clkdm_name = "core_l4_clkdm",
2051};
2052
2053DEFINE_STRUCT_CLK(icr_ick, aes2_ick_parent_names, aes2_ick_ops);
2054
2055static struct clk iva2_ck;
2056
2057static const char *iva2_ck_parent_names[] = {
2058 "dpll2_m2_ck",
2059};
2060
2061static struct clk_hw_omap iva2_ck_hw = {
2062 .hw = {
2063 .clk = &iva2_ck,
2064 },
2065 .ops = &clkhwops_wait,
2066 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
2067 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
2068 .clkdm_name = "iva2_clkdm",
2069};
2070
2071DEFINE_STRUCT_CLK(iva2_ck, iva2_ck_parent_names, aes2_ick_ops);
2072
2073static struct clk mad2d_ick;
2074
2075static struct clk_hw_omap mad2d_ick_hw = {
2076 .hw = {
2077 .clk = &mad2d_ick,
2078 },
2079 .ops = &clkhwops_iclk_wait,
2080 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2081 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
2082 .clkdm_name = "d2d_clkdm",
2083};
2084
2085DEFINE_STRUCT_CLK(mad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
2086
2087static struct clk mailboxes_ick;
2088
2089static struct clk_hw_omap mailboxes_ick_hw = {
2090 .hw = {
2091 .clk = &mailboxes_ick,
2092 },
2093 .ops = &clkhwops_iclk_wait,
2094 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2095 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2096 .clkdm_name = "core_l4_clkdm",
2097};
2098
2099DEFINE_STRUCT_CLK(mailboxes_ick, aes2_ick_parent_names, aes2_ick_ops);
2100
2101static const struct clksel_rate common_mcbsp_96m_rates[] = {
2102 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2103 { .div = 0 }
2104};
2105
2106static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
2107 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2108 { .div = 0 }
2109};
2110
2111static const struct clksel mcbsp_15_clksel[] = {
2112 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2113 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2114 { .parent = NULL },
2115};
2116
2117static const char *mcbsp1_fck_parent_names[] = {
2118 "core_96m_fck", "mcbsp_clks",
2119};
2120
2121DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_15_clksel,
2122 OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2123 OMAP2_MCBSP1_CLKS_MASK,
2124 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2125 OMAP3430_EN_MCBSP1_SHIFT, &clkhwops_wait,
2126 mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2127
2128static struct clk mcbsp1_ick;
2129
2130static struct clk_hw_omap mcbsp1_ick_hw = {
2131 .hw = {
2132 .clk = &mcbsp1_ick,
2133 },
2134 .ops = &clkhwops_iclk_wait,
2135 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2136 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2137 .clkdm_name = "core_l4_clkdm",
2138};
2139
2140DEFINE_STRUCT_CLK(mcbsp1_ick, aes2_ick_parent_names, aes2_ick_ops);
2141
2142static struct clk per_96m_fck;
2143
2144DEFINE_STRUCT_CLK_HW_OMAP(per_96m_fck, "per_clkdm");
2145DEFINE_STRUCT_CLK(per_96m_fck, cm_96m_fck_parent_names, core_l4_ick_ops);
2146
2147static const struct clksel mcbsp_234_clksel[] = {
2148 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2149 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2150 { .parent = NULL },
2151};
2152
2153static const char *mcbsp2_fck_parent_names[] = {
2154 "per_96m_fck", "mcbsp_clks",
2155};
2156
2157DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "per_clkdm", mcbsp_234_clksel,
2158 OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2159 OMAP2_MCBSP2_CLKS_MASK,
2160 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2161 OMAP3430_EN_MCBSP2_SHIFT, &clkhwops_wait,
2162 mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2163
2164static struct clk mcbsp2_ick;
2165
2166static struct clk_hw_omap mcbsp2_ick_hw = {
2167 .hw = {
2168 .clk = &mcbsp2_ick,
2169 },
2170 .ops = &clkhwops_iclk_wait,
2171 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2172 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2173 .clkdm_name = "per_clkdm",
2174};
2175
2176DEFINE_STRUCT_CLK(mcbsp2_ick, gpio2_ick_parent_names, aes2_ick_ops);
2177
2178DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "per_clkdm", mcbsp_234_clksel,
2179 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2180 OMAP2_MCBSP3_CLKS_MASK,
2181 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2182 OMAP3430_EN_MCBSP3_SHIFT, &clkhwops_wait,
2183 mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2184
2185static struct clk mcbsp3_ick;
2186
2187static struct clk_hw_omap mcbsp3_ick_hw = {
2188 .hw = {
2189 .clk = &mcbsp3_ick,
2190 },
2191 .ops = &clkhwops_iclk_wait,
2192 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2193 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2194 .clkdm_name = "per_clkdm",
2195};
2196
2197DEFINE_STRUCT_CLK(mcbsp3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2198
2199DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "per_clkdm", mcbsp_234_clksel,
2200 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2201 OMAP2_MCBSP4_CLKS_MASK,
2202 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2203 OMAP3430_EN_MCBSP4_SHIFT, &clkhwops_wait,
2204 mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2205
2206static struct clk mcbsp4_ick;
2207
2208static struct clk_hw_omap mcbsp4_ick_hw = {
2209 .hw = {
2210 .clk = &mcbsp4_ick,
2211 },
2212 .ops = &clkhwops_iclk_wait,
2213 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2214 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2215 .clkdm_name = "per_clkdm",
2216};
2217
2218DEFINE_STRUCT_CLK(mcbsp4_ick, gpio2_ick_parent_names, aes2_ick_ops);
2219
2220DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_15_clksel,
2221 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2222 OMAP2_MCBSP5_CLKS_MASK,
2223 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2224 OMAP3430_EN_MCBSP5_SHIFT, &clkhwops_wait,
2225 mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2226
2227static struct clk mcbsp5_ick;
2228
2229static struct clk_hw_omap mcbsp5_ick_hw = {
2230 .hw = {
2231 .clk = &mcbsp5_ick,
2232 },
2233 .ops = &clkhwops_iclk_wait,
2234 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2235 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2236 .clkdm_name = "core_l4_clkdm",
2237};
2238
2239DEFINE_STRUCT_CLK(mcbsp5_ick, aes2_ick_parent_names, aes2_ick_ops);
2240
2241static struct clk mcspi1_fck;
2242
2243static struct clk_hw_omap mcspi1_fck_hw = {
2244 .hw = {
2245 .clk = &mcspi1_fck,
2246 },
2247 .ops = &clkhwops_wait,
2248 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2249 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
2250 .clkdm_name = "core_l4_clkdm",
2251};
2252
2253DEFINE_STRUCT_CLK(mcspi1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2254
2255static struct clk mcspi1_ick;
2256
2257static struct clk_hw_omap mcspi1_ick_hw = {
2258 .hw = {
2259 .clk = &mcspi1_ick,
2260 },
2261 .ops = &clkhwops_iclk_wait,
2262 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2263 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
2264 .clkdm_name = "core_l4_clkdm",
2265};
2266
2267DEFINE_STRUCT_CLK(mcspi1_ick, aes2_ick_parent_names, aes2_ick_ops);
2268
2269static struct clk mcspi2_fck;
2270
2271static struct clk_hw_omap mcspi2_fck_hw = {
2272 .hw = {
2273 .clk = &mcspi2_fck,
2274 },
2275 .ops = &clkhwops_wait,
2276 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2277 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
2278 .clkdm_name = "core_l4_clkdm",
2279};
2280
2281DEFINE_STRUCT_CLK(mcspi2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2282
2283static struct clk mcspi2_ick;
2284
2285static struct clk_hw_omap mcspi2_ick_hw = {
2286 .hw = {
2287 .clk = &mcspi2_ick,
2288 },
2289 .ops = &clkhwops_iclk_wait,
2290 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2291 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
2292 .clkdm_name = "core_l4_clkdm",
2293};
2294
2295DEFINE_STRUCT_CLK(mcspi2_ick, aes2_ick_parent_names, aes2_ick_ops);
2296
2297static struct clk mcspi3_fck;
2298
2299static struct clk_hw_omap mcspi3_fck_hw = {
2300 .hw = {
2301 .clk = &mcspi3_fck,
2302 },
2303 .ops = &clkhwops_wait,
2304 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2305 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
2306 .clkdm_name = "core_l4_clkdm",
2307};
2308
2309DEFINE_STRUCT_CLK(mcspi3_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2310
2311static struct clk mcspi3_ick;
2312
2313static struct clk_hw_omap mcspi3_ick_hw = {
2314 .hw = {
2315 .clk = &mcspi3_ick,
2316 },
2317 .ops = &clkhwops_iclk_wait,
2318 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2319 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
2320 .clkdm_name = "core_l4_clkdm",
2321};
2322
2323DEFINE_STRUCT_CLK(mcspi3_ick, aes2_ick_parent_names, aes2_ick_ops);
2324
2325static struct clk mcspi4_fck;
2326
2327static struct clk_hw_omap mcspi4_fck_hw = {
2328 .hw = {
2329 .clk = &mcspi4_fck,
2330 },
2331 .ops = &clkhwops_wait,
2332 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2333 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
2334 .clkdm_name = "core_l4_clkdm",
2335};
2336
2337DEFINE_STRUCT_CLK(mcspi4_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2338
2339static struct clk mcspi4_ick;
2340
2341static struct clk_hw_omap mcspi4_ick_hw = {
2342 .hw = {
2343 .clk = &mcspi4_ick,
2344 },
2345 .ops = &clkhwops_iclk_wait,
2346 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2347 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
2348 .clkdm_name = "core_l4_clkdm",
2349};
2350
2351DEFINE_STRUCT_CLK(mcspi4_ick, aes2_ick_parent_names, aes2_ick_ops);
2352
2353static struct clk mmchs1_fck;
2354
2355static struct clk_hw_omap mmchs1_fck_hw = {
2356 .hw = {
2357 .clk = &mmchs1_fck,
2358 },
2359 .ops = &clkhwops_wait,
2360 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2361 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
2362 .clkdm_name = "core_l4_clkdm",
2363};
2364
2365DEFINE_STRUCT_CLK(mmchs1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2366
2367static struct clk mmchs1_ick;
2368
2369static struct clk_hw_omap mmchs1_ick_hw = {
2370 .hw = {
2371 .clk = &mmchs1_ick,
2372 },
2373 .ops = &clkhwops_iclk_wait,
2374 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2375 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
2376 .clkdm_name = "core_l4_clkdm",
2377};
2378
2379DEFINE_STRUCT_CLK(mmchs1_ick, aes2_ick_parent_names, aes2_ick_ops);
2380
2381static struct clk mmchs2_fck;
2382
2383static struct clk_hw_omap mmchs2_fck_hw = {
2384 .hw = {
2385 .clk = &mmchs2_fck,
2386 },
2387 .ops = &clkhwops_wait,
2388 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2389 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
2390 .clkdm_name = "core_l4_clkdm",
2391};
2392
2393DEFINE_STRUCT_CLK(mmchs2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2394
2395static struct clk mmchs2_ick;
2396
2397static struct clk_hw_omap mmchs2_ick_hw = {
2398 .hw = {
2399 .clk = &mmchs2_ick,
2400 },
2401 .ops = &clkhwops_iclk_wait,
2402 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2403 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
2404 .clkdm_name = "core_l4_clkdm",
2405};
2406
2407DEFINE_STRUCT_CLK(mmchs2_ick, aes2_ick_parent_names, aes2_ick_ops);
2408
2409static struct clk mmchs3_fck;
2410
2411static struct clk_hw_omap mmchs3_fck_hw = {
2412 .hw = {
2413 .clk = &mmchs3_fck,
2414 },
2415 .ops = &clkhwops_wait,
2416 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2417 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
2418 .clkdm_name = "core_l4_clkdm",
2419};
2420
2421DEFINE_STRUCT_CLK(mmchs3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2422
2423static struct clk mmchs3_ick;
2424
2425static struct clk_hw_omap mmchs3_ick_hw = {
2426 .hw = {
2427 .clk = &mmchs3_ick,
2428 },
2429 .ops = &clkhwops_iclk_wait,
2430 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2431 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
2432 .clkdm_name = "core_l4_clkdm",
2433};
2434
2435DEFINE_STRUCT_CLK(mmchs3_ick, aes2_ick_parent_names, aes2_ick_ops);
2436
2437static struct clk modem_fck;
2438
2439static struct clk_hw_omap modem_fck_hw = {
2440 .hw = {
2441 .clk = &modem_fck,
2442 },
2443 .ops = &clkhwops_iclk_wait,
2444 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2445 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
2446 .clkdm_name = "d2d_clkdm",
2447};
2448
2449DEFINE_STRUCT_CLK(modem_fck, cpefuse_fck_parent_names, aes2_ick_ops);
2450
2451static struct clk mspro_fck;
2452
2453static struct clk_hw_omap mspro_fck_hw = {
2454 .hw = {
2455 .clk = &mspro_fck,
2456 },
2457 .ops = &clkhwops_wait,
2458 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2459 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
2460 .clkdm_name = "core_l4_clkdm",
2461};
2462
2463DEFINE_STRUCT_CLK(mspro_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2464
2465static struct clk mspro_ick;
2466
2467static struct clk_hw_omap mspro_ick_hw = {
2468 .hw = {
2469 .clk = &mspro_ick,
2470 },
2471 .ops = &clkhwops_iclk_wait,
2472 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2473 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
2474 .clkdm_name = "core_l4_clkdm",
2475};
2476
2477DEFINE_STRUCT_CLK(mspro_ick, aes2_ick_parent_names, aes2_ick_ops);
2478
2479static struct clk omap_192m_alwon_fck;
2480
2481DEFINE_STRUCT_CLK_HW_OMAP(omap_192m_alwon_fck, NULL);
2482DEFINE_STRUCT_CLK(omap_192m_alwon_fck, omap_96m_alwon_fck_parent_names,
2483 core_ck_ops);
2484
2485static struct clk omap_32ksync_ick;
2486
2487static struct clk_hw_omap omap_32ksync_ick_hw = {
2488 .hw = {
2489 .clk = &omap_32ksync_ick,
2490 },
2491 .ops = &clkhwops_iclk_wait,
2492 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2493 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2494 .clkdm_name = "wkup_clkdm",
2495};
2496
2497DEFINE_STRUCT_CLK(omap_32ksync_ick, gpio1_ick_parent_names, aes2_ick_ops);
2498
2499static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
2500 { .div = 1, .val = 1, .flags = RATE_IN_36XX },
2501 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
2502 { .div = 0 }
2503};
2504
2505static const struct clksel omap_96m_alwon_fck_clksel[] = {
2506 { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
2507 { .parent = NULL }
2508};
2509
2510static struct clk omap_96m_alwon_fck_3630;
2511
2512static const char *omap_96m_alwon_fck_3630_parent_names[] = {
2513 "omap_192m_alwon_fck",
2514};
2515
2516static const struct clk_ops omap_96m_alwon_fck_3630_ops = {
2517 .set_rate = &omap2_clksel_set_rate,
2518 .recalc_rate = &omap2_clksel_recalc,
2519 .round_rate = &omap2_clksel_round_rate,
2520};
2521
2522static struct clk_hw_omap omap_96m_alwon_fck_3630_hw = {
2523 .hw = {
2524 .clk = &omap_96m_alwon_fck_3630,
2525 },
2526 .clksel = omap_96m_alwon_fck_clksel,
2527 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2528 .clksel_mask = OMAP3630_CLKSEL_96M_MASK,
2529};
2530
2531static struct clk_core omap_96m_alwon_fck_3630_core = {
2532 .name = "omap_96m_alwon_fck",
2533 .hw = &omap_96m_alwon_fck_3630_hw.hw,
2534 .parent_names = omap_96m_alwon_fck_3630_parent_names,
2535 .num_parents = ARRAY_SIZE(omap_96m_alwon_fck_3630_parent_names),
2536 .ops = &omap_96m_alwon_fck_3630_ops,
2537};
2538
2539static struct clk omap_96m_alwon_fck_3630 = {
2540 .core = &omap_96m_alwon_fck_3630_core,
2541};
2542
2543static struct clk omapctrl_ick;
2544
2545static struct clk_hw_omap omapctrl_ick_hw = {
2546 .hw = {
2547 .clk = &omapctrl_ick,
2548 },
2549 .ops = &clkhwops_iclk_wait,
2550 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2551 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2552 .flags = ENABLE_ON_INIT,
2553 .clkdm_name = "core_l4_clkdm",
2554};
2555
2556DEFINE_STRUCT_CLK(omapctrl_ick, aes2_ick_parent_names, aes2_ick_ops);
2557
2558DEFINE_CLK_DIVIDER(pclk_fck, "emu_src_ck", &emu_src_ck_core, 0x0,
2559 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2560 OMAP3430_CLKSEL_PCLK_SHIFT, OMAP3430_CLKSEL_PCLK_WIDTH,
2561 CLK_DIVIDER_ONE_BASED, NULL);
2562
2563DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck_core, 0x0,
2564 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2565 OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH,
2566 CLK_DIVIDER_ONE_BASED, NULL);
2567
2568static struct clk per_48m_fck;
2569
2570DEFINE_STRUCT_CLK_HW_OMAP(per_48m_fck, "per_clkdm");
2571DEFINE_STRUCT_CLK(per_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
2572
2573static struct clk security_l3_ick;
2574
2575DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick, NULL);
2576DEFINE_STRUCT_CLK(security_l3_ick, core_l3_ick_parent_names, core_ck_ops);
2577
2578static struct clk pka_ick;
2579
2580static const char *pka_ick_parent_names[] = {
2581 "security_l3_ick",
2582};
2583
2584static struct clk_hw_omap pka_ick_hw = {
2585 .hw = {
2586 .clk = &pka_ick,
2587 },
2588 .ops = &clkhwops_iclk_wait,
2589 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2590 .enable_bit = OMAP3430_EN_PKA_SHIFT,
2591};
2592
2593DEFINE_STRUCT_CLK(pka_ick, pka_ick_parent_names, aes1_ick_ops);
2594
2595DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick_core, 0x0,
2596 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2597 OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH,
2598 CLK_DIVIDER_ONE_BASED, NULL);
2599
2600static struct clk rng_ick;
2601
2602static struct clk_hw_omap rng_ick_hw = {
2603 .hw = {
2604 .clk = &rng_ick,
2605 },
2606 .ops = &clkhwops_iclk_wait,
2607 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2608 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2609};
2610
2611DEFINE_STRUCT_CLK(rng_ick, aes1_ick_parent_names, aes1_ick_ops);
2612
2613static struct clk sad2d_ick;
2614
2615static struct clk_hw_omap sad2d_ick_hw = {
2616 .hw = {
2617 .clk = &sad2d_ick,
2618 },
2619 .ops = &clkhwops_iclk_wait,
2620 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2621 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
2622 .clkdm_name = "d2d_clkdm",
2623};
2624
2625DEFINE_STRUCT_CLK(sad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
2626
2627static struct clk sdrc_ick;
2628
2629static struct clk_hw_omap sdrc_ick_hw = {
2630 .hw = {
2631 .clk = &sdrc_ick,
2632 },
2633 .ops = &clkhwops_wait,
2634 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2635 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
2636 .flags = ENABLE_ON_INIT,
2637 .clkdm_name = "core_l3_clkdm",
2638};
2639
2640DEFINE_STRUCT_CLK(sdrc_ick, ipss_ick_parent_names, aes2_ick_ops);
2641
2642static const struct clksel_rate sgx_core_rates[] = {
2643 { .div = 2, .val = 5, .flags = RATE_IN_36XX },
2644 { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
2645 { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
2646 { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
2647 { .div = 0 }
2648};
2649
2650static const struct clksel_rate sgx_96m_rates[] = {
2651 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2652 { .div = 0 }
2653};
2654
2655static const struct clksel_rate sgx_192m_rates[] = {
2656 { .div = 1, .val = 4, .flags = RATE_IN_36XX },
2657 { .div = 0 }
2658};
2659
2660static const struct clksel_rate sgx_corex2_rates[] = {
2661 { .div = 3, .val = 6, .flags = RATE_IN_36XX },
2662 { .div = 5, .val = 7, .flags = RATE_IN_36XX },
2663 { .div = 0 }
2664};
2665
2666static const struct clksel sgx_clksel[] = {
2667 { .parent = &core_ck, .rates = sgx_core_rates },
2668 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
2669 { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
2670 { .parent = &corex2_fck, .rates = sgx_corex2_rates },
2671 { .parent = NULL },
2672};
2673
2674static const char *sgx_fck_parent_names[] = {
2675 "core_ck", "cm_96m_fck", "omap_192m_alwon_fck", "corex2_fck",
2676};
2677
2678static struct clk sgx_fck;
2679
2680static const struct clk_ops sgx_fck_ops = {
2681 .init = &omap2_init_clk_clkdm,
2682 .enable = &omap2_dflt_clk_enable,
2683 .disable = &omap2_dflt_clk_disable,
2684 .is_enabled = &omap2_dflt_clk_is_enabled,
2685 .recalc_rate = &omap2_clksel_recalc,
2686 .set_rate = &omap2_clksel_set_rate,
2687 .round_rate = &omap2_clksel_round_rate,
2688 .get_parent = &omap2_clksel_find_parent_index,
2689 .set_parent = &omap2_clksel_set_parent,
2690};
2691
2692DEFINE_CLK_OMAP_MUX_GATE(sgx_fck, "sgx_clkdm", sgx_clksel,
2693 OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
2694 OMAP3430ES2_CLKSEL_SGX_MASK,
2695 OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
2696 OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
2697 &clkhwops_wait, sgx_fck_parent_names, sgx_fck_ops);
2698
2699static struct clk sgx_ick;
2700
2701static struct clk_hw_omap sgx_ick_hw = {
2702 .hw = {
2703 .clk = &sgx_ick,
2704 },
2705 .ops = &clkhwops_wait,
2706 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
2707 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
2708 .clkdm_name = "sgx_clkdm",
2709};
2710
2711DEFINE_STRUCT_CLK(sgx_ick, core_l3_ick_parent_names, aes2_ick_ops);
2712
2713static struct clk sha11_ick;
2714
2715static struct clk_hw_omap sha11_ick_hw = {
2716 .hw = {
2717 .clk = &sha11_ick,
2718 },
2719 .ops = &clkhwops_iclk_wait,
2720 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2721 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2722};
2723
2724DEFINE_STRUCT_CLK(sha11_ick, aes1_ick_parent_names, aes1_ick_ops);
2725
2726static struct clk sha12_ick;
2727
2728static struct clk_hw_omap sha12_ick_hw = {
2729 .hw = {
2730 .clk = &sha12_ick,
2731 },
2732 .ops = &clkhwops_iclk_wait,
2733 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2734 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
2735 .clkdm_name = "core_l4_clkdm",
2736};
2737
2738DEFINE_STRUCT_CLK(sha12_ick, aes2_ick_parent_names, aes2_ick_ops);
2739
2740static struct clk sr1_fck;
2741
2742static struct clk_hw_omap sr1_fck_hw = {
2743 .hw = {
2744 .clk = &sr1_fck,
2745 },
2746 .ops = &clkhwops_wait,
2747 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2748 .enable_bit = OMAP3430_EN_SR1_SHIFT,
2749 .clkdm_name = "wkup_clkdm",
2750};
2751
2752DEFINE_STRUCT_CLK(sr1_fck, cpefuse_fck_parent_names, aes2_ick_ops);
2753
2754static struct clk sr2_fck;
2755
2756static struct clk_hw_omap sr2_fck_hw = {
2757 .hw = {
2758 .clk = &sr2_fck,
2759 },
2760 .ops = &clkhwops_wait,
2761 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2762 .enable_bit = OMAP3430_EN_SR2_SHIFT,
2763 .clkdm_name = "wkup_clkdm",
2764};
2765
2766DEFINE_STRUCT_CLK(sr2_fck, cpefuse_fck_parent_names, aes2_ick_ops);
2767
2768static struct clk sr_l4_ick;
2769
2770DEFINE_STRUCT_CLK_HW_OMAP(sr_l4_ick, "core_l4_clkdm");
2771DEFINE_STRUCT_CLK(sr_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2772
2773static struct clk ssi_l4_ick;
2774
2775DEFINE_STRUCT_CLK_HW_OMAP(ssi_l4_ick, "core_l4_clkdm");
2776DEFINE_STRUCT_CLK(ssi_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2777
2778static struct clk ssi_ick_3430es1;
2779
2780static const char *ssi_ick_3430es1_parent_names[] = {
2781 "ssi_l4_ick",
2782};
2783
2784static struct clk_hw_omap ssi_ick_3430es1_hw = {
2785 .hw = {
2786 .clk = &ssi_ick_3430es1,
2787 },
2788 .ops = &clkhwops_iclk,
2789 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2790 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2791 .clkdm_name = "core_l4_clkdm",
2792};
2793
2794DEFINE_STRUCT_CLK(ssi_ick_3430es1, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2795
2796static struct clk ssi_ick_3430es2;
2797
2798static struct clk_hw_omap ssi_ick_3430es2_hw = {
2799 .hw = {
2800 .clk = &ssi_ick_3430es2,
2801 },
2802 .ops = &clkhwops_omap3430es2_iclk_ssi_wait,
2803 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2804 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2805 .clkdm_name = "core_l4_clkdm",
2806};
2807
2808DEFINE_STRUCT_CLK(ssi_ick_3430es2, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2809
2810static const struct clksel_rate ssi_ssr_corex2_rates[] = {
2811 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2812 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2813 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2814 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2815 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2816 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
2817 { .div = 0 }
2818};
2819
2820static const struct clksel ssi_ssr_clksel[] = {
2821 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
2822 { .parent = NULL },
2823};
2824
2825static const char *ssi_ssr_fck_3430es1_parent_names[] = {
2826 "corex2_fck",
2827};
2828
2829static const struct clk_ops ssi_ssr_fck_3430es1_ops = {
2830 .init = &omap2_init_clk_clkdm,
2831 .enable = &omap2_dflt_clk_enable,
2832 .disable = &omap2_dflt_clk_disable,
2833 .is_enabled = &omap2_dflt_clk_is_enabled,
2834 .recalc_rate = &omap2_clksel_recalc,
2835 .set_rate = &omap2_clksel_set_rate,
2836 .round_rate = &omap2_clksel_round_rate,
2837};
2838
2839DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es1, "core_l4_clkdm",
2840 ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2841 OMAP3430_CLKSEL_SSI_MASK,
2842 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2843 OMAP3430_EN_SSI_SHIFT,
2844 NULL, ssi_ssr_fck_3430es1_parent_names,
2845 ssi_ssr_fck_3430es1_ops);
2846
2847DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es2, "core_l4_clkdm",
2848 ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2849 OMAP3430_CLKSEL_SSI_MASK,
2850 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2851 OMAP3430_EN_SSI_SHIFT,
2852 NULL, ssi_ssr_fck_3430es1_parent_names,
2853 ssi_ssr_fck_3430es1_ops);
2854
2855DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1, "ssi_ssr_fck_3430es1",
2856 &ssi_ssr_fck_3430es1_core, 0x0, 1, 2);
2857
2858DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2, "ssi_ssr_fck_3430es2",
2859 &ssi_ssr_fck_3430es2_core, 0x0, 1, 2);
2860
2861static struct clk sys_clkout1;
2862
2863static const char *sys_clkout1_parent_names[] = {
2864 "osc_sys_ck",
2865};
2866
2867static struct clk_hw_omap sys_clkout1_hw = {
2868 .hw = {
2869 .clk = &sys_clkout1,
2870 },
2871 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
2872 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
2873};
2874
2875DEFINE_STRUCT_CLK(sys_clkout1, sys_clkout1_parent_names, aes1_ick_ops);
2876
2877DEFINE_CLK_DIVIDER(sys_clkout2, "clkout2_src_ck", &clkout2_src_ck_core, 0x0,
2878 OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_DIV_SHIFT,
2879 OMAP3430_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
2880
2881DEFINE_CLK_MUX(traceclk_src_fck, emu_src_ck_parent_names, NULL, 0x0,
2882 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2883 OMAP3430_TRACE_MUX_CTRL_SHIFT, OMAP3430_TRACE_MUX_CTRL_WIDTH,
2884 0x0, NULL);
2885
2886DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck_core,
2887 0x0,
2888 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2889 OMAP3430_CLKSEL_TRACECLK_SHIFT,
2890 OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
2891
2892static struct clk ts_fck;
2893
2894static struct clk_hw_omap ts_fck_hw = {
2895 .hw = {
2896 .clk = &ts_fck,
2897 },
2898 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
2899 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
2900 .clkdm_name = "core_l4_clkdm",
2901};
2902
2903DEFINE_STRUCT_CLK(ts_fck, wkup_32k_fck_parent_names, aes2_ick_ops);
2904
2905static struct clk uart1_fck;
2906
2907static struct clk_hw_omap uart1_fck_hw = {
2908 .hw = {
2909 .clk = &uart1_fck,
2910 },
2911 .ops = &clkhwops_wait,
2912 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2913 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2914 .clkdm_name = "core_l4_clkdm",
2915};
2916
2917DEFINE_STRUCT_CLK(uart1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2918
2919static struct clk uart1_ick;
2920
2921static struct clk_hw_omap uart1_ick_hw = {
2922 .hw = {
2923 .clk = &uart1_ick,
2924 },
2925 .ops = &clkhwops_iclk_wait,
2926 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2927 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2928 .clkdm_name = "core_l4_clkdm",
2929};
2930
2931DEFINE_STRUCT_CLK(uart1_ick, aes2_ick_parent_names, aes2_ick_ops);
2932
2933static struct clk uart2_fck;
2934
2935static struct clk_hw_omap uart2_fck_hw = {
2936 .hw = {
2937 .clk = &uart2_fck,
2938 },
2939 .ops = &clkhwops_wait,
2940 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2941 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2942 .clkdm_name = "core_l4_clkdm",
2943};
2944
2945DEFINE_STRUCT_CLK(uart2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2946
2947static struct clk uart2_ick;
2948
2949static struct clk_hw_omap uart2_ick_hw = {
2950 .hw = {
2951 .clk = &uart2_ick,
2952 },
2953 .ops = &clkhwops_iclk_wait,
2954 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2955 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2956 .clkdm_name = "core_l4_clkdm",
2957};
2958
2959DEFINE_STRUCT_CLK(uart2_ick, aes2_ick_parent_names, aes2_ick_ops);
2960
2961static struct clk uart3_fck;
2962
2963static const char *uart3_fck_parent_names[] = {
2964 "per_48m_fck",
2965};
2966
2967static struct clk_hw_omap uart3_fck_hw = {
2968 .hw = {
2969 .clk = &uart3_fck,
2970 },
2971 .ops = &clkhwops_wait,
2972 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2973 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2974 .clkdm_name = "per_clkdm",
2975};
2976
2977DEFINE_STRUCT_CLK(uart3_fck, uart3_fck_parent_names, aes2_ick_ops);
2978
2979static struct clk uart3_ick;
2980
2981static struct clk_hw_omap uart3_ick_hw = {
2982 .hw = {
2983 .clk = &uart3_ick,
2984 },
2985 .ops = &clkhwops_iclk_wait,
2986 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2987 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2988 .clkdm_name = "per_clkdm",
2989};
2990
2991DEFINE_STRUCT_CLK(uart3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2992
2993static struct clk uart4_fck;
2994
2995static struct clk_hw_omap uart4_fck_hw = {
2996 .hw = {
2997 .clk = &uart4_fck,
2998 },
2999 .ops = &clkhwops_wait,
3000 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
3001 .enable_bit = OMAP3630_EN_UART4_SHIFT,
3002 .clkdm_name = "per_clkdm",
3003};
3004
3005DEFINE_STRUCT_CLK(uart4_fck, uart3_fck_parent_names, aes2_ick_ops);
3006
3007static struct clk uart4_fck_am35xx;
3008
3009static struct clk_hw_omap uart4_fck_am35xx_hw = {
3010 .hw = {
3011 .clk = &uart4_fck_am35xx,
3012 },
3013 .ops = &clkhwops_wait,
3014 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
3015 .enable_bit = AM35XX_EN_UART4_SHIFT,
3016 .clkdm_name = "core_l4_clkdm",
3017};
3018
3019DEFINE_STRUCT_CLK(uart4_fck_am35xx, fshostusb_fck_parent_names, aes2_ick_ops);
3020
3021static struct clk uart4_ick;
3022
3023static struct clk_hw_omap uart4_ick_hw = {
3024 .hw = {
3025 .clk = &uart4_ick,
3026 },
3027 .ops = &clkhwops_iclk_wait,
3028 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
3029 .enable_bit = OMAP3630_EN_UART4_SHIFT,
3030 .clkdm_name = "per_clkdm",
3031};
3032
3033DEFINE_STRUCT_CLK(uart4_ick, gpio2_ick_parent_names, aes2_ick_ops);
3034
3035static struct clk uart4_ick_am35xx;
3036
3037static struct clk_hw_omap uart4_ick_am35xx_hw = {
3038 .hw = {
3039 .clk = &uart4_ick_am35xx,
3040 },
3041 .ops = &clkhwops_iclk_wait,
3042 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3043 .enable_bit = AM35XX_EN_UART4_SHIFT,
3044 .clkdm_name = "core_l4_clkdm",
3045};
3046
3047DEFINE_STRUCT_CLK(uart4_ick_am35xx, aes2_ick_parent_names, aes2_ick_ops);
3048
3049static const struct clksel_rate div2_rates[] = {
3050 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3051 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3052 { .div = 0 }
3053};
3054
3055static const struct clksel usb_l4_clksel[] = {
3056 { .parent = &l4_ick, .rates = div2_rates },
3057 { .parent = NULL },
3058};
3059
3060static const char *usb_l4_ick_parent_names[] = {
3061 "l4_ick",
3062};
3063
3064DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_clksel,
3065 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
3066 OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
3067 OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3068 OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
3069 &clkhwops_iclk_wait, usb_l4_ick_parent_names,
3070 ssi_ssr_fck_3430es1_ops);
3071
3072static struct clk usbhost_120m_fck;
3073
3074static const char *usbhost_120m_fck_parent_names[] = {
3075 "dpll5_m2_ck",
3076};
3077
3078static struct clk_hw_omap usbhost_120m_fck_hw = {
3079 .hw = {
3080 .clk = &usbhost_120m_fck,
3081 },
3082 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
3083 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
3084 .clkdm_name = "usbhost_clkdm",
3085};
3086
3087DEFINE_STRUCT_CLK(usbhost_120m_fck, usbhost_120m_fck_parent_names,
3088 aes2_ick_ops);
3089
3090static struct clk usbhost_48m_fck;
3091
3092static struct clk_hw_omap usbhost_48m_fck_hw = {
3093 .hw = {
3094 .clk = &usbhost_48m_fck,
3095 },
3096 .ops = &clkhwops_omap3430es2_dss_usbhost_wait,
3097 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
3098 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
3099 .clkdm_name = "usbhost_clkdm",
3100};
3101
3102DEFINE_STRUCT_CLK(usbhost_48m_fck, core_48m_fck_parent_names, aes2_ick_ops);
3103
3104static struct clk usbhost_ick;
3105
3106static struct clk_hw_omap usbhost_ick_hw = {
3107 .hw = {
3108 .clk = &usbhost_ick,
3109 },
3110 .ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
3111 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
3112 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
3113 .clkdm_name = "usbhost_clkdm",
3114};
3115
3116DEFINE_STRUCT_CLK(usbhost_ick, security_l4_ick2_parent_names, aes2_ick_ops);
3117
3118static struct clk usbtll_fck;
3119
3120static struct clk_hw_omap usbtll_fck_hw = {
3121 .hw = {
3122 .clk = &usbtll_fck,
3123 },
3124 .ops = &clkhwops_wait,
3125 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
3126 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3127 .clkdm_name = "core_l4_clkdm",
3128};
3129
3130DEFINE_STRUCT_CLK(usbtll_fck, usbhost_120m_fck_parent_names, aes2_ick_ops);
3131
3132static struct clk usbtll_ick;
3133
3134static struct clk_hw_omap usbtll_ick_hw = {
3135 .hw = {
3136 .clk = &usbtll_ick,
3137 },
3138 .ops = &clkhwops_iclk_wait,
3139 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
3140 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3141 .clkdm_name = "core_l4_clkdm",
3142};
3143
3144DEFINE_STRUCT_CLK(usbtll_ick, aes2_ick_parent_names, aes2_ick_ops);
3145
3146static const struct clksel_rate usim_96m_rates[] = {
3147 { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
3148 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3149 { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
3150 { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
3151 { .div = 0 }
3152};
3153
3154static const struct clksel_rate usim_120m_rates[] = {
3155 { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
3156 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
3157 { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
3158 { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
3159 { .div = 0 }
3160};
3161
3162static const struct clksel usim_clksel[] = {
3163 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
3164 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
3165 { .parent = &sys_ck, .rates = div2_rates },
3166 { .parent = NULL },
3167};
3168
3169static const char *usim_fck_parent_names[] = {
3170 "omap_96m_fck", "dpll5_m2_ck", "sys_ck",
3171};
3172
3173static struct clk usim_fck;
3174
3175static const struct clk_ops usim_fck_ops = {
3176 .enable = &omap2_dflt_clk_enable,
3177 .disable = &omap2_dflt_clk_disable,
3178 .is_enabled = &omap2_dflt_clk_is_enabled,
3179 .recalc_rate = &omap2_clksel_recalc,
3180 .get_parent = &omap2_clksel_find_parent_index,
3181 .set_parent = &omap2_clksel_set_parent,
3182};
3183
3184DEFINE_CLK_OMAP_MUX_GATE(usim_fck, NULL, usim_clksel,
3185 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
3186 OMAP3430ES2_CLKSEL_USIMOCP_MASK,
3187 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3188 OMAP3430ES2_EN_USIMOCP_SHIFT, &clkhwops_wait,
3189 usim_fck_parent_names, usim_fck_ops);
3190
3191static struct clk usim_ick;
3192
3193static struct clk_hw_omap usim_ick_hw = {
3194 .hw = {
3195 .clk = &usim_ick,
3196 },
3197 .ops = &clkhwops_iclk_wait,
3198 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3199 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
3200 .clkdm_name = "wkup_clkdm",
3201};
3202
3203DEFINE_STRUCT_CLK(usim_ick, gpio1_ick_parent_names, aes2_ick_ops);
3204
3205static struct clk vpfe_fck;
3206
3207static const char *vpfe_fck_parent_names[] = {
3208 "pclk_ck",
3209};
3210
3211static struct clk_hw_omap vpfe_fck_hw = {
3212 .hw = {
3213 .clk = &vpfe_fck,
3214 },
3215 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3216 .enable_bit = AM35XX_VPFE_FCLK_SHIFT,
3217};
3218
3219DEFINE_STRUCT_CLK(vpfe_fck, vpfe_fck_parent_names, aes1_ick_ops);
3220
3221static struct clk vpfe_ick;
3222
3223static struct clk_hw_omap vpfe_ick_hw = {
3224 .hw = {
3225 .clk = &vpfe_ick,
3226 },
3227 .ops = &clkhwops_am35xx_ipss_module_wait,
3228 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3229 .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3230 .clkdm_name = "core_l3_clkdm",
3231};
3232
3233DEFINE_STRUCT_CLK(vpfe_ick, emac_ick_parent_names, aes2_ick_ops);
3234
3235static struct clk wdt1_fck;
3236
3237DEFINE_STRUCT_CLK_HW_OMAP(wdt1_fck, "wkup_clkdm");
3238DEFINE_STRUCT_CLK(wdt1_fck, gpt12_fck_parent_names, core_l4_ick_ops);
3239
3240static struct clk wdt1_ick;
3241
3242static struct clk_hw_omap wdt1_ick_hw = {
3243 .hw = {
3244 .clk = &wdt1_ick,
3245 },
3246 .ops = &clkhwops_iclk_wait,
3247 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3248 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
3249 .clkdm_name = "wkup_clkdm",
3250};
3251
3252DEFINE_STRUCT_CLK(wdt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
3253
3254static struct clk wdt2_fck;
3255
3256static struct clk_hw_omap wdt2_fck_hw = {
3257 .hw = {
3258 .clk = &wdt2_fck,
3259 },
3260 .ops = &clkhwops_wait,
3261 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3262 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
3263 .clkdm_name = "wkup_clkdm",
3264};
3265
3266DEFINE_STRUCT_CLK(wdt2_fck, gpio1_dbck_parent_names, aes2_ick_ops);
3267
3268static struct clk wdt2_ick;
3269
3270static struct clk_hw_omap wdt2_ick_hw = {
3271 .hw = {
3272 .clk = &wdt2_ick,
3273 },
3274 .ops = &clkhwops_iclk_wait,
3275 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3276 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
3277 .clkdm_name = "wkup_clkdm",
3278};
3279
3280DEFINE_STRUCT_CLK(wdt2_ick, gpio1_ick_parent_names, aes2_ick_ops);
3281
3282static struct clk wdt3_fck;
3283
3284static struct clk_hw_omap wdt3_fck_hw = {
3285 .hw = {
3286 .clk = &wdt3_fck,
3287 },
3288 .ops = &clkhwops_wait,
3289 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
3290 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
3291 .clkdm_name = "per_clkdm",
3292};
3293
3294DEFINE_STRUCT_CLK(wdt3_fck, gpio2_dbck_parent_names, aes2_ick_ops);
3295
3296static struct clk wdt3_ick;
3297
3298static struct clk_hw_omap wdt3_ick_hw = {
3299 .hw = {
3300 .clk = &wdt3_ick,
3301 },
3302 .ops = &clkhwops_iclk_wait,
3303 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
3304 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
3305 .clkdm_name = "per_clkdm",
3306};
3307
3308DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
3309
3310/*
3311 * clocks specific to omap3430es1
3312 */
3313static struct omap_clk omap3430es1_clks[] = {
3314 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck),
3315 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck),
3316 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick),
3317 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck),
3318 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck),
3319 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck),
3320 CLK(NULL, "fshostusb_fck", &fshostusb_fck),
3321 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1),
3322 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1),
3323 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1),
3324 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1),
3325 CLK(NULL, "fac_ick", &fac_ick),
3326 CLK(NULL, "ssi_ick", &ssi_ick_3430es1),
3327 CLK(NULL, "usb_l4_ick", &usb_l4_ick),
3328 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1),
3329 CLK("omapdss_dss", "ick", &dss_ick_3430es1),
3330 CLK(NULL, "dss_ick", &dss_ick_3430es1),
3331};
3332
3333/*
3334 * clocks specific to am35xx
3335 */
3336static struct omap_clk am35xx_clks[] = {
3337 CLK(NULL, "ipss_ick", &ipss_ick),
3338 CLK(NULL, "rmii_ck", &rmii_ck),
3339 CLK(NULL, "pclk_ck", &pclk_ck),
3340 CLK(NULL, "emac_ick", &emac_ick),
3341 CLK(NULL, "emac_fck", &emac_fck),
3342 CLK("davinci_emac.0", NULL, &emac_ick),
3343 CLK("davinci_mdio.0", NULL, &emac_fck),
3344 CLK("vpfe-capture", "master", &vpfe_ick),
3345 CLK("vpfe-capture", "slave", &vpfe_fck),
3346 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx),
3347 CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx),
3348 CLK(NULL, "hecc_ck", &hecc_ck),
3349 CLK(NULL, "uart4_ick", &uart4_ick_am35xx),
3350 CLK(NULL, "uart4_fck", &uart4_fck_am35xx),
3351};
3352
3353/*
3354 * clocks specific to omap36xx
3355 */
3356static struct omap_clk omap36xx_clks[] = {
3357 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck),
3358 CLK(NULL, "uart4_fck", &uart4_fck),
3359};
3360
3361/*
3362 * clocks common to omap36xx omap34xx
3363 */
3364static struct omap_clk omap34xx_omap36xx_clks[] = {
3365 CLK(NULL, "aes1_ick", &aes1_ick),
3366 CLK("omap_rng", "ick", &rng_ick),
3367 CLK("omap3-rom-rng", "ick", &rng_ick),
3368 CLK(NULL, "sha11_ick", &sha11_ick),
3369 CLK(NULL, "des1_ick", &des1_ick),
3370 CLK(NULL, "cam_mclk", &cam_mclk),
3371 CLK(NULL, "cam_ick", &cam_ick),
3372 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck),
3373 CLK(NULL, "security_l3_ick", &security_l3_ick),
3374 CLK(NULL, "pka_ick", &pka_ick),
3375 CLK(NULL, "icr_ick", &icr_ick),
3376 CLK("omap-aes", "ick", &aes2_ick),
3377 CLK("omap-sham", "ick", &sha12_ick),
3378 CLK(NULL, "des2_ick", &des2_ick),
3379 CLK(NULL, "mspro_ick", &mspro_ick),
3380 CLK(NULL, "mailboxes_ick", &mailboxes_ick),
3381 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
3382 CLK(NULL, "sr1_fck", &sr1_fck),
3383 CLK(NULL, "sr2_fck", &sr2_fck),
3384 CLK(NULL, "sr_l4_ick", &sr_l4_ick),
3385 CLK(NULL, "security_l4_ick2", &security_l4_ick2),
3386 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick),
3387 CLK(NULL, "dpll2_fck", &dpll2_fck),
3388 CLK(NULL, "iva2_ck", &iva2_ck),
3389 CLK(NULL, "modem_fck", &modem_fck),
3390 CLK(NULL, "sad2d_ick", &sad2d_ick),
3391 CLK(NULL, "mad2d_ick", &mad2d_ick),
3392 CLK(NULL, "mspro_fck", &mspro_fck),
3393 CLK(NULL, "dpll2_ck", &dpll2_ck),
3394 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck),
3395};
3396
3397/*
3398 * clocks common to omap36xx and omap3430es2plus
3399 */
3400static struct omap_clk omap36xx_omap3430es2plus_clks[] = {
3401 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2),
3402 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2),
3403 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2),
3404 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2),
3405 CLK(NULL, "ssi_ick", &ssi_ick_3430es2),
3406 CLK(NULL, "usim_fck", &usim_fck),
3407 CLK(NULL, "usim_ick", &usim_ick),
3408};
3409
3410/*
3411 * clocks common to am35xx omap36xx and omap3430es2plus
3412 */
3413static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
3414 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck),
3415 CLK(NULL, "dpll5_ck", &dpll5_ck),
3416 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck),
3417 CLK(NULL, "sgx_fck", &sgx_fck),
3418 CLK(NULL, "sgx_ick", &sgx_ick),
3419 CLK(NULL, "cpefuse_fck", &cpefuse_fck),
3420 CLK(NULL, "ts_fck", &ts_fck),
3421 CLK(NULL, "usbtll_fck", &usbtll_fck),
3422 CLK(NULL, "usbtll_ick", &usbtll_ick),
3423 CLK("omap_hsmmc.2", "ick", &mmchs3_ick),
3424 CLK(NULL, "mmchs3_ick", &mmchs3_ick),
3425 CLK(NULL, "mmchs3_fck", &mmchs3_fck),
3426 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2),
3427 CLK("omapdss_dss", "ick", &dss_ick_3430es2),
3428 CLK(NULL, "dss_ick", &dss_ick_3430es2),
3429 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck),
3430 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck),
3431 CLK(NULL, "usbhost_ick", &usbhost_ick),
3432};
3433
3434/*
3435 * common clocks
3436 */
3437static struct omap_clk omap3xxx_clks[] = {
3438 CLK(NULL, "apb_pclk", &dummy_apb_pclk),
3439 CLK(NULL, "omap_32k_fck", &omap_32k_fck),
3440 CLK(NULL, "virt_12m_ck", &virt_12m_ck),
3441 CLK(NULL, "virt_13m_ck", &virt_13m_ck),
3442 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
3443 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
3444 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck),
3445 CLK(NULL, "osc_sys_ck", &osc_sys_ck),
3446 CLK("twl", "fck", &osc_sys_ck),
3447 CLK(NULL, "sys_ck", &sys_ck),
3448 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck),
3449 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck),
3450 CLK(NULL, "sys_altclk", &sys_altclk),
3451 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
3452 CLK(NULL, "sys_clkout1", &sys_clkout1),
3453 CLK(NULL, "dpll1_ck", &dpll1_ck),
3454 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck),
3455 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck),
3456 CLK(NULL, "dpll3_ck", &dpll3_ck),
3457 CLK(NULL, "core_ck", &core_ck),
3458 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck),
3459 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck),
3460 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck),
3461 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck),
3462 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck),
3463 CLK(NULL, "dpll4_ck", &dpll4_ck),
3464 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck),
3465 CLK(NULL, "omap_96m_fck", &omap_96m_fck),
3466 CLK(NULL, "cm_96m_fck", &cm_96m_fck),
3467 CLK(NULL, "omap_54m_fck", &omap_54m_fck),
3468 CLK(NULL, "omap_48m_fck", &omap_48m_fck),
3469 CLK(NULL, "omap_12m_fck", &omap_12m_fck),
3470 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck),
3471 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck),
3472 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck),
3473 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck),
3474 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck),
3475 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck),
3476 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck),
3477 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck),
3478 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck),
3479 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck),
3480 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck),
3481 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck),
3482 CLK(NULL, "sys_clkout2", &sys_clkout2),
3483 CLK(NULL, "corex2_fck", &corex2_fck),
3484 CLK(NULL, "dpll1_fck", &dpll1_fck),
3485 CLK(NULL, "mpu_ck", &mpu_ck),
3486 CLK(NULL, "arm_fck", &arm_fck),
3487 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck),
3488 CLK(NULL, "l3_ick", &l3_ick),
3489 CLK(NULL, "l4_ick", &l4_ick),
3490 CLK(NULL, "rm_ick", &rm_ick),
3491 CLK(NULL, "gpt10_fck", &gpt10_fck),
3492 CLK(NULL, "gpt11_fck", &gpt11_fck),
3493 CLK(NULL, "core_96m_fck", &core_96m_fck),
3494 CLK(NULL, "mmchs2_fck", &mmchs2_fck),
3495 CLK(NULL, "mmchs1_fck", &mmchs1_fck),
3496 CLK(NULL, "i2c3_fck", &i2c3_fck),
3497 CLK(NULL, "i2c2_fck", &i2c2_fck),
3498 CLK(NULL, "i2c1_fck", &i2c1_fck),
3499 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
3500 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
3501 CLK(NULL, "core_48m_fck", &core_48m_fck),
3502 CLK(NULL, "mcspi4_fck", &mcspi4_fck),
3503 CLK(NULL, "mcspi3_fck", &mcspi3_fck),
3504 CLK(NULL, "mcspi2_fck", &mcspi2_fck),
3505 CLK(NULL, "mcspi1_fck", &mcspi1_fck),
3506 CLK(NULL, "uart2_fck", &uart2_fck),
3507 CLK(NULL, "uart1_fck", &uart1_fck),
3508 CLK(NULL, "core_12m_fck", &core_12m_fck),
3509 CLK("omap_hdq.0", "fck", &hdq_fck),
3510 CLK(NULL, "hdq_fck", &hdq_fck),
3511 CLK(NULL, "core_l3_ick", &core_l3_ick),
3512 CLK(NULL, "sdrc_ick", &sdrc_ick),
3513 CLK(NULL, "gpmc_fck", &gpmc_fck),
3514 CLK(NULL, "core_l4_ick", &core_l4_ick),
3515 CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
3516 CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
3517 CLK(NULL, "mmchs2_ick", &mmchs2_ick),
3518 CLK(NULL, "mmchs1_ick", &mmchs1_ick),
3519 CLK("omap_hdq.0", "ick", &hdq_ick),
3520 CLK(NULL, "hdq_ick", &hdq_ick),
3521 CLK("omap2_mcspi.4", "ick", &mcspi4_ick),
3522 CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
3523 CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
3524 CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
3525 CLK(NULL, "mcspi4_ick", &mcspi4_ick),
3526 CLK(NULL, "mcspi3_ick", &mcspi3_ick),
3527 CLK(NULL, "mcspi2_ick", &mcspi2_ick),
3528 CLK(NULL, "mcspi1_ick", &mcspi1_ick),
3529 CLK("omap_i2c.3", "ick", &i2c3_ick),
3530 CLK("omap_i2c.2", "ick", &i2c2_ick),
3531 CLK("omap_i2c.1", "ick", &i2c1_ick),
3532 CLK(NULL, "i2c3_ick", &i2c3_ick),
3533 CLK(NULL, "i2c2_ick", &i2c2_ick),
3534 CLK(NULL, "i2c1_ick", &i2c1_ick),
3535 CLK(NULL, "uart2_ick", &uart2_ick),
3536 CLK(NULL, "uart1_ick", &uart1_ick),
3537 CLK(NULL, "gpt11_ick", &gpt11_ick),
3538 CLK(NULL, "gpt10_ick", &gpt10_ick),
3539 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
3540 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
3541 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
3542 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
3543 CLK(NULL, "omapctrl_ick", &omapctrl_ick),
3544 CLK(NULL, "dss_tv_fck", &dss_tv_fck),
3545 CLK(NULL, "dss_96m_fck", &dss_96m_fck),
3546 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck),
3547 CLK(NULL, "init_60m_fclk", &dummy_ck),
3548 CLK(NULL, "gpt1_fck", &gpt1_fck),
3549 CLK(NULL, "aes2_ick", &aes2_ick),
3550 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck),
3551 CLK(NULL, "gpio1_dbck", &gpio1_dbck),
3552 CLK(NULL, "sha12_ick", &sha12_ick),
3553 CLK(NULL, "wdt2_fck", &wdt2_fck),
3554 CLK("omap_wdt", "ick", &wdt2_ick),
3555 CLK(NULL, "wdt2_ick", &wdt2_ick),
3556 CLK(NULL, "wdt1_ick", &wdt1_ick),
3557 CLK(NULL, "gpio1_ick", &gpio1_ick),
3558 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick),
3559 CLK(NULL, "gpt12_ick", &gpt12_ick),
3560 CLK(NULL, "gpt1_ick", &gpt1_ick),
3561 CLK(NULL, "per_96m_fck", &per_96m_fck),
3562 CLK(NULL, "per_48m_fck", &per_48m_fck),
3563 CLK(NULL, "uart3_fck", &uart3_fck),
3564 CLK(NULL, "gpt2_fck", &gpt2_fck),
3565 CLK(NULL, "gpt3_fck", &gpt3_fck),
3566 CLK(NULL, "gpt4_fck", &gpt4_fck),
3567 CLK(NULL, "gpt5_fck", &gpt5_fck),
3568 CLK(NULL, "gpt6_fck", &gpt6_fck),
3569 CLK(NULL, "gpt7_fck", &gpt7_fck),
3570 CLK(NULL, "gpt8_fck", &gpt8_fck),
3571 CLK(NULL, "gpt9_fck", &gpt9_fck),
3572 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck),
3573 CLK(NULL, "gpio6_dbck", &gpio6_dbck),
3574 CLK(NULL, "gpio5_dbck", &gpio5_dbck),
3575 CLK(NULL, "gpio4_dbck", &gpio4_dbck),
3576 CLK(NULL, "gpio3_dbck", &gpio3_dbck),
3577 CLK(NULL, "gpio2_dbck", &gpio2_dbck),
3578 CLK(NULL, "wdt3_fck", &wdt3_fck),
3579 CLK(NULL, "per_l4_ick", &per_l4_ick),
3580 CLK(NULL, "gpio6_ick", &gpio6_ick),
3581 CLK(NULL, "gpio5_ick", &gpio5_ick),
3582 CLK(NULL, "gpio4_ick", &gpio4_ick),
3583 CLK(NULL, "gpio3_ick", &gpio3_ick),
3584 CLK(NULL, "gpio2_ick", &gpio2_ick),
3585 CLK(NULL, "wdt3_ick", &wdt3_ick),
3586 CLK(NULL, "uart3_ick", &uart3_ick),
3587 CLK(NULL, "uart4_ick", &uart4_ick),
3588 CLK(NULL, "gpt9_ick", &gpt9_ick),
3589 CLK(NULL, "gpt8_ick", &gpt8_ick),
3590 CLK(NULL, "gpt7_ick", &gpt7_ick),
3591 CLK(NULL, "gpt6_ick", &gpt6_ick),
3592 CLK(NULL, "gpt5_ick", &gpt5_ick),
3593 CLK(NULL, "gpt4_ick", &gpt4_ick),
3594 CLK(NULL, "gpt3_ick", &gpt3_ick),
3595 CLK(NULL, "gpt2_ick", &gpt2_ick),
3596 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
3597 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
3598 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
3599 CLK(NULL, "mcbsp4_ick", &mcbsp2_ick),
3600 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
3601 CLK(NULL, "mcbsp2_ick", &mcbsp4_ick),
3602 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
3603 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
3604 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
3605 CLK("etb", "emu_src_ck", &emu_src_ck),
3606 CLK(NULL, "emu_src_ck", &emu_src_ck),
3607 CLK(NULL, "pclk_fck", &pclk_fck),
3608 CLK(NULL, "pclkx2_fck", &pclkx2_fck),
3609 CLK(NULL, "atclk_fck", &atclk_fck),
3610 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck),
3611 CLK(NULL, "traceclk_fck", &traceclk_fck),
3612 CLK(NULL, "secure_32k_fck", &secure_32k_fck),
3613 CLK(NULL, "gpt12_fck", &gpt12_fck),
3614 CLK(NULL, "wdt1_fck", &wdt1_fck),
3615 CLK(NULL, "timer_32k_ck", &omap_32k_fck),
3616 CLK(NULL, "timer_sys_ck", &sys_ck),
3617 CLK(NULL, "cpufreq_ck", &dpll1_ck),
3618};
3619
3620static const char *enable_init_clks[] = {
3621 "sdrc_ick",
3622 "gpmc_fck",
3623 "omapctrl_ick",
3624};
3625
3626int __init omap3xxx_clk_init(void)
3627{
3628 if (omap3_has_192mhz_clk())
3629 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3630
3631 if (cpu_is_omap3630()) {
3632 dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
3633 dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
3634 dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
3635 dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
3636 dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
3637 dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
3638 }
3639
3640 /*
3641 * XXX This type of dynamic rewriting of the clock tree is
3642 * deprecated and should be revised soon.
3643 */
3644 if (cpu_is_omap3630())
3645 dpll4_dd = dpll4_dd_3630;
3646 else
3647 dpll4_dd = dpll4_dd_34xx;
3648
3649
3650 /*
3651 * 3505 must be tested before 3517, since 3517 returns true
3652 * for both AM3517 chips and AM3517 family chips, which
3653 * includes 3505. Unfortunately there's no obvious family
3654 * test for 3517/3505 :-(
3655 */
3656 if (soc_is_am35xx()) {
3657 cpu_mask = RATE_IN_34XX;
3658 omap_clocks_register(am35xx_clks, ARRAY_SIZE(am35xx_clks));
3659 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3660 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3661 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
3662 } else if (cpu_is_omap3630()) {
3663 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3664 omap_clocks_register(omap36xx_clks, ARRAY_SIZE(omap36xx_clks));
3665 omap_clocks_register(omap36xx_omap3430es2plus_clks,
3666 ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
3667 omap_clocks_register(omap34xx_omap36xx_clks,
3668 ARRAY_SIZE(omap34xx_omap36xx_clks));
3669 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3670 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3671 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
3672 } else if (soc_is_am33xx()) {
3673 cpu_mask = RATE_IN_AM33XX;
3674 } else if (cpu_is_ti814x()) {
3675 cpu_mask = RATE_IN_TI814X;
3676 } else if (cpu_is_omap34xx()) {
3677 if (omap_rev() == OMAP3430_REV_ES1_0) {
3678 cpu_mask = RATE_IN_3430ES1;
3679 omap_clocks_register(omap3430es1_clks,
3680 ARRAY_SIZE(omap3430es1_clks));
3681 omap_clocks_register(omap34xx_omap36xx_clks,
3682 ARRAY_SIZE(omap34xx_omap36xx_clks));
3683 omap_clocks_register(omap3xxx_clks,
3684 ARRAY_SIZE(omap3xxx_clks));
3685 } else {
3686 /*
3687 * Assume that anything that we haven't matched yet
3688 * has 3430ES2-type clocks.
3689 */
3690 cpu_mask = RATE_IN_3430ES2PLUS;
3691 omap_clocks_register(omap34xx_omap36xx_clks,
3692 ARRAY_SIZE(omap34xx_omap36xx_clks));
3693 omap_clocks_register(omap36xx_omap3430es2plus_clks,
3694 ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
3695 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3696 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3697 omap_clocks_register(omap3xxx_clks,
3698 ARRAY_SIZE(omap3xxx_clks));
3699 }
3700 } else {
3701 WARN(1, "clock: could not identify OMAP3 variant\n");
3702 }
3703
3704 omap2_clk_disable_autoidle_all();
3705
3706 omap2_clk_enable_init_clocks(enable_init_clks,
3707 ARRAY_SIZE(enable_init_clks));
3708
3709 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3710 (clk_get_rate(&osc_sys_ck) / 1000000),
3711 (clk_get_rate(&osc_sys_ck) / 100000) % 10,
3712 (clk_get_rate(&core_ck) / 1000000),
3713 (clk_get_rate(&arm_fck) / 1000000));
3714
3715 /*
3716 * Lock DPLL5 -- here only until other device init code can
3717 * handle this
3718 */
3719 if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
3720 omap3_clk_lock_dpll5();
3721
3722 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3723 sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3724 arm_fck_p = clk_get(NULL, "arm_fck");
3725
3726 return 0;
3727}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index a1bd6affb508..25ea1b176e33 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -461,7 +461,17 @@ void __init omap3_init_early(void)
461 omap3xxx_clockdomains_init(); 461 omap3xxx_clockdomains_init();
462 omap3xxx_hwmod_init(); 462 omap3xxx_hwmod_init();
463 omap_hwmod_init_postsetup(); 463 omap_hwmod_init_postsetup();
464 omap_clk_soc_init = omap3xxx_clk_init; 464 if (!of_have_populated_dt()) {
465 omap3_prcm_legacy_iomaps_init();
466 if (soc_is_am35xx())
467 omap_clk_soc_init = am35xx_clk_legacy_init;
468 else if (cpu_is_omap3630())
469 omap_clk_soc_init = omap36xx_clk_legacy_init;
470 else if (omap_rev() == OMAP3430_REV_ES1_0)
471 omap_clk_soc_init = omap3430es1_clk_legacy_init;
472 else
473 omap_clk_soc_init = omap3430_clk_legacy_init;
474 }
465} 475}
466 476
467void __init omap3430_init_early(void) 477void __init omap3430_init_early(void)
@@ -509,8 +519,6 @@ void __init ti81xx_init_early(void)
509 omap_hwmod_init_postsetup(); 519 omap_hwmod_init_postsetup();
510 if (of_have_populated_dt()) 520 if (of_have_populated_dt())
511 omap_clk_soc_init = ti81xx_dt_clk_init; 521 omap_clk_soc_init = ti81xx_dt_clk_init;
512 else
513 omap_clk_soc_init = omap3xxx_clk_init;
514} 522}
515 523
516void __init omap3_init_late(void) 524void __init omap3_init_late(void)
@@ -731,15 +739,17 @@ int __init omap_clk_init(void)
731 739
732 ti_clk_init_features(); 740 ti_clk_init_features();
733 741
734 ret = of_prcm_init(); 742 if (of_have_populated_dt()) {
735 if (ret) 743 ret = of_prcm_init();
736 return ret; 744 if (ret)
745 return ret;
737 746
738 of_clk_init(NULL); 747 of_clk_init(NULL);
739 748
740 ti_dt_clk_init_retry_clks(); 749 ti_dt_clk_init_retry_clks();
741 750
742 ti_dt_clockdomains_setup(); 751 ti_dt_clockdomains_setup();
752 }
743 753
744 ret = omap_clk_soc_init(); 754 ret = omap_clk_soc_init();
745 755
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 77752e49d8d4..b9061a6a2db8 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -20,6 +20,7 @@ extern void __iomem *prm_base;
20extern u16 prm_features; 20extern u16 prm_features;
21extern void omap2_set_globals_prm(void __iomem *prm); 21extern void omap2_set_globals_prm(void __iomem *prm);
22int of_prcm_init(void); 22int of_prcm_init(void);
23void omap3_prcm_legacy_iomaps_init(void);
23# endif 24# endif
24 25
25/* 26/*
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 779940cb6e56..542dd9dbd035 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -35,6 +35,8 @@
35#include "prm44xx.h" 35#include "prm44xx.h"
36#include "common.h" 36#include "common.h"
37#include "clock.h" 37#include "clock.h"
38#include "cm.h"
39#include "control.h"
38 40
39/* 41/*
40 * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs 42 * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
@@ -627,6 +629,15 @@ int __init of_prcm_init(void)
627 return 0; 629 return 0;
628} 630}
629 631
632void __init omap3_prcm_legacy_iomaps_init(void)
633{
634 ti_clk_ll_ops = &omap_clk_ll_ops;
635
636 clk_memmaps[TI_CLKM_CM] = cm_base + OMAP3430_IVA2_MOD;
637 clk_memmaps[TI_CLKM_PRM] = prm_base + OMAP3430_IVA2_MOD;
638 clk_memmaps[TI_CLKM_SCRM] = omap_ctrl_base_get();
639}
640
630static int __init prm_late_init(void) 641static int __init prm_late_init(void)
631{ 642{
632 if (prm_ll_data->late_init) 643 if (prm_ll_data->late_init)
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-24 23:01:11 -0400