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-rw-r--r--arch/arm/mach-omap2/Makefile2
-rw-r--r--arch/arm/mach-omap2/cclock3xxx_data.c3727
-rw-r--r--arch/arm/mach-omap2/io.c28
-rw-r--r--arch/arm/mach-omap2/prm.h1
-rw-r--r--arch/arm/mach-omap2/prm_common.c11
-rw-r--r--drivers/clk/ti/Makefile3
-rw-r--r--drivers/clk/ti/clk-3xxx-legacy.c4653
-rw-r--r--drivers/clk/ti/clk.c125
-rw-r--r--drivers/clk/ti/clock.h172
-rw-r--r--drivers/clk/ti/composite.c46
-rw-r--r--drivers/clk/ti/divider.c132
-rw-r--r--drivers/clk/ti/dpll.c119
-rw-r--r--drivers/clk/ti/gate.c161
-rw-r--r--drivers/clk/ti/interface.c96
-rw-r--r--drivers/clk/ti/mux.c70
-rw-r--r--include/linux/clk/ti.h12
16 files changed, 5548 insertions, 3810 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 5d27dfdef66b..d2a6b271e85b 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -187,7 +187,7 @@ obj-$(CONFIG_SOC_OMAP2430) += clock2430.o
187obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o 187obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
188obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o 188obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
189obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o 189obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
190obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o 190obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o
191obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o 191obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
192obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) 192obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
193obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o 193obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
deleted file mode 100644
index adb4e6437204..000000000000
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ /dev/null
@@ -1,3727 +0,0 @@
1/*
2 * OMAP3 clock data
3 *
4 * Copyright (C) 2007-2012 Texas Instruments, Inc.
5 * Copyright (C) 2007-2011 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * Updated to COMMON clk data format by Rajendra Nayak <rnayak@ti.com>
9 * With many device clock fixes by Kevin Hilman and Jouni Högander
10 * DPLL bypass clock support added by Roman Tereshonkov
11 *
12 */
13
14/*
15 * Virtual clocks are introduced as convenient tools.
16 * They are sources for other clocks and not supposed
17 * to be requested from drivers directly.
18 */
19
20#include <linux/kernel.h>
21#include <linux/clk.h>
22#include <linux/clk-private.h>
23#include <linux/list.h>
24#include <linux/io.h>
25
26#include "soc.h"
27#include "iomap.h"
28#include "clock.h"
29#include "clock3xxx.h"
30#include "clock34xx.h"
31#include "clock36xx.h"
32#include "clock3517.h"
33#include "cm3xxx.h"
34#include "cm-regbits-34xx.h"
35#include "prm3xxx.h"
36#include "prm-regbits-34xx.h"
37#include "control.h"
38
39/*
40 * clocks
41 */
42
43#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
44
45/* Maximum DPLL multiplier, divider values for OMAP3 */
46#define OMAP3_MAX_DPLL_MULT 2047
47#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
48#define OMAP3_MAX_DPLL_DIV 128
49
50DEFINE_CLK_FIXED_RATE(dummy_apb_pclk, CLK_IS_ROOT, 0x0, 0x0);
51
52DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
53
54DEFINE_CLK_FIXED_RATE(omap_32k_fck, CLK_IS_ROOT, 32768, 0x0);
55
56DEFINE_CLK_FIXED_RATE(pclk_ck, CLK_IS_ROOT, 27000000, 0x0);
57
58DEFINE_CLK_FIXED_RATE(rmii_ck, CLK_IS_ROOT, 50000000, 0x0);
59
60DEFINE_CLK_FIXED_RATE(secure_32k_fck, CLK_IS_ROOT, 32768, 0x0);
61
62DEFINE_CLK_FIXED_RATE(sys_altclk, CLK_IS_ROOT, 0x0, 0x0);
63
64DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0);
65
66DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0);
67
68DEFINE_CLK_FIXED_RATE(virt_16_8m_ck, CLK_IS_ROOT, 16800000, 0x0);
69
70DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
71
72DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
73
74DEFINE_CLK_FIXED_RATE(virt_38_4m_ck, CLK_IS_ROOT, 38400000, 0x0);
75
76static const char *osc_sys_ck_parent_names[] = {
77 "virt_12m_ck", "virt_13m_ck", "virt_19200000_ck", "virt_26000000_ck",
78 "virt_38_4m_ck", "virt_16_8m_ck",
79};
80
81DEFINE_CLK_MUX(osc_sys_ck, osc_sys_ck_parent_names, NULL, 0x0,
82 OMAP3430_PRM_CLKSEL, OMAP3430_SYS_CLKIN_SEL_SHIFT,
83 OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0, NULL);
84
85DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck_core, 0x0,
86 OMAP3430_PRM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
87 OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
88
89static struct dpll_data dpll3_dd = {
90 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
91 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
92 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
93 .clk_bypass = &sys_ck,
94 .clk_ref = &sys_ck,
95 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
96 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
97 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
98 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
99 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
100 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
101 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
102 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
103 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
104 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
105 .max_multiplier = OMAP3_MAX_DPLL_MULT,
106 .min_divider = 1,
107 .max_divider = OMAP3_MAX_DPLL_DIV,
108};
109
110static struct clk dpll3_ck;
111
112static const char *dpll3_ck_parent_names[] = {
113 "sys_ck",
114 "sys_ck",
115};
116
117static const struct clk_ops dpll3_ck_ops = {
118 .init = &omap2_init_clk_clkdm,
119 .get_parent = &omap2_init_dpll_parent,
120 .recalc_rate = &omap3_dpll_recalc,
121 .round_rate = &omap2_dpll_round_rate,
122};
123
124static struct clk_hw_omap dpll3_ck_hw = {
125 .hw = {
126 .clk = &dpll3_ck,
127 },
128 .ops = &clkhwops_omap3_dpll,
129 .dpll_data = &dpll3_dd,
130 .clkdm_name = "dpll3_clkdm",
131};
132
133DEFINE_STRUCT_CLK(dpll3_ck, dpll3_ck_parent_names, dpll3_ck_ops);
134
135DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck_core, 0x0,
136 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
137 OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT,
138 OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH,
139 CLK_DIVIDER_ONE_BASED, NULL);
140
141static struct clk core_ck;
142
143static const char *core_ck_parent_names[] = {
144 "dpll3_m2_ck",
145};
146
147static const struct clk_ops core_ck_ops = {};
148
149DEFINE_STRUCT_CLK_HW_OMAP(core_ck, NULL);
150DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
151
152DEFINE_CLK_DIVIDER(l3_ick, "core_ck", &core_ck_core, 0x0,
153 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
154 OMAP3430_CLKSEL_L3_SHIFT, OMAP3430_CLKSEL_L3_WIDTH,
155 CLK_DIVIDER_ONE_BASED, NULL);
156
157DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick_core, 0x0,
158 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
159 OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH,
160 CLK_DIVIDER_ONE_BASED, NULL);
161
162static struct clk security_l4_ick2;
163
164static const char *security_l4_ick2_parent_names[] = {
165 "l4_ick",
166};
167
168DEFINE_STRUCT_CLK_HW_OMAP(security_l4_ick2, NULL);
169DEFINE_STRUCT_CLK(security_l4_ick2, security_l4_ick2_parent_names, core_ck_ops);
170
171static struct clk aes1_ick;
172
173static const char *aes1_ick_parent_names[] = {
174 "security_l4_ick2",
175};
176
177static const struct clk_ops aes1_ick_ops = {
178 .enable = &omap2_dflt_clk_enable,
179 .disable = &omap2_dflt_clk_disable,
180 .is_enabled = &omap2_dflt_clk_is_enabled,
181};
182
183static struct clk_hw_omap aes1_ick_hw = {
184 .hw = {
185 .clk = &aes1_ick,
186 },
187 .ops = &clkhwops_iclk_wait,
188 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
189 .enable_bit = OMAP3430_EN_AES1_SHIFT,
190};
191
192DEFINE_STRUCT_CLK(aes1_ick, aes1_ick_parent_names, aes1_ick_ops);
193
194static struct clk core_l4_ick;
195
196static const struct clk_ops core_l4_ick_ops = {
197 .init = &omap2_init_clk_clkdm,
198};
199
200DEFINE_STRUCT_CLK_HW_OMAP(core_l4_ick, "core_l4_clkdm");
201DEFINE_STRUCT_CLK(core_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
202
203static struct clk aes2_ick;
204
205static const char *aes2_ick_parent_names[] = {
206 "core_l4_ick",
207};
208
209static const struct clk_ops aes2_ick_ops = {
210 .init = &omap2_init_clk_clkdm,
211 .enable = &omap2_dflt_clk_enable,
212 .disable = &omap2_dflt_clk_disable,
213 .is_enabled = &omap2_dflt_clk_is_enabled,
214};
215
216static struct clk_hw_omap aes2_ick_hw = {
217 .hw = {
218 .clk = &aes2_ick,
219 },
220 .ops = &clkhwops_iclk_wait,
221 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
222 .enable_bit = OMAP3430_EN_AES2_SHIFT,
223 .clkdm_name = "core_l4_clkdm",
224};
225
226DEFINE_STRUCT_CLK(aes2_ick, aes2_ick_parent_names, aes2_ick_ops);
227
228static struct clk dpll1_fck;
229
230static struct dpll_data dpll1_dd = {
231 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
232 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
233 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
234 .clk_bypass = &dpll1_fck,
235 .clk_ref = &sys_ck,
236 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
237 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
238 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
239 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
240 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
241 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
242 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
243 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
244 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
245 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
246 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
247 .max_multiplier = OMAP3_MAX_DPLL_MULT,
248 .min_divider = 1,
249 .max_divider = OMAP3_MAX_DPLL_DIV,
250};
251
252static struct clk dpll1_ck;
253
254static const struct clk_ops dpll1_ck_ops = {
255 .init = &omap2_init_clk_clkdm,
256 .enable = &omap3_noncore_dpll_enable,
257 .disable = &omap3_noncore_dpll_disable,
258 .get_parent = &omap2_init_dpll_parent,
259 .recalc_rate = &omap3_dpll_recalc,
260 .set_rate = &omap3_noncore_dpll_set_rate,
261 .set_parent = &omap3_noncore_dpll_set_parent,
262 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
263 .determine_rate = &omap3_noncore_dpll_determine_rate,
264 .round_rate = &omap2_dpll_round_rate,
265};
266
267static struct clk_hw_omap dpll1_ck_hw = {
268 .hw = {
269 .clk = &dpll1_ck,
270 },
271 .ops = &clkhwops_omap3_dpll,
272 .dpll_data = &dpll1_dd,
273 .clkdm_name = "dpll1_clkdm",
274};
275
276DEFINE_STRUCT_CLK(dpll1_ck, dpll3_ck_parent_names, dpll1_ck_ops);
277
278DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck, "dpll1_ck", &dpll1_ck_core, 0x0, 2, 1);
279
280DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck_core, 0x0,
281 OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
282 OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT,
283 OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH,
284 CLK_DIVIDER_ONE_BASED, NULL);
285
286static struct clk mpu_ck;
287
288static const char *mpu_ck_parent_names[] = {
289 "dpll1_x2m2_ck",
290};
291
292DEFINE_STRUCT_CLK_HW_OMAP(mpu_ck, "mpu_clkdm");
293DEFINE_STRUCT_CLK(mpu_ck, mpu_ck_parent_names, core_l4_ick_ops);
294
295DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck_core, 0x0,
296 OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
297 OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH,
298 0x0, NULL);
299
300static struct clk cam_ick;
301
302static struct clk_hw_omap cam_ick_hw = {
303 .hw = {
304 .clk = &cam_ick,
305 },
306 .ops = &clkhwops_iclk,
307 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
308 .enable_bit = OMAP3430_EN_CAM_SHIFT,
309 .clkdm_name = "cam_clkdm",
310};
311
312DEFINE_STRUCT_CLK(cam_ick, security_l4_ick2_parent_names, aes2_ick_ops);
313
314/* DPLL4 */
315/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
316/* Type: DPLL */
317static struct dpll_data dpll4_dd;
318
319static struct dpll_data dpll4_dd_34xx __initdata = {
320 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
321 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
322 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
323 .clk_bypass = &sys_ck,
324 .clk_ref = &sys_ck,
325 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
326 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
327 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
328 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
329 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
330 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
331 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
332 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
333 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
334 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
335 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
336 .max_multiplier = OMAP3_MAX_DPLL_MULT,
337 .min_divider = 1,
338 .max_divider = OMAP3_MAX_DPLL_DIV,
339};
340
341static struct dpll_data dpll4_dd_3630 __initdata = {
342 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
343 .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
344 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
345 .clk_bypass = &sys_ck,
346 .clk_ref = &sys_ck,
347 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
348 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
349 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
350 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
351 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
352 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
353 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
354 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
355 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
356 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
357 .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
358 .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
359 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
360 .min_divider = 1,
361 .max_divider = OMAP3_MAX_DPLL_DIV,
362 .flags = DPLL_J_TYPE
363};
364
365static struct clk dpll4_ck;
366
367static const struct clk_ops dpll4_ck_ops = {
368 .init = &omap2_init_clk_clkdm,
369 .enable = &omap3_noncore_dpll_enable,
370 .disable = &omap3_noncore_dpll_disable,
371 .get_parent = &omap2_init_dpll_parent,
372 .recalc_rate = &omap3_dpll_recalc,
373 .set_rate = &omap3_dpll4_set_rate,
374 .set_parent = &omap3_noncore_dpll_set_parent,
375 .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent,
376 .determine_rate = &omap3_noncore_dpll_determine_rate,
377 .round_rate = &omap2_dpll_round_rate,
378};
379
380static struct clk_hw_omap dpll4_ck_hw = {
381 .hw = {
382 .clk = &dpll4_ck,
383 },
384 .dpll_data = &dpll4_dd,
385 .ops = &clkhwops_omap3_dpll,
386 .clkdm_name = "dpll4_clkdm",
387};
388
389DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops);
390
391static const struct clk_div_table dpll4_mx_ck_div_table[] = {
392 { .div = 1, .val = 1 },
393 { .div = 2, .val = 2 },
394 { .div = 3, .val = 3 },
395 { .div = 4, .val = 4 },
396 { .div = 5, .val = 5 },
397 { .div = 6, .val = 6 },
398 { .div = 7, .val = 7 },
399 { .div = 8, .val = 8 },
400 { .div = 9, .val = 9 },
401 { .div = 10, .val = 10 },
402 { .div = 11, .val = 11 },
403 { .div = 12, .val = 12 },
404 { .div = 13, .val = 13 },
405 { .div = 14, .val = 14 },
406 { .div = 15, .val = 15 },
407 { .div = 16, .val = 16 },
408 { .div = 17, .val = 17 },
409 { .div = 18, .val = 18 },
410 { .div = 19, .val = 19 },
411 { .div = 20, .val = 20 },
412 { .div = 21, .val = 21 },
413 { .div = 22, .val = 22 },
414 { .div = 23, .val = 23 },
415 { .div = 24, .val = 24 },
416 { .div = 25, .val = 25 },
417 { .div = 26, .val = 26 },
418 { .div = 27, .val = 27 },
419 { .div = 28, .val = 28 },
420 { .div = 29, .val = 29 },
421 { .div = 30, .val = 30 },
422 { .div = 31, .val = 31 },
423 { .div = 32, .val = 32 },
424 { .div = 0 },
425};
426
427DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck_core, 0x0,
428 OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
429 OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH,
430 CLK_DIVIDER_ONE_BASED, NULL);
431
432static struct clk dpll4_m5x2_ck;
433
434static const char *dpll4_m5x2_ck_parent_names[] = {
435 "dpll4_m5_ck",
436};
437
438static const struct clk_ops dpll4_m5x2_ck_ops = {
439 .init = &omap2_init_clk_clkdm,
440 .enable = &omap2_dflt_clk_enable,
441 .disable = &omap2_dflt_clk_disable,
442 .is_enabled = &omap2_dflt_clk_is_enabled,
443 .set_rate = &omap3_clkoutx2_set_rate,
444 .recalc_rate = &omap3_clkoutx2_recalc,
445 .round_rate = &omap3_clkoutx2_round_rate,
446};
447
448static const struct clk_ops dpll4_m5x2_ck_3630_ops = {
449 .init = &omap2_init_clk_clkdm,
450 .enable = &omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
451 .disable = &omap2_dflt_clk_disable,
452 .recalc_rate = &omap3_clkoutx2_recalc,
453};
454
455static struct clk_hw_omap dpll4_m5x2_ck_hw = {
456 .hw = {
457 .clk = &dpll4_m5x2_ck,
458 },
459 .ops = &clkhwops_wait,
460 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
461 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
462 .flags = INVERT_ENABLE,
463 .clkdm_name = "dpll4_clkdm",
464};
465
466DEFINE_STRUCT_CLK_FLAGS(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names,
467 dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
468
469static struct clk_core dpll4_m5x2_ck_3630_core = {
470 .name = "dpll4_m5x2_ck",
471 .hw = &dpll4_m5x2_ck_hw.hw,
472 .parent_names = dpll4_m5x2_ck_parent_names,
473 .num_parents = ARRAY_SIZE(dpll4_m5x2_ck_parent_names),
474 .ops = &dpll4_m5x2_ck_3630_ops,
475 .flags = CLK_SET_RATE_PARENT,
476};
477
478static struct clk dpll4_m5x2_ck_3630 = {
479 .core = &dpll4_m5x2_ck_3630_core,
480};
481
482static struct clk cam_mclk;
483
484static const char *cam_mclk_parent_names[] = {
485 "dpll4_m5x2_ck",
486};
487
488static struct clk_hw_omap cam_mclk_hw = {
489 .hw = {
490 .clk = &cam_mclk,
491 },
492 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
493 .enable_bit = OMAP3430_EN_CAM_SHIFT,
494 .clkdm_name = "cam_clkdm",
495};
496
497static struct clk_core cam_mclk_core = {
498 .name = "cam_mclk",
499 .hw = &cam_mclk_hw.hw,
500 .parent_names = cam_mclk_parent_names,
501 .num_parents = ARRAY_SIZE(cam_mclk_parent_names),
502 .ops = &aes2_ick_ops,
503 .flags = CLK_SET_RATE_PARENT,
504};
505
506static struct clk cam_mclk = {
507 .core = &cam_mclk_core,
508};
509
510static const struct clksel_rate clkout2_src_core_rates[] = {
511 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
512 { .div = 0 }
513};
514
515static const struct clksel_rate clkout2_src_sys_rates[] = {
516 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
517 { .div = 0 }
518};
519
520static const struct clksel_rate clkout2_src_96m_rates[] = {
521 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
522 { .div = 0 }
523};
524
525DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck_core, 0x0,
526 OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
527 OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH,
528 CLK_DIVIDER_ONE_BASED, NULL);
529
530static struct clk dpll4_m2x2_ck;
531
532static const char *dpll4_m2x2_ck_parent_names[] = {
533 "dpll4_m2_ck",
534};
535
536static struct clk_hw_omap dpll4_m2x2_ck_hw = {
537 .hw = {
538 .clk = &dpll4_m2x2_ck,
539 },
540 .ops = &clkhwops_wait,
541 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
542 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
543 .flags = INVERT_ENABLE,
544 .clkdm_name = "dpll4_clkdm",
545};
546
547DEFINE_STRUCT_CLK(dpll4_m2x2_ck, dpll4_m2x2_ck_parent_names, dpll4_m5x2_ck_ops);
548
549static struct clk_core dpll4_m2x2_ck_3630_core = {
550 .name = "dpll4_m2x2_ck",
551 .hw = &dpll4_m2x2_ck_hw.hw,
552 .parent_names = dpll4_m2x2_ck_parent_names,
553 .num_parents = ARRAY_SIZE(dpll4_m2x2_ck_parent_names),
554 .ops = &dpll4_m5x2_ck_3630_ops,
555};
556
557static struct clk dpll4_m2x2_ck_3630 = {
558 .core = &dpll4_m2x2_ck_3630_core,
559};
560
561static struct clk omap_96m_alwon_fck;
562
563static const char *omap_96m_alwon_fck_parent_names[] = {
564 "dpll4_m2x2_ck",
565};
566
567DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck, NULL);
568DEFINE_STRUCT_CLK(omap_96m_alwon_fck, omap_96m_alwon_fck_parent_names,
569 core_ck_ops);
570
571static struct clk cm_96m_fck;
572
573static const char *cm_96m_fck_parent_names[] = {
574 "omap_96m_alwon_fck",
575};
576
577DEFINE_STRUCT_CLK_HW_OMAP(cm_96m_fck, NULL);
578DEFINE_STRUCT_CLK(cm_96m_fck, cm_96m_fck_parent_names, core_ck_ops);
579
580static const struct clksel_rate clkout2_src_54m_rates[] = {
581 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
582 { .div = 0 }
583};
584
585DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck, "dpll4_ck", &dpll4_ck_core, 0x0,
586 OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
587 OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,
588 0, dpll4_mx_ck_div_table, NULL);
589
590static struct clk dpll4_m3x2_ck;
591
592static const char *dpll4_m3x2_ck_parent_names[] = {
593 "dpll4_m3_ck",
594};
595
596static struct clk_hw_omap dpll4_m3x2_ck_hw = {
597 .hw = {
598 .clk = &dpll4_m3x2_ck,
599 },
600 .ops = &clkhwops_wait,
601 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
602 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
603 .flags = INVERT_ENABLE,
604 .clkdm_name = "dpll4_clkdm",
605};
606
607DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
608
609static struct clk_core dpll4_m3x2_ck_3630_core = {
610 .name = "dpll4_m3x2_ck",
611 .hw = &dpll4_m3x2_ck_hw.hw,
612 .parent_names = dpll4_m3x2_ck_parent_names,
613 .num_parents = ARRAY_SIZE(dpll4_m3x2_ck_parent_names),
614 .ops = &dpll4_m5x2_ck_3630_ops,
615};
616
617static struct clk dpll4_m3x2_ck_3630 = {
618 .core = &dpll4_m3x2_ck_3630_core,
619};
620
621static const char *omap_54m_fck_parent_names[] = {
622 "dpll4_m3x2_ck", "sys_altclk",
623};
624
625DEFINE_CLK_MUX(omap_54m_fck, omap_54m_fck_parent_names, NULL, 0x0,
626 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP3430_SOURCE_54M_SHIFT,
627 OMAP3430_SOURCE_54M_WIDTH, 0x0, NULL);
628
629static const struct clksel clkout2_src_clksel[] = {
630 { .parent = &core_ck, .rates = clkout2_src_core_rates },
631 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
632 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
633 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
634 { .parent = NULL },
635};
636
637static const char *clkout2_src_ck_parent_names[] = {
638 "core_ck", "sys_ck", "cm_96m_fck", "omap_54m_fck",
639};
640
641static const struct clk_ops clkout2_src_ck_ops = {
642 .init = &omap2_init_clk_clkdm,
643 .enable = &omap2_dflt_clk_enable,
644 .disable = &omap2_dflt_clk_disable,
645 .is_enabled = &omap2_dflt_clk_is_enabled,
646 .recalc_rate = &omap2_clksel_recalc,
647 .get_parent = &omap2_clksel_find_parent_index,
648 .set_parent = &omap2_clksel_set_parent,
649};
650
651DEFINE_CLK_OMAP_MUX_GATE(clkout2_src_ck, "core_clkdm",
652 clkout2_src_clksel, OMAP3430_CM_CLKOUT_CTRL,
653 OMAP3430_CLKOUT2SOURCE_MASK,
654 OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_EN_SHIFT,
655 NULL, clkout2_src_ck_parent_names, clkout2_src_ck_ops);
656
657static const struct clksel_rate omap_48m_cm96m_rates[] = {
658 { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
659 { .div = 0 }
660};
661
662static const struct clksel_rate omap_48m_alt_rates[] = {
663 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
664 { .div = 0 }
665};
666
667static const struct clksel omap_48m_clksel[] = {
668 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
669 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
670 { .parent = NULL },
671};
672
673static const char *omap_48m_fck_parent_names[] = {
674 "cm_96m_fck", "sys_altclk",
675};
676
677static struct clk omap_48m_fck;
678
679static const struct clk_ops omap_48m_fck_ops = {
680 .recalc_rate = &omap2_clksel_recalc,
681 .get_parent = &omap2_clksel_find_parent_index,
682 .set_parent = &omap2_clksel_set_parent,
683};
684
685static struct clk_hw_omap omap_48m_fck_hw = {
686 .hw = {
687 .clk = &omap_48m_fck,
688 },
689 .clksel = omap_48m_clksel,
690 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
691 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
692};
693
694DEFINE_STRUCT_CLK(omap_48m_fck, omap_48m_fck_parent_names, omap_48m_fck_ops);
695
696DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck_core, 0x0,
697 1, 4);
698
699static struct clk core_12m_fck;
700
701static const char *core_12m_fck_parent_names[] = {
702 "omap_12m_fck",
703};
704
705DEFINE_STRUCT_CLK_HW_OMAP(core_12m_fck, "core_l4_clkdm");
706DEFINE_STRUCT_CLK(core_12m_fck, core_12m_fck_parent_names, core_l4_ick_ops);
707
708static struct clk core_48m_fck;
709
710static const char *core_48m_fck_parent_names[] = {
711 "omap_48m_fck",
712};
713
714DEFINE_STRUCT_CLK_HW_OMAP(core_48m_fck, "core_l4_clkdm");
715DEFINE_STRUCT_CLK(core_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
716
717static const char *omap_96m_fck_parent_names[] = {
718 "cm_96m_fck", "sys_ck",
719};
720
721DEFINE_CLK_MUX(omap_96m_fck, omap_96m_fck_parent_names, NULL, 0x0,
722 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
723 OMAP3430_SOURCE_96M_SHIFT, OMAP3430_SOURCE_96M_WIDTH, 0x0, NULL);
724
725static struct clk core_96m_fck;
726
727static const char *core_96m_fck_parent_names[] = {
728 "omap_96m_fck",
729};
730
731DEFINE_STRUCT_CLK_HW_OMAP(core_96m_fck, "core_l4_clkdm");
732DEFINE_STRUCT_CLK(core_96m_fck, core_96m_fck_parent_names, core_l4_ick_ops);
733
734static struct clk core_l3_ick;
735
736static const char *core_l3_ick_parent_names[] = {
737 "l3_ick",
738};
739
740DEFINE_STRUCT_CLK_HW_OMAP(core_l3_ick, "core_l3_clkdm");
741DEFINE_STRUCT_CLK(core_l3_ick, core_l3_ick_parent_names, core_l4_ick_ops);
742
743DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck_core, 0x0,
744 2, 1);
745
746static struct clk corex2_fck;
747
748static const char *corex2_fck_parent_names[] = {
749 "dpll3_m2x2_ck",
750};
751
752DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL);
753DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops);
754
755static const char *cpefuse_fck_parent_names[] = {
756 "sys_ck",
757};
758
759static struct clk cpefuse_fck;
760
761static struct clk_hw_omap cpefuse_fck_hw = {
762 .hw = {
763 .clk = &cpefuse_fck,
764 },
765 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
766 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
767 .clkdm_name = "core_l4_clkdm",
768};
769
770DEFINE_STRUCT_CLK(cpefuse_fck, cpefuse_fck_parent_names, aes2_ick_ops);
771
772static struct clk csi2_96m_fck;
773
774static const char *csi2_96m_fck_parent_names[] = {
775 "core_96m_fck",
776};
777
778static struct clk_hw_omap csi2_96m_fck_hw = {
779 .hw = {
780 .clk = &csi2_96m_fck,
781 },
782 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
783 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
784 .clkdm_name = "cam_clkdm",
785};
786
787DEFINE_STRUCT_CLK(csi2_96m_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
788
789static struct clk d2d_26m_fck;
790
791static struct clk_hw_omap d2d_26m_fck_hw = {
792 .hw = {
793 .clk = &d2d_26m_fck,
794 },
795 .ops = &clkhwops_wait,
796 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
797 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
798 .clkdm_name = "d2d_clkdm",
799};
800
801DEFINE_STRUCT_CLK(d2d_26m_fck, cpefuse_fck_parent_names, aes2_ick_ops);
802
803static struct clk des1_ick;
804
805static struct clk_hw_omap des1_ick_hw = {
806 .hw = {
807 .clk = &des1_ick,
808 },
809 .ops = &clkhwops_iclk_wait,
810 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
811 .enable_bit = OMAP3430_EN_DES1_SHIFT,
812};
813
814DEFINE_STRUCT_CLK(des1_ick, aes1_ick_parent_names, aes1_ick_ops);
815
816static struct clk des2_ick;
817
818static struct clk_hw_omap des2_ick_hw = {
819 .hw = {
820 .clk = &des2_ick,
821 },
822 .ops = &clkhwops_iclk_wait,
823 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
824 .enable_bit = OMAP3430_EN_DES2_SHIFT,
825 .clkdm_name = "core_l4_clkdm",
826};
827
828DEFINE_STRUCT_CLK(des2_ick, aes2_ick_parent_names, aes2_ick_ops);
829
830DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck_core, 0x0,
831 OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
832 OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH,
833 CLK_DIVIDER_ONE_BASED, NULL);
834
835static struct clk dpll2_fck;
836
837static struct dpll_data dpll2_dd = {
838 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
839 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
840 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
841 .clk_bypass = &dpll2_fck,
842 .clk_ref = &sys_ck,
843 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
844 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
845 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
846 .modes = ((1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
847 (1 << DPLL_LOW_POWER_BYPASS)),
848 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
849 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
850 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
851 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
852 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
853 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
854 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
855 .max_multiplier = OMAP3_MAX_DPLL_MULT,
856 .min_divider = 1,
857 .max_divider = OMAP3_MAX_DPLL_DIV,
858};
859
860static struct clk dpll2_ck;
861
862static struct clk_hw_omap dpll2_ck_hw = {
863 .hw = {
864 .clk = &dpll2_ck,
865 },
866 .ops = &clkhwops_omap3_dpll,
867 .dpll_data = &dpll2_dd,
868 .clkdm_name = "dpll2_clkdm",
869};
870
871DEFINE_STRUCT_CLK(dpll2_ck, dpll3_ck_parent_names, dpll1_ck_ops);
872
873DEFINE_CLK_DIVIDER(dpll2_fck, "core_ck", &core_ck_core, 0x0,
874 OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
875 OMAP3430_IVA2_CLK_SRC_SHIFT, OMAP3430_IVA2_CLK_SRC_WIDTH,
876 CLK_DIVIDER_ONE_BASED, NULL);
877
878DEFINE_CLK_DIVIDER(dpll2_m2_ck, "dpll2_ck", &dpll2_ck_core, 0x0,
879 OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
880 OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT,
881 OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH,
882 CLK_DIVIDER_ONE_BASED, NULL);
883
884DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck_core, 0x0,
885 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
886 OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH,
887 CLK_DIVIDER_ONE_BASED, NULL);
888
889static struct clk dpll3_m3x2_ck;
890
891static const char *dpll3_m3x2_ck_parent_names[] = {
892 "dpll3_m3_ck",
893};
894
895static struct clk_hw_omap dpll3_m3x2_ck_hw = {
896 .hw = {
897 .clk = &dpll3_m3x2_ck,
898 },
899 .ops = &clkhwops_wait,
900 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
901 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
902 .flags = INVERT_ENABLE,
903 .clkdm_name = "dpll3_clkdm",
904};
905
906DEFINE_STRUCT_CLK(dpll3_m3x2_ck, dpll3_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
907
908static struct clk_core dpll3_m3x2_ck_3630_core = {
909 .name = "dpll3_m3x2_ck",
910 .hw = &dpll3_m3x2_ck_hw.hw,
911 .parent_names = dpll3_m3x2_ck_parent_names,
912 .num_parents = ARRAY_SIZE(dpll3_m3x2_ck_parent_names),
913 .ops = &dpll4_m5x2_ck_3630_ops,
914};
915
916static struct clk dpll3_m3x2_ck_3630 = {
917 .core = &dpll3_m3x2_ck_3630_core,
918};
919
920DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck_core, 0x0, 2, 1);
921
922DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck, "dpll4_ck", &dpll4_ck_core, 0x0,
923 OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
924 OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH,
925 0, dpll4_mx_ck_div_table, NULL);
926
927static struct clk dpll4_m4x2_ck;
928
929static const char *dpll4_m4x2_ck_parent_names[] = {
930 "dpll4_m4_ck",
931};
932
933static struct clk_hw_omap dpll4_m4x2_ck_hw = {
934 .hw = {
935 .clk = &dpll4_m4x2_ck,
936 },
937 .ops = &clkhwops_wait,
938 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
939 .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
940 .flags = INVERT_ENABLE,
941 .clkdm_name = "dpll4_clkdm",
942};
943
944DEFINE_STRUCT_CLK_FLAGS(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names,
945 dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
946
947static struct clk_core dpll4_m4x2_ck_3630_core = {
948 .name = "dpll4_m4x2_ck",
949 .hw = &dpll4_m4x2_ck_hw.hw,
950 .parent_names = dpll4_m4x2_ck_parent_names,
951 .num_parents = ARRAY_SIZE(dpll4_m4x2_ck_parent_names),
952 .ops = &dpll4_m5x2_ck_3630_ops,
953 .flags = CLK_SET_RATE_PARENT,
954};
955
956static struct clk dpll4_m4x2_ck_3630 = {
957 .core = &dpll4_m4x2_ck_3630_core,
958};
959
960DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck_core, 0x0,
961 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
962 OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH,
963 CLK_DIVIDER_ONE_BASED, NULL);
964
965static struct clk dpll4_m6x2_ck;
966
967static const char *dpll4_m6x2_ck_parent_names[] = {
968 "dpll4_m6_ck",
969};
970
971static struct clk_hw_omap dpll4_m6x2_ck_hw = {
972 .hw = {
973 .clk = &dpll4_m6x2_ck,
974 },
975 .ops = &clkhwops_wait,
976 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
977 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
978 .flags = INVERT_ENABLE,
979 .clkdm_name = "dpll4_clkdm",
980};
981
982DEFINE_STRUCT_CLK(dpll4_m6x2_ck, dpll4_m6x2_ck_parent_names, dpll4_m5x2_ck_ops);
983
984static struct clk_core dpll4_m6x2_ck_3630_core = {
985 .name = "dpll4_m6x2_ck",
986 .hw = &dpll4_m6x2_ck_hw.hw,
987 .parent_names = dpll4_m6x2_ck_parent_names,
988 .num_parents = ARRAY_SIZE(dpll4_m6x2_ck_parent_names),
989 .ops = &dpll4_m5x2_ck_3630_ops,
990};
991
992static struct clk dpll4_m6x2_ck_3630 = {
993 .core = &dpll4_m6x2_ck_3630_core,
994};
995
996DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck, "dpll4_ck", &dpll4_ck_core, 0x0, 2, 1);
997
998static struct dpll_data dpll5_dd = {
999 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
1000 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
1001 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
1002 .clk_bypass = &sys_ck,
1003 .clk_ref = &sys_ck,
1004 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
1005 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
1006 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
1007 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
1008 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
1009 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
1010 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
1011 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
1012 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
1013 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
1014 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
1015 .max_multiplier = OMAP3_MAX_DPLL_MULT,
1016 .min_divider = 1,
1017 .max_divider = OMAP3_MAX_DPLL_DIV,
1018};
1019
1020static struct clk dpll5_ck;
1021
1022static struct clk_hw_omap dpll5_ck_hw = {
1023 .hw = {
1024 .clk = &dpll5_ck,
1025 },
1026 .ops = &clkhwops_omap3_dpll,
1027 .dpll_data = &dpll5_dd,
1028 .clkdm_name = "dpll5_clkdm",
1029};
1030
1031DEFINE_STRUCT_CLK(dpll5_ck, dpll3_ck_parent_names, dpll1_ck_ops);
1032
1033DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck_core, 0x0,
1034 OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
1035 OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH,
1036 CLK_DIVIDER_ONE_BASED, NULL);
1037
1038static struct clk dss1_alwon_fck_3430es1;
1039
1040static const char *dss1_alwon_fck_3430es1_parent_names[] = {
1041 "dpll4_m4x2_ck",
1042};
1043
1044static struct clk_hw_omap dss1_alwon_fck_3430es1_hw = {
1045 .hw = {
1046 .clk = &dss1_alwon_fck_3430es1,
1047 },
1048 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1049 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
1050 .clkdm_name = "dss_clkdm",
1051};
1052
1053DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es1,
1054 dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops,
1055 CLK_SET_RATE_PARENT);
1056
1057static struct clk dss1_alwon_fck_3430es2;
1058
1059static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = {
1060 .hw = {
1061 .clk = &dss1_alwon_fck_3430es2,
1062 },
1063 .ops = &clkhwops_omap3430es2_dss_usbhost_wait,
1064 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1065 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
1066 .clkdm_name = "dss_clkdm",
1067};
1068
1069DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es2,
1070 dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops,
1071 CLK_SET_RATE_PARENT);
1072
1073static struct clk dss2_alwon_fck;
1074
1075static struct clk_hw_omap dss2_alwon_fck_hw = {
1076 .hw = {
1077 .clk = &dss2_alwon_fck,
1078 },
1079 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1080 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
1081 .clkdm_name = "dss_clkdm",
1082};
1083
1084DEFINE_STRUCT_CLK(dss2_alwon_fck, cpefuse_fck_parent_names, aes2_ick_ops);
1085
1086static struct clk dss_96m_fck;
1087
1088static struct clk_hw_omap dss_96m_fck_hw = {
1089 .hw = {
1090 .clk = &dss_96m_fck,
1091 },
1092 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1093 .enable_bit = OMAP3430_EN_TV_SHIFT,
1094 .clkdm_name = "dss_clkdm",
1095};
1096
1097DEFINE_STRUCT_CLK(dss_96m_fck, core_96m_fck_parent_names, aes2_ick_ops);
1098
1099static struct clk dss_ick_3430es1;
1100
1101static struct clk_hw_omap dss_ick_3430es1_hw = {
1102 .hw = {
1103 .clk = &dss_ick_3430es1,
1104 },
1105 .ops = &clkhwops_iclk,
1106 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1107 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1108 .clkdm_name = "dss_clkdm",
1109};
1110
1111DEFINE_STRUCT_CLK(dss_ick_3430es1, security_l4_ick2_parent_names, aes2_ick_ops);
1112
1113static struct clk dss_ick_3430es2;
1114
1115static struct clk_hw_omap dss_ick_3430es2_hw = {
1116 .hw = {
1117 .clk = &dss_ick_3430es2,
1118 },
1119 .ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
1120 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1121 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1122 .clkdm_name = "dss_clkdm",
1123};
1124
1125DEFINE_STRUCT_CLK(dss_ick_3430es2, security_l4_ick2_parent_names, aes2_ick_ops);
1126
1127static struct clk dss_tv_fck;
1128
1129static const char *dss_tv_fck_parent_names[] = {
1130 "omap_54m_fck",
1131};
1132
1133static struct clk_hw_omap dss_tv_fck_hw = {
1134 .hw = {
1135 .clk = &dss_tv_fck,
1136 },
1137 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1138 .enable_bit = OMAP3430_EN_TV_SHIFT,
1139 .clkdm_name = "dss_clkdm",
1140};
1141
1142DEFINE_STRUCT_CLK(dss_tv_fck, dss_tv_fck_parent_names, aes2_ick_ops);
1143
1144static struct clk emac_fck;
1145
1146static const char *emac_fck_parent_names[] = {
1147 "rmii_ck",
1148};
1149
1150static struct clk_hw_omap emac_fck_hw = {
1151 .hw = {
1152 .clk = &emac_fck,
1153 },
1154 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1155 .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
1156};
1157
1158DEFINE_STRUCT_CLK(emac_fck, emac_fck_parent_names, aes1_ick_ops);
1159
1160static struct clk ipss_ick;
1161
1162static const char *ipss_ick_parent_names[] = {
1163 "core_l3_ick",
1164};
1165
1166static struct clk_hw_omap ipss_ick_hw = {
1167 .hw = {
1168 .clk = &ipss_ick,
1169 },
1170 .ops = &clkhwops_am35xx_ipss_wait,
1171 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1172 .enable_bit = AM35XX_EN_IPSS_SHIFT,
1173 .clkdm_name = "core_l3_clkdm",
1174};
1175
1176DEFINE_STRUCT_CLK(ipss_ick, ipss_ick_parent_names, aes2_ick_ops);
1177
1178static struct clk emac_ick;
1179
1180static const char *emac_ick_parent_names[] = {
1181 "ipss_ick",
1182};
1183
1184static struct clk_hw_omap emac_ick_hw = {
1185 .hw = {
1186 .clk = &emac_ick,
1187 },
1188 .ops = &clkhwops_am35xx_ipss_module_wait,
1189 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1190 .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
1191 .clkdm_name = "core_l3_clkdm",
1192};
1193
1194DEFINE_STRUCT_CLK(emac_ick, emac_ick_parent_names, aes2_ick_ops);
1195
1196static struct clk emu_core_alwon_ck;
1197
1198static const char *emu_core_alwon_ck_parent_names[] = {
1199 "dpll3_m3x2_ck",
1200};
1201
1202DEFINE_STRUCT_CLK_HW_OMAP(emu_core_alwon_ck, "dpll3_clkdm");
1203DEFINE_STRUCT_CLK(emu_core_alwon_ck, emu_core_alwon_ck_parent_names,
1204 core_l4_ick_ops);
1205
1206static struct clk emu_mpu_alwon_ck;
1207
1208static const char *emu_mpu_alwon_ck_parent_names[] = {
1209 "mpu_ck",
1210};
1211
1212DEFINE_STRUCT_CLK_HW_OMAP(emu_mpu_alwon_ck, NULL);
1213DEFINE_STRUCT_CLK(emu_mpu_alwon_ck, emu_mpu_alwon_ck_parent_names, core_ck_ops);
1214
1215static struct clk emu_per_alwon_ck;
1216
1217static const char *emu_per_alwon_ck_parent_names[] = {
1218 "dpll4_m6x2_ck",
1219};
1220
1221DEFINE_STRUCT_CLK_HW_OMAP(emu_per_alwon_ck, "dpll4_clkdm");
1222DEFINE_STRUCT_CLK(emu_per_alwon_ck, emu_per_alwon_ck_parent_names,
1223 core_l4_ick_ops);
1224
1225static const char *emu_src_ck_parent_names[] = {
1226 "sys_ck", "emu_core_alwon_ck", "emu_per_alwon_ck", "emu_mpu_alwon_ck",
1227};
1228
1229static const struct clksel_rate emu_src_sys_rates[] = {
1230 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1231 { .div = 0 },
1232};
1233
1234static const struct clksel_rate emu_src_core_rates[] = {
1235 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1236 { .div = 0 },
1237};
1238
1239static const struct clksel_rate emu_src_per_rates[] = {
1240 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
1241 { .div = 0 },
1242};
1243
1244static const struct clksel_rate emu_src_mpu_rates[] = {
1245 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1246 { .div = 0 },
1247};
1248
1249static const struct clksel emu_src_clksel[] = {
1250 { .parent = &sys_ck, .rates = emu_src_sys_rates },
1251 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
1252 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
1253 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
1254 { .parent = NULL },
1255};
1256
1257static const struct clk_ops emu_src_ck_ops = {
1258 .init = &omap2_init_clk_clkdm,
1259 .recalc_rate = &omap2_clksel_recalc,
1260 .get_parent = &omap2_clksel_find_parent_index,
1261 .set_parent = &omap2_clksel_set_parent,
1262 .enable = &omap2_clkops_enable_clkdm,
1263 .disable = &omap2_clkops_disable_clkdm,
1264};
1265
1266static struct clk emu_src_ck;
1267
1268static struct clk_hw_omap emu_src_ck_hw = {
1269 .hw = {
1270 .clk = &emu_src_ck,
1271 },
1272 .clksel = emu_src_clksel,
1273 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1274 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
1275 .clkdm_name = "emu_clkdm",
1276};
1277
1278DEFINE_STRUCT_CLK(emu_src_ck, emu_src_ck_parent_names, emu_src_ck_ops);
1279
1280DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck_core, 0x0,
1281 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1282 OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH,
1283 CLK_DIVIDER_ONE_BASED, NULL);
1284
1285static struct clk fac_ick;
1286
1287static struct clk_hw_omap fac_ick_hw = {
1288 .hw = {
1289 .clk = &fac_ick,
1290 },
1291 .ops = &clkhwops_iclk_wait,
1292 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1293 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1294 .clkdm_name = "core_l4_clkdm",
1295};
1296
1297DEFINE_STRUCT_CLK(fac_ick, aes2_ick_parent_names, aes2_ick_ops);
1298
1299static struct clk fshostusb_fck;
1300
1301static const char *fshostusb_fck_parent_names[] = {
1302 "core_48m_fck",
1303};
1304
1305static struct clk_hw_omap fshostusb_fck_hw = {
1306 .hw = {
1307 .clk = &fshostusb_fck,
1308 },
1309 .ops = &clkhwops_wait,
1310 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1311 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1312 .clkdm_name = "core_l4_clkdm",
1313};
1314
1315DEFINE_STRUCT_CLK(fshostusb_fck, fshostusb_fck_parent_names, aes2_ick_ops);
1316
1317static struct clk gfx_l3_ck;
1318
1319static struct clk_hw_omap gfx_l3_ck_hw = {
1320 .hw = {
1321 .clk = &gfx_l3_ck,
1322 },
1323 .ops = &clkhwops_wait,
1324 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1325 .enable_bit = OMAP_EN_GFX_SHIFT,
1326 .clkdm_name = "gfx_3430es1_clkdm",
1327};
1328
1329DEFINE_STRUCT_CLK(gfx_l3_ck, core_l3_ick_parent_names, aes1_ick_ops);
1330
1331DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick_core, 0x0,
1332 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1333 OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH,
1334 CLK_DIVIDER_ONE_BASED, NULL);
1335
1336static struct clk gfx_cg1_ck;
1337
1338static const char *gfx_cg1_ck_parent_names[] = {
1339 "gfx_l3_fck",
1340};
1341
1342static struct clk_hw_omap gfx_cg1_ck_hw = {
1343 .hw = {
1344 .clk = &gfx_cg1_ck,
1345 },
1346 .ops = &clkhwops_wait,
1347 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1348 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1349 .clkdm_name = "gfx_3430es1_clkdm",
1350};
1351
1352DEFINE_STRUCT_CLK(gfx_cg1_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1353
1354static struct clk gfx_cg2_ck;
1355
1356static struct clk_hw_omap gfx_cg2_ck_hw = {
1357 .hw = {
1358 .clk = &gfx_cg2_ck,
1359 },
1360 .ops = &clkhwops_wait,
1361 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1362 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1363 .clkdm_name = "gfx_3430es1_clkdm",
1364};
1365
1366DEFINE_STRUCT_CLK(gfx_cg2_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1367
1368static struct clk gfx_l3_ick;
1369
1370static const char *gfx_l3_ick_parent_names[] = {
1371 "gfx_l3_ck",
1372};
1373
1374DEFINE_STRUCT_CLK_HW_OMAP(gfx_l3_ick, "gfx_3430es1_clkdm");
1375DEFINE_STRUCT_CLK(gfx_l3_ick, gfx_l3_ick_parent_names, core_l4_ick_ops);
1376
1377static struct clk wkup_32k_fck;
1378
1379static const char *wkup_32k_fck_parent_names[] = {
1380 "omap_32k_fck",
1381};
1382
1383DEFINE_STRUCT_CLK_HW_OMAP(wkup_32k_fck, "wkup_clkdm");
1384DEFINE_STRUCT_CLK(wkup_32k_fck, wkup_32k_fck_parent_names, core_l4_ick_ops);
1385
1386static struct clk gpio1_dbck;
1387
1388static const char *gpio1_dbck_parent_names[] = {
1389 "wkup_32k_fck",
1390};
1391
1392static struct clk_hw_omap gpio1_dbck_hw = {
1393 .hw = {
1394 .clk = &gpio1_dbck,
1395 },
1396 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1397 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
1398 .clkdm_name = "wkup_clkdm",
1399};
1400
1401DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops);
1402
1403static struct clk wkup_l4_ick;
1404
1405DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm");
1406DEFINE_STRUCT_CLK(wkup_l4_ick, cpefuse_fck_parent_names, core_l4_ick_ops);
1407
1408static struct clk gpio1_ick;
1409
1410static const char *gpio1_ick_parent_names[] = {
1411 "wkup_l4_ick",
1412};
1413
1414static struct clk_hw_omap gpio1_ick_hw = {
1415 .hw = {
1416 .clk = &gpio1_ick,
1417 },
1418 .ops = &clkhwops_iclk_wait,
1419 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1420 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
1421 .clkdm_name = "wkup_clkdm",
1422};
1423
1424DEFINE_STRUCT_CLK(gpio1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1425
1426static struct clk per_32k_alwon_fck;
1427
1428DEFINE_STRUCT_CLK_HW_OMAP(per_32k_alwon_fck, "per_clkdm");
1429DEFINE_STRUCT_CLK(per_32k_alwon_fck, wkup_32k_fck_parent_names,
1430 core_l4_ick_ops);
1431
1432static struct clk gpio2_dbck;
1433
1434static const char *gpio2_dbck_parent_names[] = {
1435 "per_32k_alwon_fck",
1436};
1437
1438static struct clk_hw_omap gpio2_dbck_hw = {
1439 .hw = {
1440 .clk = &gpio2_dbck,
1441 },
1442 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1443 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
1444 .clkdm_name = "per_clkdm",
1445};
1446
1447DEFINE_STRUCT_CLK(gpio2_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1448
1449static struct clk per_l4_ick;
1450
1451DEFINE_STRUCT_CLK_HW_OMAP(per_l4_ick, "per_clkdm");
1452DEFINE_STRUCT_CLK(per_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
1453
1454static struct clk gpio2_ick;
1455
1456static const char *gpio2_ick_parent_names[] = {
1457 "per_l4_ick",
1458};
1459
1460static struct clk_hw_omap gpio2_ick_hw = {
1461 .hw = {
1462 .clk = &gpio2_ick,
1463 },
1464 .ops = &clkhwops_iclk_wait,
1465 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1466 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
1467 .clkdm_name = "per_clkdm",
1468};
1469
1470DEFINE_STRUCT_CLK(gpio2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1471
1472static struct clk gpio3_dbck;
1473
1474static struct clk_hw_omap gpio3_dbck_hw = {
1475 .hw = {
1476 .clk = &gpio3_dbck,
1477 },
1478 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1479 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
1480 .clkdm_name = "per_clkdm",
1481};
1482
1483DEFINE_STRUCT_CLK(gpio3_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1484
1485static struct clk gpio3_ick;
1486
1487static struct clk_hw_omap gpio3_ick_hw = {
1488 .hw = {
1489 .clk = &gpio3_ick,
1490 },
1491 .ops = &clkhwops_iclk_wait,
1492 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1493 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
1494 .clkdm_name = "per_clkdm",
1495};
1496
1497DEFINE_STRUCT_CLK(gpio3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1498
1499static struct clk gpio4_dbck;
1500
1501static struct clk_hw_omap gpio4_dbck_hw = {
1502 .hw = {
1503 .clk = &gpio4_dbck,
1504 },
1505 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1506 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
1507 .clkdm_name = "per_clkdm",
1508};
1509
1510DEFINE_STRUCT_CLK(gpio4_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1511
1512static struct clk gpio4_ick;
1513
1514static struct clk_hw_omap gpio4_ick_hw = {
1515 .hw = {
1516 .clk = &gpio4_ick,
1517 },
1518 .ops = &clkhwops_iclk_wait,
1519 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1520 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
1521 .clkdm_name = "per_clkdm",
1522};
1523
1524DEFINE_STRUCT_CLK(gpio4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1525
1526static struct clk gpio5_dbck;
1527
1528static struct clk_hw_omap gpio5_dbck_hw = {
1529 .hw = {
1530 .clk = &gpio5_dbck,
1531 },
1532 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1533 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
1534 .clkdm_name = "per_clkdm",
1535};
1536
1537DEFINE_STRUCT_CLK(gpio5_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1538
1539static struct clk gpio5_ick;
1540
1541static struct clk_hw_omap gpio5_ick_hw = {
1542 .hw = {
1543 .clk = &gpio5_ick,
1544 },
1545 .ops = &clkhwops_iclk_wait,
1546 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1547 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
1548 .clkdm_name = "per_clkdm",
1549};
1550
1551DEFINE_STRUCT_CLK(gpio5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1552
1553static struct clk gpio6_dbck;
1554
1555static struct clk_hw_omap gpio6_dbck_hw = {
1556 .hw = {
1557 .clk = &gpio6_dbck,
1558 },
1559 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1560 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
1561 .clkdm_name = "per_clkdm",
1562};
1563
1564DEFINE_STRUCT_CLK(gpio6_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1565
1566static struct clk gpio6_ick;
1567
1568static struct clk_hw_omap gpio6_ick_hw = {
1569 .hw = {
1570 .clk = &gpio6_ick,
1571 },
1572 .ops = &clkhwops_iclk_wait,
1573 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1574 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
1575 .clkdm_name = "per_clkdm",
1576};
1577
1578DEFINE_STRUCT_CLK(gpio6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1579
1580static struct clk gpmc_fck;
1581
1582static struct clk_hw_omap gpmc_fck_hw = {
1583 .hw = {
1584 .clk = &gpmc_fck,
1585 },
1586 .flags = ENABLE_ON_INIT,
1587 .clkdm_name = "core_l3_clkdm",
1588};
1589
1590DEFINE_STRUCT_CLK(gpmc_fck, ipss_ick_parent_names, core_l4_ick_ops);
1591
1592static const struct clksel omap343x_gpt_clksel[] = {
1593 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1594 { .parent = &sys_ck, .rates = gpt_sys_rates },
1595 { .parent = NULL },
1596};
1597
1598static const char *gpt10_fck_parent_names[] = {
1599 "omap_32k_fck", "sys_ck",
1600};
1601
1602DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1603 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1604 OMAP3430_CLKSEL_GPT10_MASK,
1605 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1606 OMAP3430_EN_GPT10_SHIFT, &clkhwops_wait,
1607 gpt10_fck_parent_names, clkout2_src_ck_ops);
1608
1609static struct clk gpt10_ick;
1610
1611static struct clk_hw_omap gpt10_ick_hw = {
1612 .hw = {
1613 .clk = &gpt10_ick,
1614 },
1615 .ops = &clkhwops_iclk_wait,
1616 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1617 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1618 .clkdm_name = "core_l4_clkdm",
1619};
1620
1621DEFINE_STRUCT_CLK(gpt10_ick, aes2_ick_parent_names, aes2_ick_ops);
1622
1623DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1624 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1625 OMAP3430_CLKSEL_GPT11_MASK,
1626 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1627 OMAP3430_EN_GPT11_SHIFT, &clkhwops_wait,
1628 gpt10_fck_parent_names, clkout2_src_ck_ops);
1629
1630static struct clk gpt11_ick;
1631
1632static struct clk_hw_omap gpt11_ick_hw = {
1633 .hw = {
1634 .clk = &gpt11_ick,
1635 },
1636 .ops = &clkhwops_iclk_wait,
1637 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1638 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1639 .clkdm_name = "core_l4_clkdm",
1640};
1641
1642DEFINE_STRUCT_CLK(gpt11_ick, aes2_ick_parent_names, aes2_ick_ops);
1643
1644static struct clk gpt12_fck;
1645
1646static const char *gpt12_fck_parent_names[] = {
1647 "secure_32k_fck",
1648};
1649
1650DEFINE_STRUCT_CLK_HW_OMAP(gpt12_fck, "wkup_clkdm");
1651DEFINE_STRUCT_CLK(gpt12_fck, gpt12_fck_parent_names, core_l4_ick_ops);
1652
1653static struct clk gpt12_ick;
1654
1655static struct clk_hw_omap gpt12_ick_hw = {
1656 .hw = {
1657 .clk = &gpt12_ick,
1658 },
1659 .ops = &clkhwops_iclk_wait,
1660 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1661 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
1662 .clkdm_name = "wkup_clkdm",
1663};
1664
1665DEFINE_STRUCT_CLK(gpt12_ick, gpio1_ick_parent_names, aes2_ick_ops);
1666
1667DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "wkup_clkdm", omap343x_gpt_clksel,
1668 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1669 OMAP3430_CLKSEL_GPT1_MASK,
1670 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1671 OMAP3430_EN_GPT1_SHIFT, &clkhwops_wait,
1672 gpt10_fck_parent_names, clkout2_src_ck_ops);
1673
1674static struct clk gpt1_ick;
1675
1676static struct clk_hw_omap gpt1_ick_hw = {
1677 .hw = {
1678 .clk = &gpt1_ick,
1679 },
1680 .ops = &clkhwops_iclk_wait,
1681 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1682 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
1683 .clkdm_name = "wkup_clkdm",
1684};
1685
1686DEFINE_STRUCT_CLK(gpt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1687
1688DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "per_clkdm", omap343x_gpt_clksel,
1689 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1690 OMAP3430_CLKSEL_GPT2_MASK,
1691 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1692 OMAP3430_EN_GPT2_SHIFT, &clkhwops_wait,
1693 gpt10_fck_parent_names, clkout2_src_ck_ops);
1694
1695static struct clk gpt2_ick;
1696
1697static struct clk_hw_omap gpt2_ick_hw = {
1698 .hw = {
1699 .clk = &gpt2_ick,
1700 },
1701 .ops = &clkhwops_iclk_wait,
1702 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1703 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
1704 .clkdm_name = "per_clkdm",
1705};
1706
1707DEFINE_STRUCT_CLK(gpt2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1708
1709DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "per_clkdm", omap343x_gpt_clksel,
1710 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1711 OMAP3430_CLKSEL_GPT3_MASK,
1712 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1713 OMAP3430_EN_GPT3_SHIFT, &clkhwops_wait,
1714 gpt10_fck_parent_names, clkout2_src_ck_ops);
1715
1716static struct clk gpt3_ick;
1717
1718static struct clk_hw_omap gpt3_ick_hw = {
1719 .hw = {
1720 .clk = &gpt3_ick,
1721 },
1722 .ops = &clkhwops_iclk_wait,
1723 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1724 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
1725 .clkdm_name = "per_clkdm",
1726};
1727
1728DEFINE_STRUCT_CLK(gpt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1729
1730DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "per_clkdm", omap343x_gpt_clksel,
1731 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1732 OMAP3430_CLKSEL_GPT4_MASK,
1733 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1734 OMAP3430_EN_GPT4_SHIFT, &clkhwops_wait,
1735 gpt10_fck_parent_names, clkout2_src_ck_ops);
1736
1737static struct clk gpt4_ick;
1738
1739static struct clk_hw_omap gpt4_ick_hw = {
1740 .hw = {
1741 .clk = &gpt4_ick,
1742 },
1743 .ops = &clkhwops_iclk_wait,
1744 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1745 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
1746 .clkdm_name = "per_clkdm",
1747};
1748
1749DEFINE_STRUCT_CLK(gpt4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1750
1751DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "per_clkdm", omap343x_gpt_clksel,
1752 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1753 OMAP3430_CLKSEL_GPT5_MASK,
1754 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1755 OMAP3430_EN_GPT5_SHIFT, &clkhwops_wait,
1756 gpt10_fck_parent_names, clkout2_src_ck_ops);
1757
1758static struct clk gpt5_ick;
1759
1760static struct clk_hw_omap gpt5_ick_hw = {
1761 .hw = {
1762 .clk = &gpt5_ick,
1763 },
1764 .ops = &clkhwops_iclk_wait,
1765 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1766 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
1767 .clkdm_name = "per_clkdm",
1768};
1769
1770DEFINE_STRUCT_CLK(gpt5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1771
1772DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "per_clkdm", omap343x_gpt_clksel,
1773 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1774 OMAP3430_CLKSEL_GPT6_MASK,
1775 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1776 OMAP3430_EN_GPT6_SHIFT, &clkhwops_wait,
1777 gpt10_fck_parent_names, clkout2_src_ck_ops);
1778
1779static struct clk gpt6_ick;
1780
1781static struct clk_hw_omap gpt6_ick_hw = {
1782 .hw = {
1783 .clk = &gpt6_ick,
1784 },
1785 .ops = &clkhwops_iclk_wait,
1786 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1787 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
1788 .clkdm_name = "per_clkdm",
1789};
1790
1791DEFINE_STRUCT_CLK(gpt6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1792
1793DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "per_clkdm", omap343x_gpt_clksel,
1794 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1795 OMAP3430_CLKSEL_GPT7_MASK,
1796 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1797 OMAP3430_EN_GPT7_SHIFT, &clkhwops_wait,
1798 gpt10_fck_parent_names, clkout2_src_ck_ops);
1799
1800static struct clk gpt7_ick;
1801
1802static struct clk_hw_omap gpt7_ick_hw = {
1803 .hw = {
1804 .clk = &gpt7_ick,
1805 },
1806 .ops = &clkhwops_iclk_wait,
1807 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1808 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
1809 .clkdm_name = "per_clkdm",
1810};
1811
1812DEFINE_STRUCT_CLK(gpt7_ick, gpio2_ick_parent_names, aes2_ick_ops);
1813
1814DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "per_clkdm", omap343x_gpt_clksel,
1815 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1816 OMAP3430_CLKSEL_GPT8_MASK,
1817 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1818 OMAP3430_EN_GPT8_SHIFT, &clkhwops_wait,
1819 gpt10_fck_parent_names, clkout2_src_ck_ops);
1820
1821static struct clk gpt8_ick;
1822
1823static struct clk_hw_omap gpt8_ick_hw = {
1824 .hw = {
1825 .clk = &gpt8_ick,
1826 },
1827 .ops = &clkhwops_iclk_wait,
1828 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1829 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
1830 .clkdm_name = "per_clkdm",
1831};
1832
1833DEFINE_STRUCT_CLK(gpt8_ick, gpio2_ick_parent_names, aes2_ick_ops);
1834
1835DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "per_clkdm", omap343x_gpt_clksel,
1836 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1837 OMAP3430_CLKSEL_GPT9_MASK,
1838 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1839 OMAP3430_EN_GPT9_SHIFT, &clkhwops_wait,
1840 gpt10_fck_parent_names, clkout2_src_ck_ops);
1841
1842static struct clk gpt9_ick;
1843
1844static struct clk_hw_omap gpt9_ick_hw = {
1845 .hw = {
1846 .clk = &gpt9_ick,
1847 },
1848 .ops = &clkhwops_iclk_wait,
1849 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1850 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
1851 .clkdm_name = "per_clkdm",
1852};
1853
1854DEFINE_STRUCT_CLK(gpt9_ick, gpio2_ick_parent_names, aes2_ick_ops);
1855
1856static struct clk hdq_fck;
1857
1858static const char *hdq_fck_parent_names[] = {
1859 "core_12m_fck",
1860};
1861
1862static struct clk_hw_omap hdq_fck_hw = {
1863 .hw = {
1864 .clk = &hdq_fck,
1865 },
1866 .ops = &clkhwops_wait,
1867 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1868 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1869 .clkdm_name = "core_l4_clkdm",
1870};
1871
1872DEFINE_STRUCT_CLK(hdq_fck, hdq_fck_parent_names, aes2_ick_ops);
1873
1874static struct clk hdq_ick;
1875
1876static struct clk_hw_omap hdq_ick_hw = {
1877 .hw = {
1878 .clk = &hdq_ick,
1879 },
1880 .ops = &clkhwops_iclk_wait,
1881 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1882 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1883 .clkdm_name = "core_l4_clkdm",
1884};
1885
1886DEFINE_STRUCT_CLK(hdq_ick, aes2_ick_parent_names, aes2_ick_ops);
1887
1888static struct clk hecc_ck;
1889
1890static struct clk_hw_omap hecc_ck_hw = {
1891 .hw = {
1892 .clk = &hecc_ck,
1893 },
1894 .ops = &clkhwops_am35xx_ipss_module_wait,
1895 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1896 .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
1897 .clkdm_name = "core_l3_clkdm",
1898};
1899
1900DEFINE_STRUCT_CLK(hecc_ck, cpefuse_fck_parent_names, aes2_ick_ops);
1901
1902static struct clk hsotgusb_fck_am35xx;
1903
1904static struct clk_hw_omap hsotgusb_fck_am35xx_hw = {
1905 .hw = {
1906 .clk = &hsotgusb_fck_am35xx,
1907 },
1908 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1909 .enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
1910 .clkdm_name = "core_l3_clkdm",
1911};
1912
1913DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, cpefuse_fck_parent_names, aes2_ick_ops);
1914
1915static struct clk hsotgusb_ick_3430es1;
1916
1917static struct clk_hw_omap hsotgusb_ick_3430es1_hw = {
1918 .hw = {
1919 .clk = &hsotgusb_ick_3430es1,
1920 },
1921 .ops = &clkhwops_iclk,
1922 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1923 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1924 .clkdm_name = "core_l3_clkdm",
1925};
1926
1927DEFINE_STRUCT_CLK(hsotgusb_ick_3430es1, ipss_ick_parent_names, aes2_ick_ops);
1928
1929static struct clk hsotgusb_ick_3430es2;
1930
1931static struct clk_hw_omap hsotgusb_ick_3430es2_hw = {
1932 .hw = {
1933 .clk = &hsotgusb_ick_3430es2,
1934 },
1935 .ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait,
1936 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1937 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1938 .clkdm_name = "core_l3_clkdm",
1939};
1940
1941DEFINE_STRUCT_CLK(hsotgusb_ick_3430es2, ipss_ick_parent_names, aes2_ick_ops);
1942
1943static struct clk hsotgusb_ick_am35xx;
1944
1945static struct clk_hw_omap hsotgusb_ick_am35xx_hw = {
1946 .hw = {
1947 .clk = &hsotgusb_ick_am35xx,
1948 },
1949 .ops = &clkhwops_am35xx_ipss_module_wait,
1950 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1951 .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
1952 .clkdm_name = "core_l3_clkdm",
1953};
1954
1955DEFINE_STRUCT_CLK(hsotgusb_ick_am35xx, emac_ick_parent_names, aes2_ick_ops);
1956
1957static struct clk i2c1_fck;
1958
1959static struct clk_hw_omap i2c1_fck_hw = {
1960 .hw = {
1961 .clk = &i2c1_fck,
1962 },
1963 .ops = &clkhwops_wait,
1964 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1965 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1966 .clkdm_name = "core_l4_clkdm",
1967};
1968
1969DEFINE_STRUCT_CLK(i2c1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1970
1971static struct clk i2c1_ick;
1972
1973static struct clk_hw_omap i2c1_ick_hw = {
1974 .hw = {
1975 .clk = &i2c1_ick,
1976 },
1977 .ops = &clkhwops_iclk_wait,
1978 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1979 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1980 .clkdm_name = "core_l4_clkdm",
1981};
1982
1983DEFINE_STRUCT_CLK(i2c1_ick, aes2_ick_parent_names, aes2_ick_ops);
1984
1985static struct clk i2c2_fck;
1986
1987static struct clk_hw_omap i2c2_fck_hw = {
1988 .hw = {
1989 .clk = &i2c2_fck,
1990 },
1991 .ops = &clkhwops_wait,
1992 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1993 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1994 .clkdm_name = "core_l4_clkdm",
1995};
1996
1997DEFINE_STRUCT_CLK(i2c2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1998
1999static struct clk i2c2_ick;
2000
2001static struct clk_hw_omap i2c2_ick_hw = {
2002 .hw = {
2003 .clk = &i2c2_ick,
2004 },
2005 .ops = &clkhwops_iclk_wait,
2006 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2007 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
2008 .clkdm_name = "core_l4_clkdm",
2009};
2010
2011DEFINE_STRUCT_CLK(i2c2_ick, aes2_ick_parent_names, aes2_ick_ops);
2012
2013static struct clk i2c3_fck;
2014
2015static struct clk_hw_omap i2c3_fck_hw = {
2016 .hw = {
2017 .clk = &i2c3_fck,
2018 },
2019 .ops = &clkhwops_wait,
2020 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2021 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
2022 .clkdm_name = "core_l4_clkdm",
2023};
2024
2025DEFINE_STRUCT_CLK(i2c3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2026
2027static struct clk i2c3_ick;
2028
2029static struct clk_hw_omap i2c3_ick_hw = {
2030 .hw = {
2031 .clk = &i2c3_ick,
2032 },
2033 .ops = &clkhwops_iclk_wait,
2034 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2035 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
2036 .clkdm_name = "core_l4_clkdm",
2037};
2038
2039DEFINE_STRUCT_CLK(i2c3_ick, aes2_ick_parent_names, aes2_ick_ops);
2040
2041static struct clk icr_ick;
2042
2043static struct clk_hw_omap icr_ick_hw = {
2044 .hw = {
2045 .clk = &icr_ick,
2046 },
2047 .ops = &clkhwops_iclk_wait,
2048 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2049 .enable_bit = OMAP3430_EN_ICR_SHIFT,
2050 .clkdm_name = "core_l4_clkdm",
2051};
2052
2053DEFINE_STRUCT_CLK(icr_ick, aes2_ick_parent_names, aes2_ick_ops);
2054
2055static struct clk iva2_ck;
2056
2057static const char *iva2_ck_parent_names[] = {
2058 "dpll2_m2_ck",
2059};
2060
2061static struct clk_hw_omap iva2_ck_hw = {
2062 .hw = {
2063 .clk = &iva2_ck,
2064 },
2065 .ops = &clkhwops_wait,
2066 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
2067 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
2068 .clkdm_name = "iva2_clkdm",
2069};
2070
2071DEFINE_STRUCT_CLK(iva2_ck, iva2_ck_parent_names, aes2_ick_ops);
2072
2073static struct clk mad2d_ick;
2074
2075static struct clk_hw_omap mad2d_ick_hw = {
2076 .hw = {
2077 .clk = &mad2d_ick,
2078 },
2079 .ops = &clkhwops_iclk_wait,
2080 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2081 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
2082 .clkdm_name = "d2d_clkdm",
2083};
2084
2085DEFINE_STRUCT_CLK(mad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
2086
2087static struct clk mailboxes_ick;
2088
2089static struct clk_hw_omap mailboxes_ick_hw = {
2090 .hw = {
2091 .clk = &mailboxes_ick,
2092 },
2093 .ops = &clkhwops_iclk_wait,
2094 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2095 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2096 .clkdm_name = "core_l4_clkdm",
2097};
2098
2099DEFINE_STRUCT_CLK(mailboxes_ick, aes2_ick_parent_names, aes2_ick_ops);
2100
2101static const struct clksel_rate common_mcbsp_96m_rates[] = {
2102 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2103 { .div = 0 }
2104};
2105
2106static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
2107 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2108 { .div = 0 }
2109};
2110
2111static const struct clksel mcbsp_15_clksel[] = {
2112 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2113 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2114 { .parent = NULL },
2115};
2116
2117static const char *mcbsp1_fck_parent_names[] = {
2118 "core_96m_fck", "mcbsp_clks",
2119};
2120
2121DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_15_clksel,
2122 OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2123 OMAP2_MCBSP1_CLKS_MASK,
2124 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2125 OMAP3430_EN_MCBSP1_SHIFT, &clkhwops_wait,
2126 mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2127
2128static struct clk mcbsp1_ick;
2129
2130static struct clk_hw_omap mcbsp1_ick_hw = {
2131 .hw = {
2132 .clk = &mcbsp1_ick,
2133 },
2134 .ops = &clkhwops_iclk_wait,
2135 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2136 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2137 .clkdm_name = "core_l4_clkdm",
2138};
2139
2140DEFINE_STRUCT_CLK(mcbsp1_ick, aes2_ick_parent_names, aes2_ick_ops);
2141
2142static struct clk per_96m_fck;
2143
2144DEFINE_STRUCT_CLK_HW_OMAP(per_96m_fck, "per_clkdm");
2145DEFINE_STRUCT_CLK(per_96m_fck, cm_96m_fck_parent_names, core_l4_ick_ops);
2146
2147static const struct clksel mcbsp_234_clksel[] = {
2148 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2149 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2150 { .parent = NULL },
2151};
2152
2153static const char *mcbsp2_fck_parent_names[] = {
2154 "per_96m_fck", "mcbsp_clks",
2155};
2156
2157DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "per_clkdm", mcbsp_234_clksel,
2158 OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2159 OMAP2_MCBSP2_CLKS_MASK,
2160 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2161 OMAP3430_EN_MCBSP2_SHIFT, &clkhwops_wait,
2162 mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2163
2164static struct clk mcbsp2_ick;
2165
2166static struct clk_hw_omap mcbsp2_ick_hw = {
2167 .hw = {
2168 .clk = &mcbsp2_ick,
2169 },
2170 .ops = &clkhwops_iclk_wait,
2171 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2172 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2173 .clkdm_name = "per_clkdm",
2174};
2175
2176DEFINE_STRUCT_CLK(mcbsp2_ick, gpio2_ick_parent_names, aes2_ick_ops);
2177
2178DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "per_clkdm", mcbsp_234_clksel,
2179 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2180 OMAP2_MCBSP3_CLKS_MASK,
2181 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2182 OMAP3430_EN_MCBSP3_SHIFT, &clkhwops_wait,
2183 mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2184
2185static struct clk mcbsp3_ick;
2186
2187static struct clk_hw_omap mcbsp3_ick_hw = {
2188 .hw = {
2189 .clk = &mcbsp3_ick,
2190 },
2191 .ops = &clkhwops_iclk_wait,
2192 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2193 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2194 .clkdm_name = "per_clkdm",
2195};
2196
2197DEFINE_STRUCT_CLK(mcbsp3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2198
2199DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "per_clkdm", mcbsp_234_clksel,
2200 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2201 OMAP2_MCBSP4_CLKS_MASK,
2202 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2203 OMAP3430_EN_MCBSP4_SHIFT, &clkhwops_wait,
2204 mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2205
2206static struct clk mcbsp4_ick;
2207
2208static struct clk_hw_omap mcbsp4_ick_hw = {
2209 .hw = {
2210 .clk = &mcbsp4_ick,
2211 },
2212 .ops = &clkhwops_iclk_wait,
2213 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2214 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2215 .clkdm_name = "per_clkdm",
2216};
2217
2218DEFINE_STRUCT_CLK(mcbsp4_ick, gpio2_ick_parent_names, aes2_ick_ops);
2219
2220DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_15_clksel,
2221 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2222 OMAP2_MCBSP5_CLKS_MASK,
2223 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2224 OMAP3430_EN_MCBSP5_SHIFT, &clkhwops_wait,
2225 mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2226
2227static struct clk mcbsp5_ick;
2228
2229static struct clk_hw_omap mcbsp5_ick_hw = {
2230 .hw = {
2231 .clk = &mcbsp5_ick,
2232 },
2233 .ops = &clkhwops_iclk_wait,
2234 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2235 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2236 .clkdm_name = "core_l4_clkdm",
2237};
2238
2239DEFINE_STRUCT_CLK(mcbsp5_ick, aes2_ick_parent_names, aes2_ick_ops);
2240
2241static struct clk mcspi1_fck;
2242
2243static struct clk_hw_omap mcspi1_fck_hw = {
2244 .hw = {
2245 .clk = &mcspi1_fck,
2246 },
2247 .ops = &clkhwops_wait,
2248 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2249 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
2250 .clkdm_name = "core_l4_clkdm",
2251};
2252
2253DEFINE_STRUCT_CLK(mcspi1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2254
2255static struct clk mcspi1_ick;
2256
2257static struct clk_hw_omap mcspi1_ick_hw = {
2258 .hw = {
2259 .clk = &mcspi1_ick,
2260 },
2261 .ops = &clkhwops_iclk_wait,
2262 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2263 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
2264 .clkdm_name = "core_l4_clkdm",
2265};
2266
2267DEFINE_STRUCT_CLK(mcspi1_ick, aes2_ick_parent_names, aes2_ick_ops);
2268
2269static struct clk mcspi2_fck;
2270
2271static struct clk_hw_omap mcspi2_fck_hw = {
2272 .hw = {
2273 .clk = &mcspi2_fck,
2274 },
2275 .ops = &clkhwops_wait,
2276 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2277 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
2278 .clkdm_name = "core_l4_clkdm",
2279};
2280
2281DEFINE_STRUCT_CLK(mcspi2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2282
2283static struct clk mcspi2_ick;
2284
2285static struct clk_hw_omap mcspi2_ick_hw = {
2286 .hw = {
2287 .clk = &mcspi2_ick,
2288 },
2289 .ops = &clkhwops_iclk_wait,
2290 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2291 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
2292 .clkdm_name = "core_l4_clkdm",
2293};
2294
2295DEFINE_STRUCT_CLK(mcspi2_ick, aes2_ick_parent_names, aes2_ick_ops);
2296
2297static struct clk mcspi3_fck;
2298
2299static struct clk_hw_omap mcspi3_fck_hw = {
2300 .hw = {
2301 .clk = &mcspi3_fck,
2302 },
2303 .ops = &clkhwops_wait,
2304 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2305 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
2306 .clkdm_name = "core_l4_clkdm",
2307};
2308
2309DEFINE_STRUCT_CLK(mcspi3_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2310
2311static struct clk mcspi3_ick;
2312
2313static struct clk_hw_omap mcspi3_ick_hw = {
2314 .hw = {
2315 .clk = &mcspi3_ick,
2316 },
2317 .ops = &clkhwops_iclk_wait,
2318 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2319 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
2320 .clkdm_name = "core_l4_clkdm",
2321};
2322
2323DEFINE_STRUCT_CLK(mcspi3_ick, aes2_ick_parent_names, aes2_ick_ops);
2324
2325static struct clk mcspi4_fck;
2326
2327static struct clk_hw_omap mcspi4_fck_hw = {
2328 .hw = {
2329 .clk = &mcspi4_fck,
2330 },
2331 .ops = &clkhwops_wait,
2332 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2333 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
2334 .clkdm_name = "core_l4_clkdm",
2335};
2336
2337DEFINE_STRUCT_CLK(mcspi4_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2338
2339static struct clk mcspi4_ick;
2340
2341static struct clk_hw_omap mcspi4_ick_hw = {
2342 .hw = {
2343 .clk = &mcspi4_ick,
2344 },
2345 .ops = &clkhwops_iclk_wait,
2346 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2347 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
2348 .clkdm_name = "core_l4_clkdm",
2349};
2350
2351DEFINE_STRUCT_CLK(mcspi4_ick, aes2_ick_parent_names, aes2_ick_ops);
2352
2353static struct clk mmchs1_fck;
2354
2355static struct clk_hw_omap mmchs1_fck_hw = {
2356 .hw = {
2357 .clk = &mmchs1_fck,
2358 },
2359 .ops = &clkhwops_wait,
2360 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2361 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
2362 .clkdm_name = "core_l4_clkdm",
2363};
2364
2365DEFINE_STRUCT_CLK(mmchs1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2366
2367static struct clk mmchs1_ick;
2368
2369static struct clk_hw_omap mmchs1_ick_hw = {
2370 .hw = {
2371 .clk = &mmchs1_ick,
2372 },
2373 .ops = &clkhwops_iclk_wait,
2374 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2375 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
2376 .clkdm_name = "core_l4_clkdm",
2377};
2378
2379DEFINE_STRUCT_CLK(mmchs1_ick, aes2_ick_parent_names, aes2_ick_ops);
2380
2381static struct clk mmchs2_fck;
2382
2383static struct clk_hw_omap mmchs2_fck_hw = {
2384 .hw = {
2385 .clk = &mmchs2_fck,
2386 },
2387 .ops = &clkhwops_wait,
2388 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2389 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
2390 .clkdm_name = "core_l4_clkdm",
2391};
2392
2393DEFINE_STRUCT_CLK(mmchs2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2394
2395static struct clk mmchs2_ick;
2396
2397static struct clk_hw_omap mmchs2_ick_hw = {
2398 .hw = {
2399 .clk = &mmchs2_ick,
2400 },
2401 .ops = &clkhwops_iclk_wait,
2402 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2403 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
2404 .clkdm_name = "core_l4_clkdm",
2405};
2406
2407DEFINE_STRUCT_CLK(mmchs2_ick, aes2_ick_parent_names, aes2_ick_ops);
2408
2409static struct clk mmchs3_fck;
2410
2411static struct clk_hw_omap mmchs3_fck_hw = {
2412 .hw = {
2413 .clk = &mmchs3_fck,
2414 },
2415 .ops = &clkhwops_wait,
2416 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2417 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
2418 .clkdm_name = "core_l4_clkdm",
2419};
2420
2421DEFINE_STRUCT_CLK(mmchs3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2422
2423static struct clk mmchs3_ick;
2424
2425static struct clk_hw_omap mmchs3_ick_hw = {
2426 .hw = {
2427 .clk = &mmchs3_ick,
2428 },
2429 .ops = &clkhwops_iclk_wait,
2430 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2431 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
2432 .clkdm_name = "core_l4_clkdm",
2433};
2434
2435DEFINE_STRUCT_CLK(mmchs3_ick, aes2_ick_parent_names, aes2_ick_ops);
2436
2437static struct clk modem_fck;
2438
2439static struct clk_hw_omap modem_fck_hw = {
2440 .hw = {
2441 .clk = &modem_fck,
2442 },
2443 .ops = &clkhwops_iclk_wait,
2444 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2445 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
2446 .clkdm_name = "d2d_clkdm",
2447};
2448
2449DEFINE_STRUCT_CLK(modem_fck, cpefuse_fck_parent_names, aes2_ick_ops);
2450
2451static struct clk mspro_fck;
2452
2453static struct clk_hw_omap mspro_fck_hw = {
2454 .hw = {
2455 .clk = &mspro_fck,
2456 },
2457 .ops = &clkhwops_wait,
2458 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2459 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
2460 .clkdm_name = "core_l4_clkdm",
2461};
2462
2463DEFINE_STRUCT_CLK(mspro_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2464
2465static struct clk mspro_ick;
2466
2467static struct clk_hw_omap mspro_ick_hw = {
2468 .hw = {
2469 .clk = &mspro_ick,
2470 },
2471 .ops = &clkhwops_iclk_wait,
2472 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2473 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
2474 .clkdm_name = "core_l4_clkdm",
2475};
2476
2477DEFINE_STRUCT_CLK(mspro_ick, aes2_ick_parent_names, aes2_ick_ops);
2478
2479static struct clk omap_192m_alwon_fck;
2480
2481DEFINE_STRUCT_CLK_HW_OMAP(omap_192m_alwon_fck, NULL);
2482DEFINE_STRUCT_CLK(omap_192m_alwon_fck, omap_96m_alwon_fck_parent_names,
2483 core_ck_ops);
2484
2485static struct clk omap_32ksync_ick;
2486
2487static struct clk_hw_omap omap_32ksync_ick_hw = {
2488 .hw = {
2489 .clk = &omap_32ksync_ick,
2490 },
2491 .ops = &clkhwops_iclk_wait,
2492 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2493 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2494 .clkdm_name = "wkup_clkdm",
2495};
2496
2497DEFINE_STRUCT_CLK(omap_32ksync_ick, gpio1_ick_parent_names, aes2_ick_ops);
2498
2499static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
2500 { .div = 1, .val = 1, .flags = RATE_IN_36XX },
2501 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
2502 { .div = 0 }
2503};
2504
2505static const struct clksel omap_96m_alwon_fck_clksel[] = {
2506 { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
2507 { .parent = NULL }
2508};
2509
2510static struct clk omap_96m_alwon_fck_3630;
2511
2512static const char *omap_96m_alwon_fck_3630_parent_names[] = {
2513 "omap_192m_alwon_fck",
2514};
2515
2516static const struct clk_ops omap_96m_alwon_fck_3630_ops = {
2517 .set_rate = &omap2_clksel_set_rate,
2518 .recalc_rate = &omap2_clksel_recalc,
2519 .round_rate = &omap2_clksel_round_rate,
2520};
2521
2522static struct clk_hw_omap omap_96m_alwon_fck_3630_hw = {
2523 .hw = {
2524 .clk = &omap_96m_alwon_fck_3630,
2525 },
2526 .clksel = omap_96m_alwon_fck_clksel,
2527 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2528 .clksel_mask = OMAP3630_CLKSEL_96M_MASK,
2529};
2530
2531static struct clk_core omap_96m_alwon_fck_3630_core = {
2532 .name = "omap_96m_alwon_fck",
2533 .hw = &omap_96m_alwon_fck_3630_hw.hw,
2534 .parent_names = omap_96m_alwon_fck_3630_parent_names,
2535 .num_parents = ARRAY_SIZE(omap_96m_alwon_fck_3630_parent_names),
2536 .ops = &omap_96m_alwon_fck_3630_ops,
2537};
2538
2539static struct clk omap_96m_alwon_fck_3630 = {
2540 .core = &omap_96m_alwon_fck_3630_core,
2541};
2542
2543static struct clk omapctrl_ick;
2544
2545static struct clk_hw_omap omapctrl_ick_hw = {
2546 .hw = {
2547 .clk = &omapctrl_ick,
2548 },
2549 .ops = &clkhwops_iclk_wait,
2550 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2551 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2552 .flags = ENABLE_ON_INIT,
2553 .clkdm_name = "core_l4_clkdm",
2554};
2555
2556DEFINE_STRUCT_CLK(omapctrl_ick, aes2_ick_parent_names, aes2_ick_ops);
2557
2558DEFINE_CLK_DIVIDER(pclk_fck, "emu_src_ck", &emu_src_ck_core, 0x0,
2559 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2560 OMAP3430_CLKSEL_PCLK_SHIFT, OMAP3430_CLKSEL_PCLK_WIDTH,
2561 CLK_DIVIDER_ONE_BASED, NULL);
2562
2563DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck_core, 0x0,
2564 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2565 OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH,
2566 CLK_DIVIDER_ONE_BASED, NULL);
2567
2568static struct clk per_48m_fck;
2569
2570DEFINE_STRUCT_CLK_HW_OMAP(per_48m_fck, "per_clkdm");
2571DEFINE_STRUCT_CLK(per_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
2572
2573static struct clk security_l3_ick;
2574
2575DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick, NULL);
2576DEFINE_STRUCT_CLK(security_l3_ick, core_l3_ick_parent_names, core_ck_ops);
2577
2578static struct clk pka_ick;
2579
2580static const char *pka_ick_parent_names[] = {
2581 "security_l3_ick",
2582};
2583
2584static struct clk_hw_omap pka_ick_hw = {
2585 .hw = {
2586 .clk = &pka_ick,
2587 },
2588 .ops = &clkhwops_iclk_wait,
2589 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2590 .enable_bit = OMAP3430_EN_PKA_SHIFT,
2591};
2592
2593DEFINE_STRUCT_CLK(pka_ick, pka_ick_parent_names, aes1_ick_ops);
2594
2595DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick_core, 0x0,
2596 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2597 OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH,
2598 CLK_DIVIDER_ONE_BASED, NULL);
2599
2600static struct clk rng_ick;
2601
2602static struct clk_hw_omap rng_ick_hw = {
2603 .hw = {
2604 .clk = &rng_ick,
2605 },
2606 .ops = &clkhwops_iclk_wait,
2607 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2608 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2609};
2610
2611DEFINE_STRUCT_CLK(rng_ick, aes1_ick_parent_names, aes1_ick_ops);
2612
2613static struct clk sad2d_ick;
2614
2615static struct clk_hw_omap sad2d_ick_hw = {
2616 .hw = {
2617 .clk = &sad2d_ick,
2618 },
2619 .ops = &clkhwops_iclk_wait,
2620 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2621 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
2622 .clkdm_name = "d2d_clkdm",
2623};
2624
2625DEFINE_STRUCT_CLK(sad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
2626
2627static struct clk sdrc_ick;
2628
2629static struct clk_hw_omap sdrc_ick_hw = {
2630 .hw = {
2631 .clk = &sdrc_ick,
2632 },
2633 .ops = &clkhwops_wait,
2634 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2635 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
2636 .flags = ENABLE_ON_INIT,
2637 .clkdm_name = "core_l3_clkdm",
2638};
2639
2640DEFINE_STRUCT_CLK(sdrc_ick, ipss_ick_parent_names, aes2_ick_ops);
2641
2642static const struct clksel_rate sgx_core_rates[] = {
2643 { .div = 2, .val = 5, .flags = RATE_IN_36XX },
2644 { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
2645 { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
2646 { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
2647 { .div = 0 }
2648};
2649
2650static const struct clksel_rate sgx_96m_rates[] = {
2651 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2652 { .div = 0 }
2653};
2654
2655static const struct clksel_rate sgx_192m_rates[] = {
2656 { .div = 1, .val = 4, .flags = RATE_IN_36XX },
2657 { .div = 0 }
2658};
2659
2660static const struct clksel_rate sgx_corex2_rates[] = {
2661 { .div = 3, .val = 6, .flags = RATE_IN_36XX },
2662 { .div = 5, .val = 7, .flags = RATE_IN_36XX },
2663 { .div = 0 }
2664};
2665
2666static const struct clksel sgx_clksel[] = {
2667 { .parent = &core_ck, .rates = sgx_core_rates },
2668 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
2669 { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
2670 { .parent = &corex2_fck, .rates = sgx_corex2_rates },
2671 { .parent = NULL },
2672};
2673
2674static const char *sgx_fck_parent_names[] = {
2675 "core_ck", "cm_96m_fck", "omap_192m_alwon_fck", "corex2_fck",
2676};
2677
2678static struct clk sgx_fck;
2679
2680static const struct clk_ops sgx_fck_ops = {
2681 .init = &omap2_init_clk_clkdm,
2682 .enable = &omap2_dflt_clk_enable,
2683 .disable = &omap2_dflt_clk_disable,
2684 .is_enabled = &omap2_dflt_clk_is_enabled,
2685 .recalc_rate = &omap2_clksel_recalc,
2686 .set_rate = &omap2_clksel_set_rate,
2687 .round_rate = &omap2_clksel_round_rate,
2688 .get_parent = &omap2_clksel_find_parent_index,
2689 .set_parent = &omap2_clksel_set_parent,
2690};
2691
2692DEFINE_CLK_OMAP_MUX_GATE(sgx_fck, "sgx_clkdm", sgx_clksel,
2693 OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
2694 OMAP3430ES2_CLKSEL_SGX_MASK,
2695 OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
2696 OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
2697 &clkhwops_wait, sgx_fck_parent_names, sgx_fck_ops);
2698
2699static struct clk sgx_ick;
2700
2701static struct clk_hw_omap sgx_ick_hw = {
2702 .hw = {
2703 .clk = &sgx_ick,
2704 },
2705 .ops = &clkhwops_wait,
2706 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
2707 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
2708 .clkdm_name = "sgx_clkdm",
2709};
2710
2711DEFINE_STRUCT_CLK(sgx_ick, core_l3_ick_parent_names, aes2_ick_ops);
2712
2713static struct clk sha11_ick;
2714
2715static struct clk_hw_omap sha11_ick_hw = {
2716 .hw = {
2717 .clk = &sha11_ick,
2718 },
2719 .ops = &clkhwops_iclk_wait,
2720 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2721 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2722};
2723
2724DEFINE_STRUCT_CLK(sha11_ick, aes1_ick_parent_names, aes1_ick_ops);
2725
2726static struct clk sha12_ick;
2727
2728static struct clk_hw_omap sha12_ick_hw = {
2729 .hw = {
2730 .clk = &sha12_ick,
2731 },
2732 .ops = &clkhwops_iclk_wait,
2733 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2734 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
2735 .clkdm_name = "core_l4_clkdm",
2736};
2737
2738DEFINE_STRUCT_CLK(sha12_ick, aes2_ick_parent_names, aes2_ick_ops);
2739
2740static struct clk sr1_fck;
2741
2742static struct clk_hw_omap sr1_fck_hw = {
2743 .hw = {
2744 .clk = &sr1_fck,
2745 },
2746 .ops = &clkhwops_wait,
2747 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2748 .enable_bit = OMAP3430_EN_SR1_SHIFT,
2749 .clkdm_name = "wkup_clkdm",
2750};
2751
2752DEFINE_STRUCT_CLK(sr1_fck, cpefuse_fck_parent_names, aes2_ick_ops);
2753
2754static struct clk sr2_fck;
2755
2756static struct clk_hw_omap sr2_fck_hw = {
2757 .hw = {
2758 .clk = &sr2_fck,
2759 },
2760 .ops = &clkhwops_wait,
2761 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2762 .enable_bit = OMAP3430_EN_SR2_SHIFT,
2763 .clkdm_name = "wkup_clkdm",
2764};
2765
2766DEFINE_STRUCT_CLK(sr2_fck, cpefuse_fck_parent_names, aes2_ick_ops);
2767
2768static struct clk sr_l4_ick;
2769
2770DEFINE_STRUCT_CLK_HW_OMAP(sr_l4_ick, "core_l4_clkdm");
2771DEFINE_STRUCT_CLK(sr_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2772
2773static struct clk ssi_l4_ick;
2774
2775DEFINE_STRUCT_CLK_HW_OMAP(ssi_l4_ick, "core_l4_clkdm");
2776DEFINE_STRUCT_CLK(ssi_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2777
2778static struct clk ssi_ick_3430es1;
2779
2780static const char *ssi_ick_3430es1_parent_names[] = {
2781 "ssi_l4_ick",
2782};
2783
2784static struct clk_hw_omap ssi_ick_3430es1_hw = {
2785 .hw = {
2786 .clk = &ssi_ick_3430es1,
2787 },
2788 .ops = &clkhwops_iclk,
2789 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2790 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2791 .clkdm_name = "core_l4_clkdm",
2792};
2793
2794DEFINE_STRUCT_CLK(ssi_ick_3430es1, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2795
2796static struct clk ssi_ick_3430es2;
2797
2798static struct clk_hw_omap ssi_ick_3430es2_hw = {
2799 .hw = {
2800 .clk = &ssi_ick_3430es2,
2801 },
2802 .ops = &clkhwops_omap3430es2_iclk_ssi_wait,
2803 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2804 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2805 .clkdm_name = "core_l4_clkdm",
2806};
2807
2808DEFINE_STRUCT_CLK(ssi_ick_3430es2, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2809
2810static const struct clksel_rate ssi_ssr_corex2_rates[] = {
2811 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2812 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2813 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2814 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2815 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2816 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
2817 { .div = 0 }
2818};
2819
2820static const struct clksel ssi_ssr_clksel[] = {
2821 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
2822 { .parent = NULL },
2823};
2824
2825static const char *ssi_ssr_fck_3430es1_parent_names[] = {
2826 "corex2_fck",
2827};
2828
2829static const struct clk_ops ssi_ssr_fck_3430es1_ops = {
2830 .init = &omap2_init_clk_clkdm,
2831 .enable = &omap2_dflt_clk_enable,
2832 .disable = &omap2_dflt_clk_disable,
2833 .is_enabled = &omap2_dflt_clk_is_enabled,
2834 .recalc_rate = &omap2_clksel_recalc,
2835 .set_rate = &omap2_clksel_set_rate,
2836 .round_rate = &omap2_clksel_round_rate,
2837};
2838
2839DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es1, "core_l4_clkdm",
2840 ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2841 OMAP3430_CLKSEL_SSI_MASK,
2842 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2843 OMAP3430_EN_SSI_SHIFT,
2844 NULL, ssi_ssr_fck_3430es1_parent_names,
2845 ssi_ssr_fck_3430es1_ops);
2846
2847DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es2, "core_l4_clkdm",
2848 ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2849 OMAP3430_CLKSEL_SSI_MASK,
2850 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2851 OMAP3430_EN_SSI_SHIFT,
2852 NULL, ssi_ssr_fck_3430es1_parent_names,
2853 ssi_ssr_fck_3430es1_ops);
2854
2855DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1, "ssi_ssr_fck_3430es1",
2856 &ssi_ssr_fck_3430es1_core, 0x0, 1, 2);
2857
2858DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2, "ssi_ssr_fck_3430es2",
2859 &ssi_ssr_fck_3430es2_core, 0x0, 1, 2);
2860
2861static struct clk sys_clkout1;
2862
2863static const char *sys_clkout1_parent_names[] = {
2864 "osc_sys_ck",
2865};
2866
2867static struct clk_hw_omap sys_clkout1_hw = {
2868 .hw = {
2869 .clk = &sys_clkout1,
2870 },
2871 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
2872 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
2873};
2874
2875DEFINE_STRUCT_CLK(sys_clkout1, sys_clkout1_parent_names, aes1_ick_ops);
2876
2877DEFINE_CLK_DIVIDER(sys_clkout2, "clkout2_src_ck", &clkout2_src_ck_core, 0x0,
2878 OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_DIV_SHIFT,
2879 OMAP3430_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
2880
2881DEFINE_CLK_MUX(traceclk_src_fck, emu_src_ck_parent_names, NULL, 0x0,
2882 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2883 OMAP3430_TRACE_MUX_CTRL_SHIFT, OMAP3430_TRACE_MUX_CTRL_WIDTH,
2884 0x0, NULL);
2885
2886DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck_core,
2887 0x0,
2888 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2889 OMAP3430_CLKSEL_TRACECLK_SHIFT,
2890 OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
2891
2892static struct clk ts_fck;
2893
2894static struct clk_hw_omap ts_fck_hw = {
2895 .hw = {
2896 .clk = &ts_fck,
2897 },
2898 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
2899 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
2900 .clkdm_name = "core_l4_clkdm",
2901};
2902
2903DEFINE_STRUCT_CLK(ts_fck, wkup_32k_fck_parent_names, aes2_ick_ops);
2904
2905static struct clk uart1_fck;
2906
2907static struct clk_hw_omap uart1_fck_hw = {
2908 .hw = {
2909 .clk = &uart1_fck,
2910 },
2911 .ops = &clkhwops_wait,
2912 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2913 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2914 .clkdm_name = "core_l4_clkdm",
2915};
2916
2917DEFINE_STRUCT_CLK(uart1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2918
2919static struct clk uart1_ick;
2920
2921static struct clk_hw_omap uart1_ick_hw = {
2922 .hw = {
2923 .clk = &uart1_ick,
2924 },
2925 .ops = &clkhwops_iclk_wait,
2926 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2927 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2928 .clkdm_name = "core_l4_clkdm",
2929};
2930
2931DEFINE_STRUCT_CLK(uart1_ick, aes2_ick_parent_names, aes2_ick_ops);
2932
2933static struct clk uart2_fck;
2934
2935static struct clk_hw_omap uart2_fck_hw = {
2936 .hw = {
2937 .clk = &uart2_fck,
2938 },
2939 .ops = &clkhwops_wait,
2940 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2941 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2942 .clkdm_name = "core_l4_clkdm",
2943};
2944
2945DEFINE_STRUCT_CLK(uart2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2946
2947static struct clk uart2_ick;
2948
2949static struct clk_hw_omap uart2_ick_hw = {
2950 .hw = {
2951 .clk = &uart2_ick,
2952 },
2953 .ops = &clkhwops_iclk_wait,
2954 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2955 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2956 .clkdm_name = "core_l4_clkdm",
2957};
2958
2959DEFINE_STRUCT_CLK(uart2_ick, aes2_ick_parent_names, aes2_ick_ops);
2960
2961static struct clk uart3_fck;
2962
2963static const char *uart3_fck_parent_names[] = {
2964 "per_48m_fck",
2965};
2966
2967static struct clk_hw_omap uart3_fck_hw = {
2968 .hw = {
2969 .clk = &uart3_fck,
2970 },
2971 .ops = &clkhwops_wait,
2972 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2973 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2974 .clkdm_name = "per_clkdm",
2975};
2976
2977DEFINE_STRUCT_CLK(uart3_fck, uart3_fck_parent_names, aes2_ick_ops);
2978
2979static struct clk uart3_ick;
2980
2981static struct clk_hw_omap uart3_ick_hw = {
2982 .hw = {
2983 .clk = &uart3_ick,
2984 },
2985 .ops = &clkhwops_iclk_wait,
2986 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2987 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2988 .clkdm_name = "per_clkdm",
2989};
2990
2991DEFINE_STRUCT_CLK(uart3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2992
2993static struct clk uart4_fck;
2994
2995static struct clk_hw_omap uart4_fck_hw = {
2996 .hw = {
2997 .clk = &uart4_fck,
2998 },
2999 .ops = &clkhwops_wait,
3000 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
3001 .enable_bit = OMAP3630_EN_UART4_SHIFT,
3002 .clkdm_name = "per_clkdm",
3003};
3004
3005DEFINE_STRUCT_CLK(uart4_fck, uart3_fck_parent_names, aes2_ick_ops);
3006
3007static struct clk uart4_fck_am35xx;
3008
3009static struct clk_hw_omap uart4_fck_am35xx_hw = {
3010 .hw = {
3011 .clk = &uart4_fck_am35xx,
3012 },
3013 .ops = &clkhwops_wait,
3014 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
3015 .enable_bit = AM35XX_EN_UART4_SHIFT,
3016 .clkdm_name = "core_l4_clkdm",
3017};
3018
3019DEFINE_STRUCT_CLK(uart4_fck_am35xx, fshostusb_fck_parent_names, aes2_ick_ops);
3020
3021static struct clk uart4_ick;
3022
3023static struct clk_hw_omap uart4_ick_hw = {
3024 .hw = {
3025 .clk = &uart4_ick,
3026 },
3027 .ops = &clkhwops_iclk_wait,
3028 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
3029 .enable_bit = OMAP3630_EN_UART4_SHIFT,
3030 .clkdm_name = "per_clkdm",
3031};
3032
3033DEFINE_STRUCT_CLK(uart4_ick, gpio2_ick_parent_names, aes2_ick_ops);
3034
3035static struct clk uart4_ick_am35xx;
3036
3037static struct clk_hw_omap uart4_ick_am35xx_hw = {
3038 .hw = {
3039 .clk = &uart4_ick_am35xx,
3040 },
3041 .ops = &clkhwops_iclk_wait,
3042 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3043 .enable_bit = AM35XX_EN_UART4_SHIFT,
3044 .clkdm_name = "core_l4_clkdm",
3045};
3046
3047DEFINE_STRUCT_CLK(uart4_ick_am35xx, aes2_ick_parent_names, aes2_ick_ops);
3048
3049static const struct clksel_rate div2_rates[] = {
3050 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3051 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3052 { .div = 0 }
3053};
3054
3055static const struct clksel usb_l4_clksel[] = {
3056 { .parent = &l4_ick, .rates = div2_rates },
3057 { .parent = NULL },
3058};
3059
3060static const char *usb_l4_ick_parent_names[] = {
3061 "l4_ick",
3062};
3063
3064DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_clksel,
3065 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
3066 OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
3067 OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3068 OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
3069 &clkhwops_iclk_wait, usb_l4_ick_parent_names,
3070 ssi_ssr_fck_3430es1_ops);
3071
3072static struct clk usbhost_120m_fck;
3073
3074static const char *usbhost_120m_fck_parent_names[] = {
3075 "dpll5_m2_ck",
3076};
3077
3078static struct clk_hw_omap usbhost_120m_fck_hw = {
3079 .hw = {
3080 .clk = &usbhost_120m_fck,
3081 },
3082 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
3083 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
3084 .clkdm_name = "usbhost_clkdm",
3085};
3086
3087DEFINE_STRUCT_CLK(usbhost_120m_fck, usbhost_120m_fck_parent_names,
3088 aes2_ick_ops);
3089
3090static struct clk usbhost_48m_fck;
3091
3092static struct clk_hw_omap usbhost_48m_fck_hw = {
3093 .hw = {
3094 .clk = &usbhost_48m_fck,
3095 },
3096 .ops = &clkhwops_omap3430es2_dss_usbhost_wait,
3097 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
3098 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
3099 .clkdm_name = "usbhost_clkdm",
3100};
3101
3102DEFINE_STRUCT_CLK(usbhost_48m_fck, core_48m_fck_parent_names, aes2_ick_ops);
3103
3104static struct clk usbhost_ick;
3105
3106static struct clk_hw_omap usbhost_ick_hw = {
3107 .hw = {
3108 .clk = &usbhost_ick,
3109 },
3110 .ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
3111 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
3112 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
3113 .clkdm_name = "usbhost_clkdm",
3114};
3115
3116DEFINE_STRUCT_CLK(usbhost_ick, security_l4_ick2_parent_names, aes2_ick_ops);
3117
3118static struct clk usbtll_fck;
3119
3120static struct clk_hw_omap usbtll_fck_hw = {
3121 .hw = {
3122 .clk = &usbtll_fck,
3123 },
3124 .ops = &clkhwops_wait,
3125 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
3126 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3127 .clkdm_name = "core_l4_clkdm",
3128};
3129
3130DEFINE_STRUCT_CLK(usbtll_fck, usbhost_120m_fck_parent_names, aes2_ick_ops);
3131
3132static struct clk usbtll_ick;
3133
3134static struct clk_hw_omap usbtll_ick_hw = {
3135 .hw = {
3136 .clk = &usbtll_ick,
3137 },
3138 .ops = &clkhwops_iclk_wait,
3139 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
3140 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3141 .clkdm_name = "core_l4_clkdm",
3142};
3143
3144DEFINE_STRUCT_CLK(usbtll_ick, aes2_ick_parent_names, aes2_ick_ops);
3145
3146static const struct clksel_rate usim_96m_rates[] = {
3147 { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
3148 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3149 { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
3150 { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
3151 { .div = 0 }
3152};
3153
3154static const struct clksel_rate usim_120m_rates[] = {
3155 { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
3156 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
3157 { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
3158 { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
3159 { .div = 0 }
3160};
3161
3162static const struct clksel usim_clksel[] = {
3163 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
3164 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
3165 { .parent = &sys_ck, .rates = div2_rates },
3166 { .parent = NULL },
3167};
3168
3169static const char *usim_fck_parent_names[] = {
3170 "omap_96m_fck", "dpll5_m2_ck", "sys_ck",
3171};
3172
3173static struct clk usim_fck;
3174
3175static const struct clk_ops usim_fck_ops = {
3176 .enable = &omap2_dflt_clk_enable,
3177 .disable = &omap2_dflt_clk_disable,
3178 .is_enabled = &omap2_dflt_clk_is_enabled,
3179 .recalc_rate = &omap2_clksel_recalc,
3180 .get_parent = &omap2_clksel_find_parent_index,
3181 .set_parent = &omap2_clksel_set_parent,
3182};
3183
3184DEFINE_CLK_OMAP_MUX_GATE(usim_fck, NULL, usim_clksel,
3185 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
3186 OMAP3430ES2_CLKSEL_USIMOCP_MASK,
3187 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3188 OMAP3430ES2_EN_USIMOCP_SHIFT, &clkhwops_wait,
3189 usim_fck_parent_names, usim_fck_ops);
3190
3191static struct clk usim_ick;
3192
3193static struct clk_hw_omap usim_ick_hw = {
3194 .hw = {
3195 .clk = &usim_ick,
3196 },
3197 .ops = &clkhwops_iclk_wait,
3198 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3199 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
3200 .clkdm_name = "wkup_clkdm",
3201};
3202
3203DEFINE_STRUCT_CLK(usim_ick, gpio1_ick_parent_names, aes2_ick_ops);
3204
3205static struct clk vpfe_fck;
3206
3207static const char *vpfe_fck_parent_names[] = {
3208 "pclk_ck",
3209};
3210
3211static struct clk_hw_omap vpfe_fck_hw = {
3212 .hw = {
3213 .clk = &vpfe_fck,
3214 },
3215 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3216 .enable_bit = AM35XX_VPFE_FCLK_SHIFT,
3217};
3218
3219DEFINE_STRUCT_CLK(vpfe_fck, vpfe_fck_parent_names, aes1_ick_ops);
3220
3221static struct clk vpfe_ick;
3222
3223static struct clk_hw_omap vpfe_ick_hw = {
3224 .hw = {
3225 .clk = &vpfe_ick,
3226 },
3227 .ops = &clkhwops_am35xx_ipss_module_wait,
3228 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3229 .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3230 .clkdm_name = "core_l3_clkdm",
3231};
3232
3233DEFINE_STRUCT_CLK(vpfe_ick, emac_ick_parent_names, aes2_ick_ops);
3234
3235static struct clk wdt1_fck;
3236
3237DEFINE_STRUCT_CLK_HW_OMAP(wdt1_fck, "wkup_clkdm");
3238DEFINE_STRUCT_CLK(wdt1_fck, gpt12_fck_parent_names, core_l4_ick_ops);
3239
3240static struct clk wdt1_ick;
3241
3242static struct clk_hw_omap wdt1_ick_hw = {
3243 .hw = {
3244 .clk = &wdt1_ick,
3245 },
3246 .ops = &clkhwops_iclk_wait,
3247 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3248 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
3249 .clkdm_name = "wkup_clkdm",
3250};
3251
3252DEFINE_STRUCT_CLK(wdt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
3253
3254static struct clk wdt2_fck;
3255
3256static struct clk_hw_omap wdt2_fck_hw = {
3257 .hw = {
3258 .clk = &wdt2_fck,
3259 },
3260 .ops = &clkhwops_wait,
3261 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3262 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
3263 .clkdm_name = "wkup_clkdm",
3264};
3265
3266DEFINE_STRUCT_CLK(wdt2_fck, gpio1_dbck_parent_names, aes2_ick_ops);
3267
3268static struct clk wdt2_ick;
3269
3270static struct clk_hw_omap wdt2_ick_hw = {
3271 .hw = {
3272 .clk = &wdt2_ick,
3273 },
3274 .ops = &clkhwops_iclk_wait,
3275 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3276 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
3277 .clkdm_name = "wkup_clkdm",
3278};
3279
3280DEFINE_STRUCT_CLK(wdt2_ick, gpio1_ick_parent_names, aes2_ick_ops);
3281
3282static struct clk wdt3_fck;
3283
3284static struct clk_hw_omap wdt3_fck_hw = {
3285 .hw = {
3286 .clk = &wdt3_fck,
3287 },
3288 .ops = &clkhwops_wait,
3289 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
3290 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
3291 .clkdm_name = "per_clkdm",
3292};
3293
3294DEFINE_STRUCT_CLK(wdt3_fck, gpio2_dbck_parent_names, aes2_ick_ops);
3295
3296static struct clk wdt3_ick;
3297
3298static struct clk_hw_omap wdt3_ick_hw = {
3299 .hw = {
3300 .clk = &wdt3_ick,
3301 },
3302 .ops = &clkhwops_iclk_wait,
3303 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
3304 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
3305 .clkdm_name = "per_clkdm",
3306};
3307
3308DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
3309
3310/*
3311 * clocks specific to omap3430es1
3312 */
3313static struct omap_clk omap3430es1_clks[] = {
3314 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck),
3315 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck),
3316 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick),
3317 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck),
3318 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck),
3319 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck),
3320 CLK(NULL, "fshostusb_fck", &fshostusb_fck),
3321 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1),
3322 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1),
3323 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1),
3324 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1),
3325 CLK(NULL, "fac_ick", &fac_ick),
3326 CLK(NULL, "ssi_ick", &ssi_ick_3430es1),
3327 CLK(NULL, "usb_l4_ick", &usb_l4_ick),
3328 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1),
3329 CLK("omapdss_dss", "ick", &dss_ick_3430es1),
3330 CLK(NULL, "dss_ick", &dss_ick_3430es1),
3331};
3332
3333/*
3334 * clocks specific to am35xx
3335 */
3336static struct omap_clk am35xx_clks[] = {
3337 CLK(NULL, "ipss_ick", &ipss_ick),
3338 CLK(NULL, "rmii_ck", &rmii_ck),
3339 CLK(NULL, "pclk_ck", &pclk_ck),
3340 CLK(NULL, "emac_ick", &emac_ick),
3341 CLK(NULL, "emac_fck", &emac_fck),
3342 CLK("davinci_emac.0", NULL, &emac_ick),
3343 CLK("davinci_mdio.0", NULL, &emac_fck),
3344 CLK("vpfe-capture", "master", &vpfe_ick),
3345 CLK("vpfe-capture", "slave", &vpfe_fck),
3346 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx),
3347 CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx),
3348 CLK(NULL, "hecc_ck", &hecc_ck),
3349 CLK(NULL, "uart4_ick", &uart4_ick_am35xx),
3350 CLK(NULL, "uart4_fck", &uart4_fck_am35xx),
3351};
3352
3353/*
3354 * clocks specific to omap36xx
3355 */
3356static struct omap_clk omap36xx_clks[] = {
3357 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck),
3358 CLK(NULL, "uart4_fck", &uart4_fck),
3359};
3360
3361/*
3362 * clocks common to omap36xx omap34xx
3363 */
3364static struct omap_clk omap34xx_omap36xx_clks[] = {
3365 CLK(NULL, "aes1_ick", &aes1_ick),
3366 CLK("omap_rng", "ick", &rng_ick),
3367 CLK("omap3-rom-rng", "ick", &rng_ick),
3368 CLK(NULL, "sha11_ick", &sha11_ick),
3369 CLK(NULL, "des1_ick", &des1_ick),
3370 CLK(NULL, "cam_mclk", &cam_mclk),
3371 CLK(NULL, "cam_ick", &cam_ick),
3372 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck),
3373 CLK(NULL, "security_l3_ick", &security_l3_ick),
3374 CLK(NULL, "pka_ick", &pka_ick),
3375 CLK(NULL, "icr_ick", &icr_ick),
3376 CLK("omap-aes", "ick", &aes2_ick),
3377 CLK("omap-sham", "ick", &sha12_ick),
3378 CLK(NULL, "des2_ick", &des2_ick),
3379 CLK(NULL, "mspro_ick", &mspro_ick),
3380 CLK(NULL, "mailboxes_ick", &mailboxes_ick),
3381 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
3382 CLK(NULL, "sr1_fck", &sr1_fck),
3383 CLK(NULL, "sr2_fck", &sr2_fck),
3384 CLK(NULL, "sr_l4_ick", &sr_l4_ick),
3385 CLK(NULL, "security_l4_ick2", &security_l4_ick2),
3386 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick),
3387 CLK(NULL, "dpll2_fck", &dpll2_fck),
3388 CLK(NULL, "iva2_ck", &iva2_ck),
3389 CLK(NULL, "modem_fck", &modem_fck),
3390 CLK(NULL, "sad2d_ick", &sad2d_ick),
3391 CLK(NULL, "mad2d_ick", &mad2d_ick),
3392 CLK(NULL, "mspro_fck", &mspro_fck),
3393 CLK(NULL, "dpll2_ck", &dpll2_ck),
3394 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck),
3395};
3396
3397/*
3398 * clocks common to omap36xx and omap3430es2plus
3399 */
3400static struct omap_clk omap36xx_omap3430es2plus_clks[] = {
3401 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2),
3402 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2),
3403 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2),
3404 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2),
3405 CLK(NULL, "ssi_ick", &ssi_ick_3430es2),
3406 CLK(NULL, "usim_fck", &usim_fck),
3407 CLK(NULL, "usim_ick", &usim_ick),
3408};
3409
3410/*
3411 * clocks common to am35xx omap36xx and omap3430es2plus
3412 */
3413static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
3414 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck),
3415 CLK(NULL, "dpll5_ck", &dpll5_ck),
3416 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck),
3417 CLK(NULL, "sgx_fck", &sgx_fck),
3418 CLK(NULL, "sgx_ick", &sgx_ick),
3419 CLK(NULL, "cpefuse_fck", &cpefuse_fck),
3420 CLK(NULL, "ts_fck", &ts_fck),
3421 CLK(NULL, "usbtll_fck", &usbtll_fck),
3422 CLK(NULL, "usbtll_ick", &usbtll_ick),
3423 CLK("omap_hsmmc.2", "ick", &mmchs3_ick),
3424 CLK(NULL, "mmchs3_ick", &mmchs3_ick),
3425 CLK(NULL, "mmchs3_fck", &mmchs3_fck),
3426 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2),
3427 CLK("omapdss_dss", "ick", &dss_ick_3430es2),
3428 CLK(NULL, "dss_ick", &dss_ick_3430es2),
3429 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck),
3430 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck),
3431 CLK(NULL, "usbhost_ick", &usbhost_ick),
3432};
3433
3434/*
3435 * common clocks
3436 */
3437static struct omap_clk omap3xxx_clks[] = {
3438 CLK(NULL, "apb_pclk", &dummy_apb_pclk),
3439 CLK(NULL, "omap_32k_fck", &omap_32k_fck),
3440 CLK(NULL, "virt_12m_ck", &virt_12m_ck),
3441 CLK(NULL, "virt_13m_ck", &virt_13m_ck),
3442 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
3443 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
3444 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck),
3445 CLK(NULL, "osc_sys_ck", &osc_sys_ck),
3446 CLK("twl", "fck", &osc_sys_ck),
3447 CLK(NULL, "sys_ck", &sys_ck),
3448 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck),
3449 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck),
3450 CLK(NULL, "sys_altclk", &sys_altclk),
3451 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
3452 CLK(NULL, "sys_clkout1", &sys_clkout1),
3453 CLK(NULL, "dpll1_ck", &dpll1_ck),
3454 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck),
3455 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck),
3456 CLK(NULL, "dpll3_ck", &dpll3_ck),
3457 CLK(NULL, "core_ck", &core_ck),
3458 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck),
3459 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck),
3460 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck),
3461 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck),
3462 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck),
3463 CLK(NULL, "dpll4_ck", &dpll4_ck),
3464 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck),
3465 CLK(NULL, "omap_96m_fck", &omap_96m_fck),
3466 CLK(NULL, "cm_96m_fck", &cm_96m_fck),
3467 CLK(NULL, "omap_54m_fck", &omap_54m_fck),
3468 CLK(NULL, "omap_48m_fck", &omap_48m_fck),
3469 CLK(NULL, "omap_12m_fck", &omap_12m_fck),
3470 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck),
3471 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck),
3472 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck),
3473 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck),
3474 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck),
3475 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck),
3476 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck),
3477 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck),
3478 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck),
3479 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck),
3480 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck),
3481 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck),
3482 CLK(NULL, "sys_clkout2", &sys_clkout2),
3483 CLK(NULL, "corex2_fck", &corex2_fck),
3484 CLK(NULL, "dpll1_fck", &dpll1_fck),
3485 CLK(NULL, "mpu_ck", &mpu_ck),
3486 CLK(NULL, "arm_fck", &arm_fck),
3487 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck),
3488 CLK(NULL, "l3_ick", &l3_ick),
3489 CLK(NULL, "l4_ick", &l4_ick),
3490 CLK(NULL, "rm_ick", &rm_ick),
3491 CLK(NULL, "gpt10_fck", &gpt10_fck),
3492 CLK(NULL, "gpt11_fck", &gpt11_fck),
3493 CLK(NULL, "core_96m_fck", &core_96m_fck),
3494 CLK(NULL, "mmchs2_fck", &mmchs2_fck),
3495 CLK(NULL, "mmchs1_fck", &mmchs1_fck),
3496 CLK(NULL, "i2c3_fck", &i2c3_fck),
3497 CLK(NULL, "i2c2_fck", &i2c2_fck),
3498 CLK(NULL, "i2c1_fck", &i2c1_fck),
3499 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
3500 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
3501 CLK(NULL, "core_48m_fck", &core_48m_fck),
3502 CLK(NULL, "mcspi4_fck", &mcspi4_fck),
3503 CLK(NULL, "mcspi3_fck", &mcspi3_fck),
3504 CLK(NULL, "mcspi2_fck", &mcspi2_fck),
3505 CLK(NULL, "mcspi1_fck", &mcspi1_fck),
3506 CLK(NULL, "uart2_fck", &uart2_fck),
3507 CLK(NULL, "uart1_fck", &uart1_fck),
3508 CLK(NULL, "core_12m_fck", &core_12m_fck),
3509 CLK("omap_hdq.0", "fck", &hdq_fck),
3510 CLK(NULL, "hdq_fck", &hdq_fck),
3511 CLK(NULL, "core_l3_ick", &core_l3_ick),
3512 CLK(NULL, "sdrc_ick", &sdrc_ick),
3513 CLK(NULL, "gpmc_fck", &gpmc_fck),
3514 CLK(NULL, "core_l4_ick", &core_l4_ick),
3515 CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
3516 CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
3517 CLK(NULL, "mmchs2_ick", &mmchs2_ick),
3518 CLK(NULL, "mmchs1_ick", &mmchs1_ick),
3519 CLK("omap_hdq.0", "ick", &hdq_ick),
3520 CLK(NULL, "hdq_ick", &hdq_ick),
3521 CLK("omap2_mcspi.4", "ick", &mcspi4_ick),
3522 CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
3523 CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
3524 CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
3525 CLK(NULL, "mcspi4_ick", &mcspi4_ick),
3526 CLK(NULL, "mcspi3_ick", &mcspi3_ick),
3527 CLK(NULL, "mcspi2_ick", &mcspi2_ick),
3528 CLK(NULL, "mcspi1_ick", &mcspi1_ick),
3529 CLK("omap_i2c.3", "ick", &i2c3_ick),
3530 CLK("omap_i2c.2", "ick", &i2c2_ick),
3531 CLK("omap_i2c.1", "ick", &i2c1_ick),
3532 CLK(NULL, "i2c3_ick", &i2c3_ick),
3533 CLK(NULL, "i2c2_ick", &i2c2_ick),
3534 CLK(NULL, "i2c1_ick", &i2c1_ick),
3535 CLK(NULL, "uart2_ick", &uart2_ick),
3536 CLK(NULL, "uart1_ick", &uart1_ick),
3537 CLK(NULL, "gpt11_ick", &gpt11_ick),
3538 CLK(NULL, "gpt10_ick", &gpt10_ick),
3539 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
3540 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
3541 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
3542 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
3543 CLK(NULL, "omapctrl_ick", &omapctrl_ick),
3544 CLK(NULL, "dss_tv_fck", &dss_tv_fck),
3545 CLK(NULL, "dss_96m_fck", &dss_96m_fck),
3546 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck),
3547 CLK(NULL, "init_60m_fclk", &dummy_ck),
3548 CLK(NULL, "gpt1_fck", &gpt1_fck),
3549 CLK(NULL, "aes2_ick", &aes2_ick),
3550 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck),
3551 CLK(NULL, "gpio1_dbck", &gpio1_dbck),
3552 CLK(NULL, "sha12_ick", &sha12_ick),
3553 CLK(NULL, "wdt2_fck", &wdt2_fck),
3554 CLK("omap_wdt", "ick", &wdt2_ick),
3555 CLK(NULL, "wdt2_ick", &wdt2_ick),
3556 CLK(NULL, "wdt1_ick", &wdt1_ick),
3557 CLK(NULL, "gpio1_ick", &gpio1_ick),
3558 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick),
3559 CLK(NULL, "gpt12_ick", &gpt12_ick),
3560 CLK(NULL, "gpt1_ick", &gpt1_ick),
3561 CLK(NULL, "per_96m_fck", &per_96m_fck),
3562 CLK(NULL, "per_48m_fck", &per_48m_fck),
3563 CLK(NULL, "uart3_fck", &uart3_fck),
3564 CLK(NULL, "gpt2_fck", &gpt2_fck),
3565 CLK(NULL, "gpt3_fck", &gpt3_fck),
3566 CLK(NULL, "gpt4_fck", &gpt4_fck),
3567 CLK(NULL, "gpt5_fck", &gpt5_fck),
3568 CLK(NULL, "gpt6_fck", &gpt6_fck),
3569 CLK(NULL, "gpt7_fck", &gpt7_fck),
3570 CLK(NULL, "gpt8_fck", &gpt8_fck),
3571 CLK(NULL, "gpt9_fck", &gpt9_fck),
3572 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck),
3573 CLK(NULL, "gpio6_dbck", &gpio6_dbck),
3574 CLK(NULL, "gpio5_dbck", &gpio5_dbck),
3575 CLK(NULL, "gpio4_dbck", &gpio4_dbck),
3576 CLK(NULL, "gpio3_dbck", &gpio3_dbck),
3577 CLK(NULL, "gpio2_dbck", &gpio2_dbck),
3578 CLK(NULL, "wdt3_fck", &wdt3_fck),
3579 CLK(NULL, "per_l4_ick", &per_l4_ick),
3580 CLK(NULL, "gpio6_ick", &gpio6_ick),
3581 CLK(NULL, "gpio5_ick", &gpio5_ick),
3582 CLK(NULL, "gpio4_ick", &gpio4_ick),
3583 CLK(NULL, "gpio3_ick", &gpio3_ick),
3584 CLK(NULL, "gpio2_ick", &gpio2_ick),
3585 CLK(NULL, "wdt3_ick", &wdt3_ick),
3586 CLK(NULL, "uart3_ick", &uart3_ick),
3587 CLK(NULL, "uart4_ick", &uart4_ick),
3588 CLK(NULL, "gpt9_ick", &gpt9_ick),
3589 CLK(NULL, "gpt8_ick", &gpt8_ick),
3590 CLK(NULL, "gpt7_ick", &gpt7_ick),
3591 CLK(NULL, "gpt6_ick", &gpt6_ick),
3592 CLK(NULL, "gpt5_ick", &gpt5_ick),
3593 CLK(NULL, "gpt4_ick", &gpt4_ick),
3594 CLK(NULL, "gpt3_ick", &gpt3_ick),
3595 CLK(NULL, "gpt2_ick", &gpt2_ick),
3596 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
3597 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
3598 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
3599 CLK(NULL, "mcbsp4_ick", &mcbsp2_ick),
3600 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
3601 CLK(NULL, "mcbsp2_ick", &mcbsp4_ick),
3602 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
3603 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
3604 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
3605 CLK("etb", "emu_src_ck", &emu_src_ck),
3606 CLK(NULL, "emu_src_ck", &emu_src_ck),
3607 CLK(NULL, "pclk_fck", &pclk_fck),
3608 CLK(NULL, "pclkx2_fck", &pclkx2_fck),
3609 CLK(NULL, "atclk_fck", &atclk_fck),
3610 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck),
3611 CLK(NULL, "traceclk_fck", &traceclk_fck),
3612 CLK(NULL, "secure_32k_fck", &secure_32k_fck),
3613 CLK(NULL, "gpt12_fck", &gpt12_fck),
3614 CLK(NULL, "wdt1_fck", &wdt1_fck),
3615 CLK(NULL, "timer_32k_ck", &omap_32k_fck),
3616 CLK(NULL, "timer_sys_ck", &sys_ck),
3617 CLK(NULL, "cpufreq_ck", &dpll1_ck),
3618};
3619
3620static const char *enable_init_clks[] = {
3621 "sdrc_ick",
3622 "gpmc_fck",
3623 "omapctrl_ick",
3624};
3625
3626int __init omap3xxx_clk_init(void)
3627{
3628 if (omap3_has_192mhz_clk())
3629 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3630
3631 if (cpu_is_omap3630()) {
3632 dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
3633 dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
3634 dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
3635 dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
3636 dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
3637 dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
3638 }
3639
3640 /*
3641 * XXX This type of dynamic rewriting of the clock tree is
3642 * deprecated and should be revised soon.
3643 */
3644 if (cpu_is_omap3630())
3645 dpll4_dd = dpll4_dd_3630;
3646 else
3647 dpll4_dd = dpll4_dd_34xx;
3648
3649
3650 /*
3651 * 3505 must be tested before 3517, since 3517 returns true
3652 * for both AM3517 chips and AM3517 family chips, which
3653 * includes 3505. Unfortunately there's no obvious family
3654 * test for 3517/3505 :-(
3655 */
3656 if (soc_is_am35xx()) {
3657 cpu_mask = RATE_IN_34XX;
3658 omap_clocks_register(am35xx_clks, ARRAY_SIZE(am35xx_clks));
3659 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3660 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3661 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
3662 } else if (cpu_is_omap3630()) {
3663 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3664 omap_clocks_register(omap36xx_clks, ARRAY_SIZE(omap36xx_clks));
3665 omap_clocks_register(omap36xx_omap3430es2plus_clks,
3666 ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
3667 omap_clocks_register(omap34xx_omap36xx_clks,
3668 ARRAY_SIZE(omap34xx_omap36xx_clks));
3669 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3670 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3671 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
3672 } else if (soc_is_am33xx()) {
3673 cpu_mask = RATE_IN_AM33XX;
3674 } else if (cpu_is_ti814x()) {
3675 cpu_mask = RATE_IN_TI814X;
3676 } else if (cpu_is_omap34xx()) {
3677 if (omap_rev() == OMAP3430_REV_ES1_0) {
3678 cpu_mask = RATE_IN_3430ES1;
3679 omap_clocks_register(omap3430es1_clks,
3680 ARRAY_SIZE(omap3430es1_clks));
3681 omap_clocks_register(omap34xx_omap36xx_clks,
3682 ARRAY_SIZE(omap34xx_omap36xx_clks));
3683 omap_clocks_register(omap3xxx_clks,
3684 ARRAY_SIZE(omap3xxx_clks));
3685 } else {
3686 /*
3687 * Assume that anything that we haven't matched yet
3688 * has 3430ES2-type clocks.
3689 */
3690 cpu_mask = RATE_IN_3430ES2PLUS;
3691 omap_clocks_register(omap34xx_omap36xx_clks,
3692 ARRAY_SIZE(omap34xx_omap36xx_clks));
3693 omap_clocks_register(omap36xx_omap3430es2plus_clks,
3694 ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
3695 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3696 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3697 omap_clocks_register(omap3xxx_clks,
3698 ARRAY_SIZE(omap3xxx_clks));
3699 }
3700 } else {
3701 WARN(1, "clock: could not identify OMAP3 variant\n");
3702 }
3703
3704 omap2_clk_disable_autoidle_all();
3705
3706 omap2_clk_enable_init_clocks(enable_init_clks,
3707 ARRAY_SIZE(enable_init_clks));
3708
3709 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3710 (clk_get_rate(&osc_sys_ck) / 1000000),
3711 (clk_get_rate(&osc_sys_ck) / 100000) % 10,
3712 (clk_get_rate(&core_ck) / 1000000),
3713 (clk_get_rate(&arm_fck) / 1000000));
3714
3715 /*
3716 * Lock DPLL5 -- here only until other device init code can
3717 * handle this
3718 */
3719 if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
3720 omap3_clk_lock_dpll5();
3721
3722 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3723 sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3724 arm_fck_p = clk_get(NULL, "arm_fck");
3725
3726 return 0;
3727}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index a1bd6affb508..25ea1b176e33 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -461,7 +461,17 @@ void __init omap3_init_early(void)
461 omap3xxx_clockdomains_init(); 461 omap3xxx_clockdomains_init();
462 omap3xxx_hwmod_init(); 462 omap3xxx_hwmod_init();
463 omap_hwmod_init_postsetup(); 463 omap_hwmod_init_postsetup();
464 omap_clk_soc_init = omap3xxx_clk_init; 464 if (!of_have_populated_dt()) {
465 omap3_prcm_legacy_iomaps_init();
466 if (soc_is_am35xx())
467 omap_clk_soc_init = am35xx_clk_legacy_init;
468 else if (cpu_is_omap3630())
469 omap_clk_soc_init = omap36xx_clk_legacy_init;
470 else if (omap_rev() == OMAP3430_REV_ES1_0)
471 omap_clk_soc_init = omap3430es1_clk_legacy_init;
472 else
473 omap_clk_soc_init = omap3430_clk_legacy_init;
474 }
465} 475}
466 476
467void __init omap3430_init_early(void) 477void __init omap3430_init_early(void)
@@ -509,8 +519,6 @@ void __init ti81xx_init_early(void)
509 omap_hwmod_init_postsetup(); 519 omap_hwmod_init_postsetup();
510 if (of_have_populated_dt()) 520 if (of_have_populated_dt())
511 omap_clk_soc_init = ti81xx_dt_clk_init; 521 omap_clk_soc_init = ti81xx_dt_clk_init;
512 else
513 omap_clk_soc_init = omap3xxx_clk_init;
514} 522}
515 523
516void __init omap3_init_late(void) 524void __init omap3_init_late(void)
@@ -731,15 +739,17 @@ int __init omap_clk_init(void)
731 739
732 ti_clk_init_features(); 740 ti_clk_init_features();
733 741
734 ret = of_prcm_init(); 742 if (of_have_populated_dt()) {
735 if (ret) 743 ret = of_prcm_init();
736 return ret; 744 if (ret)
745 return ret;
737 746
738 of_clk_init(NULL); 747 of_clk_init(NULL);
739 748
740 ti_dt_clk_init_retry_clks(); 749 ti_dt_clk_init_retry_clks();
741 750
742 ti_dt_clockdomains_setup(); 751 ti_dt_clockdomains_setup();
752 }
743 753
744 ret = omap_clk_soc_init(); 754 ret = omap_clk_soc_init();
745 755
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 77752e49d8d4..b9061a6a2db8 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -20,6 +20,7 @@ extern void __iomem *prm_base;
20extern u16 prm_features; 20extern u16 prm_features;
21extern void omap2_set_globals_prm(void __iomem *prm); 21extern void omap2_set_globals_prm(void __iomem *prm);
22int of_prcm_init(void); 22int of_prcm_init(void);
23void omap3_prcm_legacy_iomaps_init(void);
23# endif 24# endif
24 25
25/* 26/*
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 779940cb6e56..542dd9dbd035 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -35,6 +35,8 @@
35#include "prm44xx.h" 35#include "prm44xx.h"
36#include "common.h" 36#include "common.h"
37#include "clock.h" 37#include "clock.h"
38#include "cm.h"
39#include "control.h"
38 40
39/* 41/*
40 * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs 42 * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
@@ -627,6 +629,15 @@ int __init of_prcm_init(void)
627 return 0; 629 return 0;
628} 630}
629 631
632void __init omap3_prcm_legacy_iomaps_init(void)
633{
634 ti_clk_ll_ops = &omap_clk_ll_ops;
635
636 clk_memmaps[TI_CLKM_CM] = cm_base + OMAP3430_IVA2_MOD;
637 clk_memmaps[TI_CLKM_PRM] = prm_base + OMAP3430_IVA2_MOD;
638 clk_memmaps[TI_CLKM_SCRM] = omap_ctrl_base_get();
639}
640
630static int __init prm_late_init(void) 641static int __init prm_late_init(void)
631{ 642{
632 if (prm_ll_data->late_init) 643 if (prm_ll_data->late_init)
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 36acc7d0d91c..14e6686a5eea 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -5,7 +5,8 @@ clk-common = dpll.o composite.o divider.o gate.o \
5obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o 5obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o
6obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-816x.o 6obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-816x.o
7obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o 7obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
8obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o clk-3xxx.o 8obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \
9 clk-3xxx.o clk-3xxx-legacy.o
9obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o 10obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o
10obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o 11obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o
11obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \ 12obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \
diff --git a/drivers/clk/ti/clk-3xxx-legacy.c b/drivers/clk/ti/clk-3xxx-legacy.c
new file mode 100644
index 000000000000..e0732a4c8f26
--- /dev/null
+++ b/drivers/clk/ti/clk-3xxx-legacy.c
@@ -0,0 +1,4653 @@
1/*
2 * OMAP3 Legacy clock data
3 *
4 * Copyright (C) 2014 Texas Instruments, Inc
5 * Tero Kristo (t-kristo@ti.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/clk-provider.h>
19#include <linux/clk/ti.h>
20
21#include "clock.h"
22
23static struct ti_clk_fixed virt_12m_ck_data = {
24 .frequency = 12000000,
25};
26
27static struct ti_clk virt_12m_ck = {
28 .name = "virt_12m_ck",
29 .type = TI_CLK_FIXED,
30 .data = &virt_12m_ck_data,
31};
32
33static struct ti_clk_fixed virt_13m_ck_data = {
34 .frequency = 13000000,
35};
36
37static struct ti_clk virt_13m_ck = {
38 .name = "virt_13m_ck",
39 .type = TI_CLK_FIXED,
40 .data = &virt_13m_ck_data,
41};
42
43static struct ti_clk_fixed virt_19200000_ck_data = {
44 .frequency = 19200000,
45};
46
47static struct ti_clk virt_19200000_ck = {
48 .name = "virt_19200000_ck",
49 .type = TI_CLK_FIXED,
50 .data = &virt_19200000_ck_data,
51};
52
53static struct ti_clk_fixed virt_26000000_ck_data = {
54 .frequency = 26000000,
55};
56
57static struct ti_clk virt_26000000_ck = {
58 .name = "virt_26000000_ck",
59 .type = TI_CLK_FIXED,
60 .data = &virt_26000000_ck_data,
61};
62
63static struct ti_clk_fixed virt_38_4m_ck_data = {
64 .frequency = 38400000,
65};
66
67static struct ti_clk virt_38_4m_ck = {
68 .name = "virt_38_4m_ck",
69 .type = TI_CLK_FIXED,
70 .data = &virt_38_4m_ck_data,
71};
72
73static struct ti_clk_fixed virt_16_8m_ck_data = {
74 .frequency = 16800000,
75};
76
77static struct ti_clk virt_16_8m_ck = {
78 .name = "virt_16_8m_ck",
79 .type = TI_CLK_FIXED,
80 .data = &virt_16_8m_ck_data,
81};
82
83static const char *osc_sys_ck_parents[] = {
84 "virt_12m_ck",
85 "virt_13m_ck",
86 "virt_19200000_ck",
87 "virt_26000000_ck",
88 "virt_38_4m_ck",
89 "virt_16_8m_ck",
90};
91
92static struct ti_clk_mux osc_sys_ck_data = {
93 .num_parents = ARRAY_SIZE(osc_sys_ck_parents),
94 .reg = 0xd40,
95 .module = TI_CLKM_PRM,
96 .parents = osc_sys_ck_parents,
97};
98
99static struct ti_clk osc_sys_ck = {
100 .name = "osc_sys_ck",
101 .type = TI_CLK_MUX,
102 .data = &osc_sys_ck_data,
103};
104
105static struct ti_clk_divider sys_ck_data = {
106 .parent = "osc_sys_ck",
107 .bit_shift = 6,
108 .max_div = 3,
109 .reg = 0x1270,
110 .module = TI_CLKM_PRM,
111 .flags = CLKF_INDEX_STARTS_AT_ONE,
112};
113
114static struct ti_clk sys_ck = {
115 .name = "sys_ck",
116 .type = TI_CLK_DIVIDER,
117 .data = &sys_ck_data,
118};
119
120static const char *dpll3_ck_parents[] = {
121 "sys_ck",
122 "sys_ck",
123};
124
125static struct ti_clk_dpll dpll3_ck_data = {
126 .num_parents = ARRAY_SIZE(dpll3_ck_parents),
127 .control_reg = 0xd00,
128 .idlest_reg = 0xd20,
129 .mult_div1_reg = 0xd40,
130 .autoidle_reg = 0xd30,
131 .module = TI_CLKM_CM,
132 .parents = dpll3_ck_parents,
133 .flags = CLKF_CORE,
134 .freqsel_mask = 0xf0,
135 .div1_mask = 0x7f00,
136 .idlest_mask = 0x1,
137 .auto_recal_bit = 0x3,
138 .max_divider = 0x80,
139 .min_divider = 0x1,
140 .recal_en_bit = 0x5,
141 .max_multiplier = 0x7ff,
142 .enable_mask = 0x7,
143 .mult_mask = 0x7ff0000,
144 .recal_st_bit = 0x5,
145 .autoidle_mask = 0x7,
146};
147
148static struct ti_clk dpll3_ck = {
149 .name = "dpll3_ck",
150 .clkdm_name = "dpll3_clkdm",
151 .type = TI_CLK_DPLL,
152 .data = &dpll3_ck_data,
153};
154
155static struct ti_clk_divider dpll3_m2_ck_data = {
156 .parent = "dpll3_ck",
157 .bit_shift = 27,
158 .max_div = 31,
159 .reg = 0xd40,
160 .module = TI_CLKM_CM,
161 .flags = CLKF_INDEX_STARTS_AT_ONE,
162};
163
164static struct ti_clk dpll3_m2_ck = {
165 .name = "dpll3_m2_ck",
166 .type = TI_CLK_DIVIDER,
167 .data = &dpll3_m2_ck_data,
168};
169
170static struct ti_clk_fixed_factor core_ck_data = {
171 .parent = "dpll3_m2_ck",
172 .div = 1,
173 .mult = 1,
174};
175
176static struct ti_clk core_ck = {
177 .name = "core_ck",
178 .type = TI_CLK_FIXED_FACTOR,
179 .data = &core_ck_data,
180};
181
182static struct ti_clk_divider l3_ick_data = {
183 .parent = "core_ck",
184 .max_div = 3,
185 .reg = 0xa40,
186 .module = TI_CLKM_CM,
187 .flags = CLKF_INDEX_STARTS_AT_ONE,
188};
189
190static struct ti_clk l3_ick = {
191 .name = "l3_ick",
192 .type = TI_CLK_DIVIDER,
193 .data = &l3_ick_data,
194};
195
196static struct ti_clk_fixed_factor security_l3_ick_data = {
197 .parent = "l3_ick",
198 .div = 1,
199 .mult = 1,
200};
201
202static struct ti_clk security_l3_ick = {
203 .name = "security_l3_ick",
204 .type = TI_CLK_FIXED_FACTOR,
205 .data = &security_l3_ick_data,
206};
207
208static struct ti_clk_fixed_factor wkup_l4_ick_data = {
209 .parent = "sys_ck",
210 .div = 1,
211 .mult = 1,
212};
213
214static struct ti_clk wkup_l4_ick = {
215 .name = "wkup_l4_ick",
216 .type = TI_CLK_FIXED_FACTOR,
217 .data = &wkup_l4_ick_data,
218};
219
220static struct ti_clk_gate usim_ick_data = {
221 .parent = "wkup_l4_ick",
222 .bit_shift = 9,
223 .reg = 0xc10,
224 .module = TI_CLKM_CM,
225 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
226};
227
228static struct ti_clk usim_ick = {
229 .name = "usim_ick",
230 .clkdm_name = "wkup_clkdm",
231 .type = TI_CLK_GATE,
232 .data = &usim_ick_data,
233};
234
235static struct ti_clk_gate dss2_alwon_fck_data = {
236 .parent = "sys_ck",
237 .bit_shift = 1,
238 .reg = 0xe00,
239 .module = TI_CLKM_CM,
240};
241
242static struct ti_clk dss2_alwon_fck = {
243 .name = "dss2_alwon_fck",
244 .clkdm_name = "dss_clkdm",
245 .type = TI_CLK_GATE,
246 .data = &dss2_alwon_fck_data,
247};
248
249static struct ti_clk_divider l4_ick_data = {
250 .parent = "l3_ick",
251 .bit_shift = 2,
252 .max_div = 3,
253 .reg = 0xa40,
254 .module = TI_CLKM_CM,
255 .flags = CLKF_INDEX_STARTS_AT_ONE,
256};
257
258static struct ti_clk l4_ick = {
259 .name = "l4_ick",
260 .type = TI_CLK_DIVIDER,
261 .data = &l4_ick_data,
262};
263
264static struct ti_clk_fixed_factor core_l4_ick_data = {
265 .parent = "l4_ick",
266 .div = 1,
267 .mult = 1,
268};
269
270static struct ti_clk core_l4_ick = {
271 .name = "core_l4_ick",
272 .type = TI_CLK_FIXED_FACTOR,
273 .data = &core_l4_ick_data,
274};
275
276static struct ti_clk_gate mmchs2_ick_data = {
277 .parent = "core_l4_ick",
278 .bit_shift = 25,
279 .reg = 0xa10,
280 .module = TI_CLKM_CM,
281 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
282};
283
284static struct ti_clk mmchs2_ick = {
285 .name = "mmchs2_ick",
286 .clkdm_name = "core_l4_clkdm",
287 .type = TI_CLK_GATE,
288 .data = &mmchs2_ick_data,
289};
290
291static const char *dpll4_ck_parents[] = {
292 "sys_ck",
293 "sys_ck",
294};
295
296static struct ti_clk_dpll dpll4_ck_data = {
297 .num_parents = ARRAY_SIZE(dpll4_ck_parents),
298 .control_reg = 0xd00,
299 .idlest_reg = 0xd20,
300 .mult_div1_reg = 0xd44,
301 .autoidle_reg = 0xd30,
302 .module = TI_CLKM_CM,
303 .parents = dpll4_ck_parents,
304 .flags = CLKF_PER,
305 .freqsel_mask = 0xf00000,
306 .modes = 0x82,
307 .div1_mask = 0x7f,
308 .idlest_mask = 0x2,
309 .auto_recal_bit = 0x13,
310 .max_divider = 0x80,
311 .min_divider = 0x1,
312 .recal_en_bit = 0x6,
313 .max_multiplier = 0x7ff,
314 .enable_mask = 0x70000,
315 .mult_mask = 0x7ff00,
316 .recal_st_bit = 0x6,
317 .autoidle_mask = 0x38,
318};
319
320static struct ti_clk dpll4_ck = {
321 .name = "dpll4_ck",
322 .clkdm_name = "dpll4_clkdm",
323 .type = TI_CLK_DPLL,
324 .data = &dpll4_ck_data,
325};
326
327static struct ti_clk_divider dpll4_m2_ck_data = {
328 .parent = "dpll4_ck",
329 .max_div = 63,
330 .reg = 0xd48,
331 .module = TI_CLKM_CM,
332 .flags = CLKF_INDEX_STARTS_AT_ONE,
333};
334
335static struct ti_clk dpll4_m2_ck = {
336 .name = "dpll4_m2_ck",
337 .type = TI_CLK_DIVIDER,
338 .data = &dpll4_m2_ck_data,
339};
340
341static struct ti_clk_fixed_factor dpll4_m2x2_mul_ck_data = {
342 .parent = "dpll4_m2_ck",
343 .div = 1,
344 .mult = 2,
345};
346
347static struct ti_clk dpll4_m2x2_mul_ck = {
348 .name = "dpll4_m2x2_mul_ck",
349 .type = TI_CLK_FIXED_FACTOR,
350 .data = &dpll4_m2x2_mul_ck_data,
351};
352
353static struct ti_clk_gate dpll4_m2x2_ck_data = {
354 .parent = "dpll4_m2x2_mul_ck",
355 .bit_shift = 0x1b,
356 .reg = 0xd00,
357 .module = TI_CLKM_CM,
358 .flags = CLKF_SET_BIT_TO_DISABLE,
359};
360
361static struct ti_clk dpll4_m2x2_ck = {
362 .name = "dpll4_m2x2_ck",
363 .type = TI_CLK_GATE,
364 .data = &dpll4_m2x2_ck_data,
365};
366
367static struct ti_clk_fixed_factor omap_96m_alwon_fck_data = {
368 .parent = "dpll4_m2x2_ck",
369 .div = 1,
370 .mult = 1,
371};
372
373static struct ti_clk omap_96m_alwon_fck = {
374 .name = "omap_96m_alwon_fck",
375 .type = TI_CLK_FIXED_FACTOR,
376 .data = &omap_96m_alwon_fck_data,
377};
378
379static struct ti_clk_fixed_factor cm_96m_fck_data = {
380 .parent = "omap_96m_alwon_fck",
381 .div = 1,
382 .mult = 1,
383};
384
385static struct ti_clk cm_96m_fck = {
386 .name = "cm_96m_fck",
387 .type = TI_CLK_FIXED_FACTOR,
388 .data = &cm_96m_fck_data,
389};
390
391static const char *omap_96m_fck_parents[] = {
392 "cm_96m_fck",
393 "sys_ck",
394};
395
396static struct ti_clk_mux omap_96m_fck_data = {
397 .bit_shift = 6,
398 .num_parents = ARRAY_SIZE(omap_96m_fck_parents),
399 .reg = 0xd40,
400 .module = TI_CLKM_CM,
401 .parents = omap_96m_fck_parents,
402};
403
404static struct ti_clk omap_96m_fck = {
405 .name = "omap_96m_fck",
406 .type = TI_CLK_MUX,
407 .data = &omap_96m_fck_data,
408};
409
410static struct ti_clk_fixed_factor core_96m_fck_data = {
411 .parent = "omap_96m_fck",
412 .div = 1,
413 .mult = 1,
414};
415
416static struct ti_clk core_96m_fck = {
417 .name = "core_96m_fck",
418 .type = TI_CLK_FIXED_FACTOR,
419 .data = &core_96m_fck_data,
420};
421
422static struct ti_clk_gate mspro_fck_data = {
423 .parent = "core_96m_fck",
424 .bit_shift = 23,
425 .reg = 0xa00,
426 .module = TI_CLKM_CM,
427 .flags = CLKF_WAIT,
428};
429
430static struct ti_clk mspro_fck = {
431 .name = "mspro_fck",
432 .clkdm_name = "core_l4_clkdm",
433 .type = TI_CLK_GATE,
434 .data = &mspro_fck_data,
435};
436
437static struct ti_clk_gate dss_ick_3430es2_data = {
438 .parent = "l4_ick",
439 .bit_shift = 0,
440 .reg = 0xe10,
441 .module = TI_CLKM_CM,
442 .flags = CLKF_DSS | CLKF_OMAP3 | CLKF_INTERFACE,
443};
444
445static struct ti_clk dss_ick_3430es2 = {
446 .name = "dss_ick",
447 .clkdm_name = "dss_clkdm",
448 .type = TI_CLK_GATE,
449 .data = &dss_ick_3430es2_data,
450};
451
452static struct ti_clk_gate uart4_ick_am35xx_data = {
453 .parent = "core_l4_ick",
454 .bit_shift = 23,
455 .reg = 0xa10,
456 .module = TI_CLKM_CM,
457 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
458};
459
460static struct ti_clk uart4_ick_am35xx = {
461 .name = "uart4_ick_am35xx",
462 .clkdm_name = "core_l4_clkdm",
463 .type = TI_CLK_GATE,
464 .data = &uart4_ick_am35xx_data,
465};
466
467static struct ti_clk_fixed_factor security_l4_ick2_data = {
468 .parent = "l4_ick",
469 .div = 1,
470 .mult = 1,
471};
472
473static struct ti_clk security_l4_ick2 = {
474 .name = "security_l4_ick2",
475 .type = TI_CLK_FIXED_FACTOR,
476 .data = &security_l4_ick2_data,
477};
478
479static struct ti_clk_gate aes1_ick_data = {
480 .parent = "security_l4_ick2",
481 .bit_shift = 3,
482 .reg = 0xa14,
483 .module = TI_CLKM_CM,
484 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
485};
486
487static struct ti_clk aes1_ick = {
488 .name = "aes1_ick",
489 .type = TI_CLK_GATE,
490 .data = &aes1_ick_data,
491};
492
493static const char *dpll5_ck_parents[] = {
494 "sys_ck",
495 "sys_ck",
496};
497
498static struct ti_clk_dpll dpll5_ck_data = {
499 .num_parents = ARRAY_SIZE(dpll5_ck_parents),
500 .control_reg = 0xd04,
501 .idlest_reg = 0xd24,
502 .mult_div1_reg = 0xd4c,
503 .autoidle_reg = 0xd34,
504 .module = TI_CLKM_CM,
505 .parents = dpll5_ck_parents,
506 .freqsel_mask = 0xf0,
507 .modes = 0x82,
508 .div1_mask = 0x7f,
509 .idlest_mask = 0x1,
510 .auto_recal_bit = 0x3,
511 .max_divider = 0x80,
512 .min_divider = 0x1,
513 .recal_en_bit = 0x19,
514 .max_multiplier = 0x7ff,
515 .enable_mask = 0x7,
516 .mult_mask = 0x7ff00,
517 .recal_st_bit = 0x19,
518 .autoidle_mask = 0x7,
519};
520
521static struct ti_clk dpll5_ck = {
522 .name = "dpll5_ck",
523 .clkdm_name = "dpll5_clkdm",
524 .type = TI_CLK_DPLL,
525 .data = &dpll5_ck_data,
526};
527
528static struct ti_clk_divider dpll5_m2_ck_data = {
529 .parent = "dpll5_ck",
530 .max_div = 31,
531 .reg = 0xd50,
532 .module = TI_CLKM_CM,
533 .flags = CLKF_INDEX_STARTS_AT_ONE,
534};
535
536static struct ti_clk dpll5_m2_ck = {
537 .name = "dpll5_m2_ck",
538 .type = TI_CLK_DIVIDER,
539 .data = &dpll5_m2_ck_data,
540};
541
542static struct ti_clk_gate usbhost_120m_fck_data = {
543 .parent = "dpll5_m2_ck",
544 .bit_shift = 1,
545 .reg = 0x1400,
546 .module = TI_CLKM_CM,
547};
548
549static struct ti_clk usbhost_120m_fck = {
550 .name = "usbhost_120m_fck",
551 .clkdm_name = "usbhost_clkdm",
552 .type = TI_CLK_GATE,
553 .data = &usbhost_120m_fck_data,
554};
555
556static struct ti_clk_fixed_factor cm_96m_d2_fck_data = {
557 .parent = "cm_96m_fck",
558 .div = 2,
559 .mult = 1,
560};
561
562static struct ti_clk cm_96m_d2_fck = {
563 .name = "cm_96m_d2_fck",
564 .type = TI_CLK_FIXED_FACTOR,
565 .data = &cm_96m_d2_fck_data,
566};
567
568static struct ti_clk_fixed sys_altclk_data = {
569 .frequency = 0x0,
570};
571
572static struct ti_clk sys_altclk = {
573 .name = "sys_altclk",
574 .type = TI_CLK_FIXED,
575 .data = &sys_altclk_data,
576};
577
578static const char *omap_48m_fck_parents[] = {
579 "cm_96m_d2_fck",
580 "sys_altclk",
581};
582
583static struct ti_clk_mux omap_48m_fck_data = {
584 .bit_shift = 3,
585 .num_parents = ARRAY_SIZE(omap_48m_fck_parents),
586 .reg = 0xd40,
587 .module = TI_CLKM_CM,
588 .parents = omap_48m_fck_parents,
589};
590
591static struct ti_clk omap_48m_fck = {
592 .name = "omap_48m_fck",
593 .type = TI_CLK_MUX,
594 .data = &omap_48m_fck_data,
595};
596
597static struct ti_clk_fixed_factor core_48m_fck_data = {
598 .parent = "omap_48m_fck",
599 .div = 1,
600 .mult = 1,
601};
602
603static struct ti_clk core_48m_fck = {
604 .name = "core_48m_fck",
605 .type = TI_CLK_FIXED_FACTOR,
606 .data = &core_48m_fck_data,
607};
608
609static struct ti_clk_fixed mcbsp_clks_data = {
610 .frequency = 0x0,
611};
612
613static struct ti_clk mcbsp_clks = {
614 .name = "mcbsp_clks",
615 .type = TI_CLK_FIXED,
616 .data = &mcbsp_clks_data,
617};
618
619static struct ti_clk_gate mcbsp2_gate_fck_data = {
620 .parent = "mcbsp_clks",
621 .bit_shift = 0,
622 .reg = 0x1000,
623 .module = TI_CLKM_CM,
624};
625
626static struct ti_clk_fixed_factor per_96m_fck_data = {
627 .parent = "omap_96m_alwon_fck",
628 .div = 1,
629 .mult = 1,
630};
631
632static struct ti_clk per_96m_fck = {
633 .name = "per_96m_fck",
634 .type = TI_CLK_FIXED_FACTOR,
635 .data = &per_96m_fck_data,
636};
637
638static const char *mcbsp2_mux_fck_parents[] = {
639 "per_96m_fck",
640 "mcbsp_clks",
641};
642
643static struct ti_clk_mux mcbsp2_mux_fck_data = {
644 .bit_shift = 6,
645 .num_parents = ARRAY_SIZE(mcbsp2_mux_fck_parents),
646 .reg = 0x274,
647 .module = TI_CLKM_SCRM,
648 .parents = mcbsp2_mux_fck_parents,
649};
650
651static struct ti_clk_composite mcbsp2_fck_data = {
652 .mux = &mcbsp2_mux_fck_data,
653 .gate = &mcbsp2_gate_fck_data,
654};
655
656static struct ti_clk mcbsp2_fck = {
657 .name = "mcbsp2_fck",
658 .type = TI_CLK_COMPOSITE,
659 .data = &mcbsp2_fck_data,
660};
661
662static struct ti_clk_fixed_factor dpll3_m2x2_ck_data = {
663 .parent = "dpll3_m2_ck",
664 .div = 1,
665 .mult = 2,
666};
667
668static struct ti_clk dpll3_m2x2_ck = {
669 .name = "dpll3_m2x2_ck",
670 .type = TI_CLK_FIXED_FACTOR,
671 .data = &dpll3_m2x2_ck_data,
672};
673
674static struct ti_clk_fixed_factor corex2_fck_data = {
675 .parent = "dpll3_m2x2_ck",
676 .div = 1,
677 .mult = 1,
678};
679
680static struct ti_clk corex2_fck = {
681 .name = "corex2_fck",
682 .type = TI_CLK_FIXED_FACTOR,
683 .data = &corex2_fck_data,
684};
685
686static struct ti_clk_gate ssi_ssr_gate_fck_3430es1_data = {
687 .parent = "corex2_fck",
688 .bit_shift = 0,
689 .reg = 0xa00,
690 .module = TI_CLKM_CM,
691 .flags = CLKF_NO_WAIT,
692};
693
694static int ssi_ssr_div_fck_3430es1_divs[] = {
695 0,
696 1,
697 2,
698 3,
699 4,
700 0,
701 6,
702 0,
703 8,
704};
705
706static struct ti_clk_divider ssi_ssr_div_fck_3430es1_data = {
707 .num_dividers = ARRAY_SIZE(ssi_ssr_div_fck_3430es1_divs),
708 .parent = "corex2_fck",
709 .bit_shift = 8,
710 .dividers = ssi_ssr_div_fck_3430es1_divs,
711 .reg = 0xa40,
712 .module = TI_CLKM_CM,
713};
714
715static struct ti_clk_composite ssi_ssr_fck_3430es1_data = {
716 .gate = &ssi_ssr_gate_fck_3430es1_data,
717 .divider = &ssi_ssr_div_fck_3430es1_data,
718};
719
720static struct ti_clk ssi_ssr_fck_3430es1 = {
721 .name = "ssi_ssr_fck",
722 .type = TI_CLK_COMPOSITE,
723 .data = &ssi_ssr_fck_3430es1_data,
724};
725
726static struct ti_clk_fixed_factor ssi_sst_fck_3430es1_data = {
727 .parent = "ssi_ssr_fck",
728 .div = 2,
729 .mult = 1,
730};
731
732static struct ti_clk ssi_sst_fck_3430es1 = {
733 .name = "ssi_sst_fck",
734 .type = TI_CLK_FIXED_FACTOR,
735 .data = &ssi_sst_fck_3430es1_data,
736};
737
738static struct ti_clk_fixed omap_32k_fck_data = {
739 .frequency = 32768,
740};
741
742static struct ti_clk omap_32k_fck = {
743 .name = "omap_32k_fck",
744 .type = TI_CLK_FIXED,
745 .data = &omap_32k_fck_data,
746};
747
748static struct ti_clk_fixed_factor per_32k_alwon_fck_data = {
749 .parent = "omap_32k_fck",
750 .div = 1,
751 .mult = 1,
752};
753
754static struct ti_clk per_32k_alwon_fck = {
755 .name = "per_32k_alwon_fck",
756 .type = TI_CLK_FIXED_FACTOR,
757 .data = &per_32k_alwon_fck_data,
758};
759
760static struct ti_clk_gate gpio5_dbck_data = {
761 .parent = "per_32k_alwon_fck",
762 .bit_shift = 16,
763 .reg = 0x1000,
764 .module = TI_CLKM_CM,
765};
766
767static struct ti_clk gpio5_dbck = {
768 .name = "gpio5_dbck",
769 .clkdm_name = "per_clkdm",
770 .type = TI_CLK_GATE,
771 .data = &gpio5_dbck_data,
772};
773
774static struct ti_clk_gate gpt1_ick_data = {
775 .parent = "wkup_l4_ick",
776 .bit_shift = 0,
777 .reg = 0xc10,
778 .module = TI_CLKM_CM,
779 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
780};
781
782static struct ti_clk gpt1_ick = {
783 .name = "gpt1_ick",
784 .clkdm_name = "wkup_clkdm",
785 .type = TI_CLK_GATE,
786 .data = &gpt1_ick_data,
787};
788
789static struct ti_clk_gate mcspi3_fck_data = {
790 .parent = "core_48m_fck",
791 .bit_shift = 20,
792 .reg = 0xa00,
793 .module = TI_CLKM_CM,
794 .flags = CLKF_WAIT,
795};
796
797static struct ti_clk mcspi3_fck = {
798 .name = "mcspi3_fck",
799 .clkdm_name = "core_l4_clkdm",
800 .type = TI_CLK_GATE,
801 .data = &mcspi3_fck_data,
802};
803
804static struct ti_clk_gate gpt2_gate_fck_data = {
805 .parent = "sys_ck",
806 .bit_shift = 3,
807 .reg = 0x1000,
808 .module = TI_CLKM_CM,
809};
810
811static const char *gpt2_mux_fck_parents[] = {
812 "omap_32k_fck",
813 "sys_ck",
814};
815
816static struct ti_clk_mux gpt2_mux_fck_data = {
817 .num_parents = ARRAY_SIZE(gpt2_mux_fck_parents),
818 .reg = 0x1040,
819 .module = TI_CLKM_CM,
820 .parents = gpt2_mux_fck_parents,
821};
822
823static struct ti_clk_composite gpt2_fck_data = {
824 .mux = &gpt2_mux_fck_data,
825 .gate = &gpt2_gate_fck_data,
826};
827
828static struct ti_clk gpt2_fck = {
829 .name = "gpt2_fck",
830 .type = TI_CLK_COMPOSITE,
831 .data = &gpt2_fck_data,
832};
833
834static struct ti_clk_gate gpt10_ick_data = {
835 .parent = "core_l4_ick",
836 .bit_shift = 11,
837 .reg = 0xa10,
838 .module = TI_CLKM_CM,
839 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
840};
841
842static struct ti_clk gpt10_ick = {
843 .name = "gpt10_ick",
844 .clkdm_name = "core_l4_clkdm",
845 .type = TI_CLK_GATE,
846 .data = &gpt10_ick_data,
847};
848
849static struct ti_clk_gate uart2_fck_data = {
850 .parent = "core_48m_fck",
851 .bit_shift = 14,
852 .reg = 0xa00,
853 .module = TI_CLKM_CM,
854 .flags = CLKF_WAIT,
855};
856
857static struct ti_clk uart2_fck = {
858 .name = "uart2_fck",
859 .clkdm_name = "core_l4_clkdm",
860 .type = TI_CLK_GATE,
861 .data = &uart2_fck_data,
862};
863
864static struct ti_clk_fixed_factor sr_l4_ick_data = {
865 .parent = "l4_ick",
866 .div = 1,
867 .mult = 1,
868};
869
870static struct ti_clk sr_l4_ick = {
871 .name = "sr_l4_ick",
872 .type = TI_CLK_FIXED_FACTOR,
873 .data = &sr_l4_ick_data,
874};
875
876static struct ti_clk_fixed_factor omap_96m_d8_fck_data = {
877 .parent = "omap_96m_fck",
878 .div = 8,
879 .mult = 1,
880};
881
882static struct ti_clk omap_96m_d8_fck = {
883 .name = "omap_96m_d8_fck",
884 .type = TI_CLK_FIXED_FACTOR,
885 .data = &omap_96m_d8_fck_data,
886};
887
888static struct ti_clk_divider dpll4_m5_ck_data = {
889 .parent = "dpll4_ck",
890 .max_div = 63,
891 .reg = 0xf40,
892 .module = TI_CLKM_CM,
893 .flags = CLKF_INDEX_STARTS_AT_ONE,
894};
895
896static struct ti_clk dpll4_m5_ck = {
897 .name = "dpll4_m5_ck",
898 .type = TI_CLK_DIVIDER,
899 .data = &dpll4_m5_ck_data,
900};
901
902static struct ti_clk_fixed_factor dpll4_m5x2_mul_ck_data = {
903 .parent = "dpll4_m5_ck",
904 .div = 1,
905 .mult = 2,
906 .flags = CLKF_SET_RATE_PARENT,
907};
908
909static struct ti_clk dpll4_m5x2_mul_ck = {
910 .name = "dpll4_m5x2_mul_ck",
911 .type = TI_CLK_FIXED_FACTOR,
912 .data = &dpll4_m5x2_mul_ck_data,
913};
914
915static struct ti_clk_gate dpll4_m5x2_ck_data = {
916 .parent = "dpll4_m5x2_mul_ck",
917 .bit_shift = 0x1e,
918 .reg = 0xd00,
919 .module = TI_CLKM_CM,
920 .flags = CLKF_SET_BIT_TO_DISABLE,
921};
922
923static struct ti_clk dpll4_m5x2_ck = {
924 .name = "dpll4_m5x2_ck",
925 .type = TI_CLK_GATE,
926 .data = &dpll4_m5x2_ck_data,
927};
928
929static struct ti_clk_gate cam_mclk_data = {
930 .parent = "dpll4_m5x2_ck",
931 .bit_shift = 0,
932 .reg = 0xf00,
933 .module = TI_CLKM_CM,
934 .flags = CLKF_SET_RATE_PARENT,
935};
936
937static struct ti_clk cam_mclk = {
938 .name = "cam_mclk",
939 .type = TI_CLK_GATE,
940 .data = &cam_mclk_data,
941};
942
943static struct ti_clk_gate mcbsp3_gate_fck_data = {
944 .parent = "mcbsp_clks",
945 .bit_shift = 1,
946 .reg = 0x1000,
947 .module = TI_CLKM_CM,
948};
949
950static const char *mcbsp3_mux_fck_parents[] = {
951 "per_96m_fck",
952 "mcbsp_clks",
953};
954
955static struct ti_clk_mux mcbsp3_mux_fck_data = {
956 .num_parents = ARRAY_SIZE(mcbsp3_mux_fck_parents),
957 .reg = 0x2d8,
958 .module = TI_CLKM_SCRM,
959 .parents = mcbsp3_mux_fck_parents,
960};
961
962static struct ti_clk_composite mcbsp3_fck_data = {
963 .mux = &mcbsp3_mux_fck_data,
964 .gate = &mcbsp3_gate_fck_data,
965};
966
967static struct ti_clk mcbsp3_fck = {
968 .name = "mcbsp3_fck",
969 .type = TI_CLK_COMPOSITE,
970 .data = &mcbsp3_fck_data,
971};
972
973static struct ti_clk_gate csi2_96m_fck_data = {
974 .parent = "core_96m_fck",
975 .bit_shift = 1,
976 .reg = 0xf00,
977 .module = TI_CLKM_CM,
978};
979
980static struct ti_clk csi2_96m_fck = {
981 .name = "csi2_96m_fck",
982 .clkdm_name = "cam_clkdm",
983 .type = TI_CLK_GATE,
984 .data = &csi2_96m_fck_data,
985};
986
987static struct ti_clk_gate gpt9_gate_fck_data = {
988 .parent = "sys_ck",
989 .bit_shift = 10,
990 .reg = 0x1000,
991 .module = TI_CLKM_CM,
992};
993
994static const char *gpt9_mux_fck_parents[] = {
995 "omap_32k_fck",
996 "sys_ck",
997};
998
999static struct ti_clk_mux gpt9_mux_fck_data = {
1000 .bit_shift = 7,
1001 .num_parents = ARRAY_SIZE(gpt9_mux_fck_parents),
1002 .reg = 0x1040,
1003 .module = TI_CLKM_CM,
1004 .parents = gpt9_mux_fck_parents,
1005};
1006
1007static struct ti_clk_composite gpt9_fck_data = {
1008 .mux = &gpt9_mux_fck_data,
1009 .gate = &gpt9_gate_fck_data,
1010};
1011
1012static struct ti_clk gpt9_fck = {
1013 .name = "gpt9_fck",
1014 .type = TI_CLK_COMPOSITE,
1015 .data = &gpt9_fck_data,
1016};
1017
1018static struct ti_clk_divider dpll3_m3_ck_data = {
1019 .parent = "dpll3_ck",
1020 .bit_shift = 16,
1021 .max_div = 31,
1022 .reg = 0x1140,
1023 .module = TI_CLKM_CM,
1024 .flags = CLKF_INDEX_STARTS_AT_ONE,
1025};
1026
1027static struct ti_clk dpll3_m3_ck = {
1028 .name = "dpll3_m3_ck",
1029 .type = TI_CLK_DIVIDER,
1030 .data = &dpll3_m3_ck_data,
1031};
1032
1033static struct ti_clk_fixed_factor dpll3_m3x2_mul_ck_data = {
1034 .parent = "dpll3_m3_ck",
1035 .div = 1,
1036 .mult = 2,
1037};
1038
1039static struct ti_clk dpll3_m3x2_mul_ck = {
1040 .name = "dpll3_m3x2_mul_ck",
1041 .type = TI_CLK_FIXED_FACTOR,
1042 .data = &dpll3_m3x2_mul_ck_data,
1043};
1044
1045static struct ti_clk_gate sr2_fck_data = {
1046 .parent = "sys_ck",
1047 .bit_shift = 7,
1048 .reg = 0xc00,
1049 .module = TI_CLKM_CM,
1050 .flags = CLKF_WAIT,
1051};
1052
1053static struct ti_clk sr2_fck = {
1054 .name = "sr2_fck",
1055 .clkdm_name = "wkup_clkdm",
1056 .type = TI_CLK_GATE,
1057 .data = &sr2_fck_data,
1058};
1059
1060static struct ti_clk_fixed pclk_ck_data = {
1061 .frequency = 27000000,
1062};
1063
1064static struct ti_clk pclk_ck = {
1065 .name = "pclk_ck",
1066 .type = TI_CLK_FIXED,
1067 .data = &pclk_ck_data,
1068};
1069
1070static struct ti_clk_gate wdt2_ick_data = {
1071 .parent = "wkup_l4_ick",
1072 .bit_shift = 5,
1073 .reg = 0xc10,
1074 .module = TI_CLKM_CM,
1075 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1076};
1077
1078static struct ti_clk wdt2_ick = {
1079 .name = "wdt2_ick",
1080 .clkdm_name = "wkup_clkdm",
1081 .type = TI_CLK_GATE,
1082 .data = &wdt2_ick_data,
1083};
1084
1085static struct ti_clk_fixed_factor core_l3_ick_data = {
1086 .parent = "l3_ick",
1087 .div = 1,
1088 .mult = 1,
1089};
1090
1091static struct ti_clk core_l3_ick = {
1092 .name = "core_l3_ick",
1093 .type = TI_CLK_FIXED_FACTOR,
1094 .data = &core_l3_ick_data,
1095};
1096
1097static struct ti_clk_gate mcspi4_fck_data = {
1098 .parent = "core_48m_fck",
1099 .bit_shift = 21,
1100 .reg = 0xa00,
1101 .module = TI_CLKM_CM,
1102 .flags = CLKF_WAIT,
1103};
1104
1105static struct ti_clk mcspi4_fck = {
1106 .name = "mcspi4_fck",
1107 .clkdm_name = "core_l4_clkdm",
1108 .type = TI_CLK_GATE,
1109 .data = &mcspi4_fck_data,
1110};
1111
1112static struct ti_clk_fixed_factor per_48m_fck_data = {
1113 .parent = "omap_48m_fck",
1114 .div = 1,
1115 .mult = 1,
1116};
1117
1118static struct ti_clk per_48m_fck = {
1119 .name = "per_48m_fck",
1120 .type = TI_CLK_FIXED_FACTOR,
1121 .data = &per_48m_fck_data,
1122};
1123
1124static struct ti_clk_gate uart4_fck_data = {
1125 .parent = "per_48m_fck",
1126 .bit_shift = 18,
1127 .reg = 0x1000,
1128 .module = TI_CLKM_CM,
1129 .flags = CLKF_WAIT,
1130};
1131
1132static struct ti_clk uart4_fck = {
1133 .name = "uart4_fck",
1134 .clkdm_name = "per_clkdm",
1135 .type = TI_CLK_GATE,
1136 .data = &uart4_fck_data,
1137};
1138
1139static struct ti_clk_fixed_factor omap_96m_d10_fck_data = {
1140 .parent = "omap_96m_fck",
1141 .div = 10,
1142 .mult = 1,
1143};
1144
1145static struct ti_clk omap_96m_d10_fck = {
1146 .name = "omap_96m_d10_fck",
1147 .type = TI_CLK_FIXED_FACTOR,
1148 .data = &omap_96m_d10_fck_data,
1149};
1150
1151static struct ti_clk_gate usim_gate_fck_data = {
1152 .parent = "omap_96m_fck",
1153 .bit_shift = 9,
1154 .reg = 0xc00,
1155 .module = TI_CLKM_CM,
1156};
1157
1158static struct ti_clk_fixed_factor per_l4_ick_data = {
1159 .parent = "l4_ick",
1160 .div = 1,
1161 .mult = 1,
1162};
1163
1164static struct ti_clk per_l4_ick = {
1165 .name = "per_l4_ick",
1166 .type = TI_CLK_FIXED_FACTOR,
1167 .data = &per_l4_ick_data,
1168};
1169
1170static struct ti_clk_gate gpt5_ick_data = {
1171 .parent = "per_l4_ick",
1172 .bit_shift = 6,
1173 .reg = 0x1010,
1174 .module = TI_CLKM_CM,
1175 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1176};
1177
1178static struct ti_clk gpt5_ick = {
1179 .name = "gpt5_ick",
1180 .clkdm_name = "per_clkdm",
1181 .type = TI_CLK_GATE,
1182 .data = &gpt5_ick_data,
1183};
1184
1185static struct ti_clk_gate mcspi2_ick_data = {
1186 .parent = "core_l4_ick",
1187 .bit_shift = 19,
1188 .reg = 0xa10,
1189 .module = TI_CLKM_CM,
1190 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1191};
1192
1193static struct ti_clk mcspi2_ick = {
1194 .name = "mcspi2_ick",
1195 .clkdm_name = "core_l4_clkdm",
1196 .type = TI_CLK_GATE,
1197 .data = &mcspi2_ick_data,
1198};
1199
1200static struct ti_clk_fixed_factor ssi_l4_ick_data = {
1201 .parent = "l4_ick",
1202 .div = 1,
1203 .mult = 1,
1204};
1205
1206static struct ti_clk ssi_l4_ick = {
1207 .name = "ssi_l4_ick",
1208 .clkdm_name = "core_l4_clkdm",
1209 .type = TI_CLK_FIXED_FACTOR,
1210 .data = &ssi_l4_ick_data,
1211};
1212
1213static struct ti_clk_gate ssi_ick_3430es1_data = {
1214 .parent = "ssi_l4_ick",
1215 .bit_shift = 0,
1216 .reg = 0xa10,
1217 .module = TI_CLKM_CM,
1218 .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
1219};
1220
1221static struct ti_clk ssi_ick_3430es1 = {
1222 .name = "ssi_ick",
1223 .clkdm_name = "core_l4_clkdm",
1224 .type = TI_CLK_GATE,
1225 .data = &ssi_ick_3430es1_data,
1226};
1227
1228static struct ti_clk_gate i2c2_fck_data = {
1229 .parent = "core_96m_fck",
1230 .bit_shift = 16,
1231 .reg = 0xa00,
1232 .module = TI_CLKM_CM,
1233 .flags = CLKF_WAIT,
1234};
1235
1236static struct ti_clk i2c2_fck = {
1237 .name = "i2c2_fck",
1238 .clkdm_name = "core_l4_clkdm",
1239 .type = TI_CLK_GATE,
1240 .data = &i2c2_fck_data,
1241};
1242
1243static struct ti_clk_divider dpll1_fck_data = {
1244 .parent = "core_ck",
1245 .bit_shift = 19,
1246 .max_div = 7,
1247 .reg = 0x940,
1248 .module = TI_CLKM_CM,
1249 .flags = CLKF_INDEX_STARTS_AT_ONE,
1250};
1251
1252static struct ti_clk dpll1_fck = {
1253 .name = "dpll1_fck",
1254 .type = TI_CLK_DIVIDER,
1255 .data = &dpll1_fck_data,
1256};
1257
1258static const char *dpll1_ck_parents[] = {
1259 "sys_ck",
1260 "dpll1_fck",
1261};
1262
1263static struct ti_clk_dpll dpll1_ck_data = {
1264 .num_parents = ARRAY_SIZE(dpll1_ck_parents),
1265 .control_reg = 0x904,
1266 .idlest_reg = 0x924,
1267 .mult_div1_reg = 0x940,
1268 .autoidle_reg = 0x934,
1269 .module = TI_CLKM_CM,
1270 .parents = dpll1_ck_parents,
1271 .freqsel_mask = 0xf0,
1272 .modes = 0xa0,
1273 .div1_mask = 0x7f,
1274 .idlest_mask = 0x1,
1275 .auto_recal_bit = 0x3,
1276 .max_divider = 0x80,
1277 .min_divider = 0x1,
1278 .recal_en_bit = 0x7,
1279 .max_multiplier = 0x7ff,
1280 .enable_mask = 0x7,
1281 .mult_mask = 0x7ff00,
1282 .recal_st_bit = 0x7,
1283 .autoidle_mask = 0x7,
1284};
1285
1286static struct ti_clk dpll1_ck = {
1287 .name = "dpll1_ck",
1288 .clkdm_name = "dpll1_clkdm",
1289 .type = TI_CLK_DPLL,
1290 .data = &dpll1_ck_data,
1291};
1292
1293static struct ti_clk_fixed secure_32k_fck_data = {
1294 .frequency = 32768,
1295};
1296
1297static struct ti_clk secure_32k_fck = {
1298 .name = "secure_32k_fck",
1299 .type = TI_CLK_FIXED,
1300 .data = &secure_32k_fck_data,
1301};
1302
1303static struct ti_clk_gate gpio5_ick_data = {
1304 .parent = "per_l4_ick",
1305 .bit_shift = 16,
1306 .reg = 0x1010,
1307 .module = TI_CLKM_CM,
1308 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1309};
1310
1311static struct ti_clk gpio5_ick = {
1312 .name = "gpio5_ick",
1313 .clkdm_name = "per_clkdm",
1314 .type = TI_CLK_GATE,
1315 .data = &gpio5_ick_data,
1316};
1317
1318static struct ti_clk_divider dpll4_m4_ck_data = {
1319 .parent = "dpll4_ck",
1320 .max_div = 32,
1321 .reg = 0xe40,
1322 .module = TI_CLKM_CM,
1323 .flags = CLKF_INDEX_STARTS_AT_ONE,
1324};
1325
1326static struct ti_clk dpll4_m4_ck = {
1327 .name = "dpll4_m4_ck",
1328 .type = TI_CLK_DIVIDER,
1329 .data = &dpll4_m4_ck_data,
1330};
1331
1332static struct ti_clk_fixed_factor dpll4_m4x2_mul_ck_data = {
1333 .parent = "dpll4_m4_ck",
1334 .div = 1,
1335 .mult = 2,
1336 .flags = CLKF_SET_RATE_PARENT,
1337};
1338
1339static struct ti_clk dpll4_m4x2_mul_ck = {
1340 .name = "dpll4_m4x2_mul_ck",
1341 .type = TI_CLK_FIXED_FACTOR,
1342 .data = &dpll4_m4x2_mul_ck_data,
1343};
1344
1345static struct ti_clk_gate dpll4_m4x2_ck_data = {
1346 .parent = "dpll4_m4x2_mul_ck",
1347 .bit_shift = 0x1d,
1348 .reg = 0xd00,
1349 .module = TI_CLKM_CM,
1350 .flags = CLKF_SET_RATE_PARENT | CLKF_SET_BIT_TO_DISABLE,
1351};
1352
1353static struct ti_clk dpll4_m4x2_ck = {
1354 .name = "dpll4_m4x2_ck",
1355 .type = TI_CLK_GATE,
1356 .data = &dpll4_m4x2_ck_data,
1357};
1358
1359static struct ti_clk_gate dss1_alwon_fck_3430es2_data = {
1360 .parent = "dpll4_m4x2_ck",
1361 .bit_shift = 0,
1362 .reg = 0xe00,
1363 .module = TI_CLKM_CM,
1364 .flags = CLKF_DSS | CLKF_SET_RATE_PARENT,
1365};
1366
1367static struct ti_clk dss1_alwon_fck_3430es2 = {
1368 .name = "dss1_alwon_fck",
1369 .clkdm_name = "dss_clkdm",
1370 .type = TI_CLK_GATE,
1371 .data = &dss1_alwon_fck_3430es2_data,
1372};
1373
1374static struct ti_clk_gate uart3_ick_data = {
1375 .parent = "per_l4_ick",
1376 .bit_shift = 11,
1377 .reg = 0x1010,
1378 .module = TI_CLKM_CM,
1379 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1380};
1381
1382static struct ti_clk uart3_ick = {
1383 .name = "uart3_ick",
1384 .clkdm_name = "per_clkdm",
1385 .type = TI_CLK_GATE,
1386 .data = &uart3_ick_data,
1387};
1388
1389static struct ti_clk_divider dpll4_m3_ck_data = {
1390 .parent = "dpll4_ck",
1391 .bit_shift = 8,
1392 .max_div = 32,
1393 .reg = 0xe40,
1394 .module = TI_CLKM_CM,
1395 .flags = CLKF_INDEX_STARTS_AT_ONE,
1396};
1397
1398static struct ti_clk dpll4_m3_ck = {
1399 .name = "dpll4_m3_ck",
1400 .type = TI_CLK_DIVIDER,
1401 .data = &dpll4_m3_ck_data,
1402};
1403
1404static struct ti_clk_gate mcbsp3_ick_data = {
1405 .parent = "per_l4_ick",
1406 .bit_shift = 1,
1407 .reg = 0x1010,
1408 .module = TI_CLKM_CM,
1409 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1410};
1411
1412static struct ti_clk mcbsp3_ick = {
1413 .name = "mcbsp3_ick",
1414 .clkdm_name = "per_clkdm",
1415 .type = TI_CLK_GATE,
1416 .data = &mcbsp3_ick_data,
1417};
1418
1419static struct ti_clk_gate gpio3_dbck_data = {
1420 .parent = "per_32k_alwon_fck",
1421 .bit_shift = 14,
1422 .reg = 0x1000,
1423 .module = TI_CLKM_CM,
1424};
1425
1426static struct ti_clk gpio3_dbck = {
1427 .name = "gpio3_dbck",
1428 .clkdm_name = "per_clkdm",
1429 .type = TI_CLK_GATE,
1430 .data = &gpio3_dbck_data,
1431};
1432
1433static struct ti_clk_gate fac_ick_data = {
1434 .parent = "core_l4_ick",
1435 .bit_shift = 8,
1436 .reg = 0xa10,
1437 .module = TI_CLKM_CM,
1438 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1439};
1440
1441static struct ti_clk fac_ick = {
1442 .name = "fac_ick",
1443 .clkdm_name = "core_l4_clkdm",
1444 .type = TI_CLK_GATE,
1445 .data = &fac_ick_data,
1446};
1447
1448static struct ti_clk_gate clkout2_src_gate_ck_data = {
1449 .parent = "core_ck",
1450 .bit_shift = 7,
1451 .reg = 0xd70,
1452 .module = TI_CLKM_CM,
1453 .flags = CLKF_NO_WAIT,
1454};
1455
1456static struct ti_clk_fixed_factor dpll4_m3x2_mul_ck_data = {
1457 .parent = "dpll4_m3_ck",
1458 .div = 1,
1459 .mult = 2,
1460};
1461
1462static struct ti_clk dpll4_m3x2_mul_ck = {
1463 .name = "dpll4_m3x2_mul_ck",
1464 .type = TI_CLK_FIXED_FACTOR,
1465 .data = &dpll4_m3x2_mul_ck_data,
1466};
1467
1468static struct ti_clk_gate dpll4_m3x2_ck_data = {
1469 .parent = "dpll4_m3x2_mul_ck",
1470 .bit_shift = 0x1c,
1471 .reg = 0xd00,
1472 .module = TI_CLKM_CM,
1473 .flags = CLKF_SET_BIT_TO_DISABLE,
1474};
1475
1476static struct ti_clk dpll4_m3x2_ck = {
1477 .name = "dpll4_m3x2_ck",
1478 .type = TI_CLK_GATE,
1479 .data = &dpll4_m3x2_ck_data,
1480};
1481
1482static const char *omap_54m_fck_parents[] = {
1483 "dpll4_m3x2_ck",
1484 "sys_altclk",
1485};
1486
1487static struct ti_clk_mux omap_54m_fck_data = {
1488 .bit_shift = 5,
1489 .num_parents = ARRAY_SIZE(omap_54m_fck_parents),
1490 .reg = 0xd40,
1491 .module = TI_CLKM_CM,
1492 .parents = omap_54m_fck_parents,
1493};
1494
1495static struct ti_clk omap_54m_fck = {
1496 .name = "omap_54m_fck",
1497 .type = TI_CLK_MUX,
1498 .data = &omap_54m_fck_data,
1499};
1500
1501static const char *clkout2_src_mux_ck_parents[] = {
1502 "core_ck",
1503 "sys_ck",
1504 "cm_96m_fck",
1505 "omap_54m_fck",
1506};
1507
1508static struct ti_clk_mux clkout2_src_mux_ck_data = {
1509 .num_parents = ARRAY_SIZE(clkout2_src_mux_ck_parents),
1510 .reg = 0xd70,
1511 .module = TI_CLKM_CM,
1512 .parents = clkout2_src_mux_ck_parents,
1513};
1514
1515static struct ti_clk_composite clkout2_src_ck_data = {
1516 .mux = &clkout2_src_mux_ck_data,
1517 .gate = &clkout2_src_gate_ck_data,
1518};
1519
1520static struct ti_clk clkout2_src_ck = {
1521 .name = "clkout2_src_ck",
1522 .type = TI_CLK_COMPOSITE,
1523 .data = &clkout2_src_ck_data,
1524};
1525
1526static struct ti_clk_gate i2c1_fck_data = {
1527 .parent = "core_96m_fck",
1528 .bit_shift = 15,
1529 .reg = 0xa00,
1530 .module = TI_CLKM_CM,
1531 .flags = CLKF_WAIT,
1532};
1533
1534static struct ti_clk i2c1_fck = {
1535 .name = "i2c1_fck",
1536 .clkdm_name = "core_l4_clkdm",
1537 .type = TI_CLK_GATE,
1538 .data = &i2c1_fck_data,
1539};
1540
1541static struct ti_clk_gate wdt3_fck_data = {
1542 .parent = "per_32k_alwon_fck",
1543 .bit_shift = 12,
1544 .reg = 0x1000,
1545 .module = TI_CLKM_CM,
1546 .flags = CLKF_WAIT,
1547};
1548
1549static struct ti_clk wdt3_fck = {
1550 .name = "wdt3_fck",
1551 .clkdm_name = "per_clkdm",
1552 .type = TI_CLK_GATE,
1553 .data = &wdt3_fck_data,
1554};
1555
1556static struct ti_clk_gate gpt7_gate_fck_data = {
1557 .parent = "sys_ck",
1558 .bit_shift = 8,
1559 .reg = 0x1000,
1560 .module = TI_CLKM_CM,
1561};
1562
1563static const char *gpt7_mux_fck_parents[] = {
1564 "omap_32k_fck",
1565 "sys_ck",
1566};
1567
1568static struct ti_clk_mux gpt7_mux_fck_data = {
1569 .bit_shift = 5,
1570 .num_parents = ARRAY_SIZE(gpt7_mux_fck_parents),
1571 .reg = 0x1040,
1572 .module = TI_CLKM_CM,
1573 .parents = gpt7_mux_fck_parents,
1574};
1575
1576static struct ti_clk_composite gpt7_fck_data = {
1577 .mux = &gpt7_mux_fck_data,
1578 .gate = &gpt7_gate_fck_data,
1579};
1580
1581static struct ti_clk gpt7_fck = {
1582 .name = "gpt7_fck",
1583 .type = TI_CLK_COMPOSITE,
1584 .data = &gpt7_fck_data,
1585};
1586
1587static struct ti_clk_gate usb_l4_gate_ick_data = {
1588 .parent = "l4_ick",
1589 .bit_shift = 5,
1590 .reg = 0xa10,
1591 .module = TI_CLKM_CM,
1592 .flags = CLKF_INTERFACE,
1593};
1594
1595static struct ti_clk_divider usb_l4_div_ick_data = {
1596 .parent = "l4_ick",
1597 .bit_shift = 4,
1598 .max_div = 1,
1599 .reg = 0xa40,
1600 .module = TI_CLKM_CM,
1601 .flags = CLKF_INDEX_STARTS_AT_ONE,
1602};
1603
1604static struct ti_clk_composite usb_l4_ick_data = {
1605 .gate = &usb_l4_gate_ick_data,
1606 .divider = &usb_l4_div_ick_data,
1607};
1608
1609static struct ti_clk usb_l4_ick = {
1610 .name = "usb_l4_ick",
1611 .type = TI_CLK_COMPOSITE,
1612 .data = &usb_l4_ick_data,
1613};
1614
1615static struct ti_clk_gate uart4_ick_data = {
1616 .parent = "per_l4_ick",
1617 .bit_shift = 18,
1618 .reg = 0x1010,
1619 .module = TI_CLKM_CM,
1620 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1621};
1622
1623static struct ti_clk uart4_ick = {
1624 .name = "uart4_ick",
1625 .clkdm_name = "per_clkdm",
1626 .type = TI_CLK_GATE,
1627 .data = &uart4_ick_data,
1628};
1629
1630static struct ti_clk_fixed dummy_ck_data = {
1631 .frequency = 0,
1632};
1633
1634static struct ti_clk dummy_ck = {
1635 .name = "dummy_ck",
1636 .type = TI_CLK_FIXED,
1637 .data = &dummy_ck_data,
1638};
1639
1640static const char *gpt3_mux_fck_parents[] = {
1641 "omap_32k_fck",
1642 "sys_ck",
1643};
1644
1645static struct ti_clk_mux gpt3_mux_fck_data = {
1646 .bit_shift = 1,
1647 .num_parents = ARRAY_SIZE(gpt3_mux_fck_parents),
1648 .reg = 0x1040,
1649 .module = TI_CLKM_CM,
1650 .parents = gpt3_mux_fck_parents,
1651};
1652
1653static struct ti_clk_gate gpt9_ick_data = {
1654 .parent = "per_l4_ick",
1655 .bit_shift = 10,
1656 .reg = 0x1010,
1657 .module = TI_CLKM_CM,
1658 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1659};
1660
1661static struct ti_clk gpt9_ick = {
1662 .name = "gpt9_ick",
1663 .clkdm_name = "per_clkdm",
1664 .type = TI_CLK_GATE,
1665 .data = &gpt9_ick_data,
1666};
1667
1668static struct ti_clk_gate gpt10_gate_fck_data = {
1669 .parent = "sys_ck",
1670 .bit_shift = 11,
1671 .reg = 0xa00,
1672 .module = TI_CLKM_CM,
1673};
1674
1675static struct ti_clk_gate dss_ick_3430es1_data = {
1676 .parent = "l4_ick",
1677 .bit_shift = 0,
1678 .reg = 0xe10,
1679 .module = TI_CLKM_CM,
1680 .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
1681};
1682
1683static struct ti_clk dss_ick_3430es1 = {
1684 .name = "dss_ick",
1685 .clkdm_name = "dss_clkdm",
1686 .type = TI_CLK_GATE,
1687 .data = &dss_ick_3430es1_data,
1688};
1689
1690static struct ti_clk_gate gpt11_ick_data = {
1691 .parent = "core_l4_ick",
1692 .bit_shift = 12,
1693 .reg = 0xa10,
1694 .module = TI_CLKM_CM,
1695 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1696};
1697
1698static struct ti_clk gpt11_ick = {
1699 .name = "gpt11_ick",
1700 .clkdm_name = "core_l4_clkdm",
1701 .type = TI_CLK_GATE,
1702 .data = &gpt11_ick_data,
1703};
1704
1705static struct ti_clk_divider dpll2_fck_data = {
1706 .parent = "core_ck",
1707 .bit_shift = 19,
1708 .max_div = 7,
1709 .reg = 0x40,
1710 .module = TI_CLKM_CM,
1711 .flags = CLKF_INDEX_STARTS_AT_ONE,
1712};
1713
1714static struct ti_clk dpll2_fck = {
1715 .name = "dpll2_fck",
1716 .type = TI_CLK_DIVIDER,
1717 .data = &dpll2_fck_data,
1718};
1719
1720static struct ti_clk_gate uart1_fck_data = {
1721 .parent = "core_48m_fck",
1722 .bit_shift = 13,
1723 .reg = 0xa00,
1724 .module = TI_CLKM_CM,
1725 .flags = CLKF_WAIT,
1726};
1727
1728static struct ti_clk uart1_fck = {
1729 .name = "uart1_fck",
1730 .clkdm_name = "core_l4_clkdm",
1731 .type = TI_CLK_GATE,
1732 .data = &uart1_fck_data,
1733};
1734
1735static struct ti_clk_gate hsotgusb_ick_3430es1_data = {
1736 .parent = "core_l3_ick",
1737 .bit_shift = 4,
1738 .reg = 0xa10,
1739 .module = TI_CLKM_CM,
1740 .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
1741};
1742
1743static struct ti_clk hsotgusb_ick_3430es1 = {
1744 .name = "hsotgusb_ick_3430es1",
1745 .clkdm_name = "core_l3_clkdm",
1746 .type = TI_CLK_GATE,
1747 .data = &hsotgusb_ick_3430es1_data,
1748};
1749
1750static struct ti_clk_gate gpio2_ick_data = {
1751 .parent = "per_l4_ick",
1752 .bit_shift = 13,
1753 .reg = 0x1010,
1754 .module = TI_CLKM_CM,
1755 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1756};
1757
1758static struct ti_clk gpio2_ick = {
1759 .name = "gpio2_ick",
1760 .clkdm_name = "per_clkdm",
1761 .type = TI_CLK_GATE,
1762 .data = &gpio2_ick_data,
1763};
1764
1765static struct ti_clk_gate mmchs1_ick_data = {
1766 .parent = "core_l4_ick",
1767 .bit_shift = 24,
1768 .reg = 0xa10,
1769 .module = TI_CLKM_CM,
1770 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1771};
1772
1773static struct ti_clk mmchs1_ick = {
1774 .name = "mmchs1_ick",
1775 .clkdm_name = "core_l4_clkdm",
1776 .type = TI_CLK_GATE,
1777 .data = &mmchs1_ick_data,
1778};
1779
1780static struct ti_clk_gate modem_fck_data = {
1781 .parent = "sys_ck",
1782 .bit_shift = 31,
1783 .reg = 0xa00,
1784 .module = TI_CLKM_CM,
1785 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1786};
1787
1788static struct ti_clk modem_fck = {
1789 .name = "modem_fck",
1790 .clkdm_name = "d2d_clkdm",
1791 .type = TI_CLK_GATE,
1792 .data = &modem_fck_data,
1793};
1794
1795static struct ti_clk_gate mcbsp4_ick_data = {
1796 .parent = "per_l4_ick",
1797 .bit_shift = 2,
1798 .reg = 0x1010,
1799 .module = TI_CLKM_CM,
1800 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1801};
1802
1803static struct ti_clk mcbsp4_ick = {
1804 .name = "mcbsp4_ick",
1805 .clkdm_name = "per_clkdm",
1806 .type = TI_CLK_GATE,
1807 .data = &mcbsp4_ick_data,
1808};
1809
1810static struct ti_clk_gate gpio1_ick_data = {
1811 .parent = "wkup_l4_ick",
1812 .bit_shift = 3,
1813 .reg = 0xc10,
1814 .module = TI_CLKM_CM,
1815 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1816};
1817
1818static struct ti_clk gpio1_ick = {
1819 .name = "gpio1_ick",
1820 .clkdm_name = "wkup_clkdm",
1821 .type = TI_CLK_GATE,
1822 .data = &gpio1_ick_data,
1823};
1824
1825static const char *gpt6_mux_fck_parents[] = {
1826 "omap_32k_fck",
1827 "sys_ck",
1828};
1829
1830static struct ti_clk_mux gpt6_mux_fck_data = {
1831 .bit_shift = 4,
1832 .num_parents = ARRAY_SIZE(gpt6_mux_fck_parents),
1833 .reg = 0x1040,
1834 .module = TI_CLKM_CM,
1835 .parents = gpt6_mux_fck_parents,
1836};
1837
1838static struct ti_clk_fixed_factor dpll1_x2_ck_data = {
1839 .parent = "dpll1_ck",
1840 .div = 1,
1841 .mult = 2,
1842};
1843
1844static struct ti_clk dpll1_x2_ck = {
1845 .name = "dpll1_x2_ck",
1846 .type = TI_CLK_FIXED_FACTOR,
1847 .data = &dpll1_x2_ck_data,
1848};
1849
1850static struct ti_clk_divider dpll1_x2m2_ck_data = {
1851 .parent = "dpll1_x2_ck",
1852 .max_div = 31,
1853 .reg = 0x944,
1854 .module = TI_CLKM_CM,
1855 .flags = CLKF_INDEX_STARTS_AT_ONE,
1856};
1857
1858static struct ti_clk dpll1_x2m2_ck = {
1859 .name = "dpll1_x2m2_ck",
1860 .type = TI_CLK_DIVIDER,
1861 .data = &dpll1_x2m2_ck_data,
1862};
1863
1864static struct ti_clk_fixed_factor mpu_ck_data = {
1865 .parent = "dpll1_x2m2_ck",
1866 .div = 1,
1867 .mult = 1,
1868};
1869
1870static struct ti_clk mpu_ck = {
1871 .name = "mpu_ck",
1872 .type = TI_CLK_FIXED_FACTOR,
1873 .data = &mpu_ck_data,
1874};
1875
1876static struct ti_clk_divider arm_fck_data = {
1877 .parent = "mpu_ck",
1878 .max_div = 2,
1879 .reg = 0x924,
1880 .module = TI_CLKM_CM,
1881};
1882
1883static struct ti_clk arm_fck = {
1884 .name = "arm_fck",
1885 .type = TI_CLK_DIVIDER,
1886 .data = &arm_fck_data,
1887};
1888
1889static struct ti_clk_fixed_factor core_d3_ck_data = {
1890 .parent = "core_ck",
1891 .div = 3,
1892 .mult = 1,
1893};
1894
1895static struct ti_clk core_d3_ck = {
1896 .name = "core_d3_ck",
1897 .type = TI_CLK_FIXED_FACTOR,
1898 .data = &core_d3_ck_data,
1899};
1900
1901static struct ti_clk_gate gpt11_gate_fck_data = {
1902 .parent = "sys_ck",
1903 .bit_shift = 12,
1904 .reg = 0xa00,
1905 .module = TI_CLKM_CM,
1906};
1907
1908static const char *gpt11_mux_fck_parents[] = {
1909 "omap_32k_fck",
1910 "sys_ck",
1911};
1912
1913static struct ti_clk_mux gpt11_mux_fck_data = {
1914 .bit_shift = 7,
1915 .num_parents = ARRAY_SIZE(gpt11_mux_fck_parents),
1916 .reg = 0xa40,
1917 .module = TI_CLKM_CM,
1918 .parents = gpt11_mux_fck_parents,
1919};
1920
1921static struct ti_clk_composite gpt11_fck_data = {
1922 .mux = &gpt11_mux_fck_data,
1923 .gate = &gpt11_gate_fck_data,
1924};
1925
1926static struct ti_clk gpt11_fck = {
1927 .name = "gpt11_fck",
1928 .type = TI_CLK_COMPOSITE,
1929 .data = &gpt11_fck_data,
1930};
1931
1932static struct ti_clk_fixed_factor core_d6_ck_data = {
1933 .parent = "core_ck",
1934 .div = 6,
1935 .mult = 1,
1936};
1937
1938static struct ti_clk core_d6_ck = {
1939 .name = "core_d6_ck",
1940 .type = TI_CLK_FIXED_FACTOR,
1941 .data = &core_d6_ck_data,
1942};
1943
1944static struct ti_clk_gate uart4_fck_am35xx_data = {
1945 .parent = "core_48m_fck",
1946 .bit_shift = 23,
1947 .reg = 0xa00,
1948 .module = TI_CLKM_CM,
1949 .flags = CLKF_WAIT,
1950};
1951
1952static struct ti_clk uart4_fck_am35xx = {
1953 .name = "uart4_fck_am35xx",
1954 .clkdm_name = "core_l4_clkdm",
1955 .type = TI_CLK_GATE,
1956 .data = &uart4_fck_am35xx_data,
1957};
1958
1959static struct ti_clk_gate dpll3_m3x2_ck_data = {
1960 .parent = "dpll3_m3x2_mul_ck",
1961 .bit_shift = 0xc,
1962 .reg = 0xd00,
1963 .module = TI_CLKM_CM,
1964 .flags = CLKF_SET_BIT_TO_DISABLE,
1965};
1966
1967static struct ti_clk dpll3_m3x2_ck = {
1968 .name = "dpll3_m3x2_ck",
1969 .type = TI_CLK_GATE,
1970 .data = &dpll3_m3x2_ck_data,
1971};
1972
1973static struct ti_clk_fixed_factor emu_core_alwon_ck_data = {
1974 .parent = "dpll3_m3x2_ck",
1975 .div = 1,
1976 .mult = 1,
1977};
1978
1979static struct ti_clk emu_core_alwon_ck = {
1980 .name = "emu_core_alwon_ck",
1981 .type = TI_CLK_FIXED_FACTOR,
1982 .data = &emu_core_alwon_ck_data,
1983};
1984
1985static struct ti_clk_divider dpll4_m6_ck_data = {
1986 .parent = "dpll4_ck",
1987 .bit_shift = 24,
1988 .max_div = 63,
1989 .reg = 0x1140,
1990 .module = TI_CLKM_CM,
1991 .flags = CLKF_INDEX_STARTS_AT_ONE,
1992};
1993
1994static struct ti_clk dpll4_m6_ck = {
1995 .name = "dpll4_m6_ck",
1996 .type = TI_CLK_DIVIDER,
1997 .data = &dpll4_m6_ck_data,
1998};
1999
2000static struct ti_clk_fixed_factor dpll4_m6x2_mul_ck_data = {
2001 .parent = "dpll4_m6_ck",
2002 .div = 1,
2003 .mult = 2,
2004};
2005
2006static struct ti_clk dpll4_m6x2_mul_ck = {
2007 .name = "dpll4_m6x2_mul_ck",
2008 .type = TI_CLK_FIXED_FACTOR,
2009 .data = &dpll4_m6x2_mul_ck_data,
2010};
2011
2012static struct ti_clk_gate dpll4_m6x2_ck_data = {
2013 .parent = "dpll4_m6x2_mul_ck",
2014 .bit_shift = 0x1f,
2015 .reg = 0xd00,
2016 .module = TI_CLKM_CM,
2017 .flags = CLKF_SET_BIT_TO_DISABLE,
2018};
2019
2020static struct ti_clk dpll4_m6x2_ck = {
2021 .name = "dpll4_m6x2_ck",
2022 .type = TI_CLK_GATE,
2023 .data = &dpll4_m6x2_ck_data,
2024};
2025
2026static struct ti_clk_fixed_factor emu_per_alwon_ck_data = {
2027 .parent = "dpll4_m6x2_ck",
2028 .div = 1,
2029 .mult = 1,
2030};
2031
2032static struct ti_clk emu_per_alwon_ck = {
2033 .name = "emu_per_alwon_ck",
2034 .type = TI_CLK_FIXED_FACTOR,
2035 .data = &emu_per_alwon_ck_data,
2036};
2037
2038static struct ti_clk_fixed_factor emu_mpu_alwon_ck_data = {
2039 .parent = "mpu_ck",
2040 .div = 1,
2041 .mult = 1,
2042};
2043
2044static struct ti_clk emu_mpu_alwon_ck = {
2045 .name = "emu_mpu_alwon_ck",
2046 .type = TI_CLK_FIXED_FACTOR,
2047 .data = &emu_mpu_alwon_ck_data,
2048};
2049
2050static const char *emu_src_mux_ck_parents[] = {
2051 "sys_ck",
2052 "emu_core_alwon_ck",
2053 "emu_per_alwon_ck",
2054 "emu_mpu_alwon_ck",
2055};
2056
2057static struct ti_clk_mux emu_src_mux_ck_data = {
2058 .num_parents = ARRAY_SIZE(emu_src_mux_ck_parents),
2059 .reg = 0x1140,
2060 .module = TI_CLKM_CM,
2061 .parents = emu_src_mux_ck_parents,
2062};
2063
2064static struct ti_clk emu_src_mux_ck = {
2065 .name = "emu_src_mux_ck",
2066 .type = TI_CLK_MUX,
2067 .data = &emu_src_mux_ck_data,
2068};
2069
2070static struct ti_clk_gate emu_src_ck_data = {
2071 .parent = "emu_src_mux_ck",
2072 .flags = CLKF_CLKDM,
2073};
2074
2075static struct ti_clk emu_src_ck = {
2076 .name = "emu_src_ck",
2077 .clkdm_name = "emu_clkdm",
2078 .type = TI_CLK_GATE,
2079 .data = &emu_src_ck_data,
2080};
2081
2082static struct ti_clk_divider atclk_fck_data = {
2083 .parent = "emu_src_ck",
2084 .bit_shift = 4,
2085 .max_div = 3,
2086 .reg = 0x1140,
2087 .module = TI_CLKM_CM,
2088 .flags = CLKF_INDEX_STARTS_AT_ONE,
2089};
2090
2091static struct ti_clk atclk_fck = {
2092 .name = "atclk_fck",
2093 .type = TI_CLK_DIVIDER,
2094 .data = &atclk_fck_data,
2095};
2096
2097static struct ti_clk_gate ipss_ick_data = {
2098 .parent = "core_l3_ick",
2099 .bit_shift = 4,
2100 .reg = 0xa10,
2101 .module = TI_CLKM_CM,
2102 .flags = CLKF_AM35XX | CLKF_INTERFACE,
2103};
2104
2105static struct ti_clk ipss_ick = {
2106 .name = "ipss_ick",
2107 .clkdm_name = "core_l3_clkdm",
2108 .type = TI_CLK_GATE,
2109 .data = &ipss_ick_data,
2110};
2111
2112static struct ti_clk_gate emac_ick_data = {
2113 .parent = "ipss_ick",
2114 .bit_shift = 1,
2115 .reg = 0x59c,
2116 .module = TI_CLKM_SCRM,
2117 .flags = CLKF_AM35XX,
2118};
2119
2120static struct ti_clk emac_ick = {
2121 .name = "emac_ick",
2122 .clkdm_name = "core_l3_clkdm",
2123 .type = TI_CLK_GATE,
2124 .data = &emac_ick_data,
2125};
2126
2127static struct ti_clk_gate vpfe_ick_data = {
2128 .parent = "ipss_ick",
2129 .bit_shift = 2,
2130 .reg = 0x59c,
2131 .module = TI_CLKM_SCRM,
2132 .flags = CLKF_AM35XX,
2133};
2134
2135static struct ti_clk vpfe_ick = {
2136 .name = "vpfe_ick",
2137 .clkdm_name = "core_l3_clkdm",
2138 .type = TI_CLK_GATE,
2139 .data = &vpfe_ick_data,
2140};
2141
2142static const char *dpll2_ck_parents[] = {
2143 "sys_ck",
2144 "dpll2_fck",
2145};
2146
2147static struct ti_clk_dpll dpll2_ck_data = {
2148 .num_parents = ARRAY_SIZE(dpll2_ck_parents),
2149 .control_reg = 0x4,
2150 .idlest_reg = 0x24,
2151 .mult_div1_reg = 0x40,
2152 .autoidle_reg = 0x34,
2153 .module = TI_CLKM_CM,
2154 .parents = dpll2_ck_parents,
2155 .freqsel_mask = 0xf0,
2156 .modes = 0xa2,
2157 .div1_mask = 0x7f,
2158 .idlest_mask = 0x1,
2159 .auto_recal_bit = 0x3,
2160 .max_divider = 0x80,
2161 .min_divider = 0x1,
2162 .recal_en_bit = 0x8,
2163 .max_multiplier = 0x7ff,
2164 .enable_mask = 0x7,
2165 .mult_mask = 0x7ff00,
2166 .recal_st_bit = 0x8,
2167 .autoidle_mask = 0x7,
2168};
2169
2170static struct ti_clk dpll2_ck = {
2171 .name = "dpll2_ck",
2172 .clkdm_name = "dpll2_clkdm",
2173 .type = TI_CLK_DPLL,
2174 .data = &dpll2_ck_data,
2175};
2176
2177static struct ti_clk_divider dpll2_m2_ck_data = {
2178 .parent = "dpll2_ck",
2179 .max_div = 31,
2180 .reg = 0x44,
2181 .module = TI_CLKM_CM,
2182 .flags = CLKF_INDEX_STARTS_AT_ONE,
2183};
2184
2185static struct ti_clk dpll2_m2_ck = {
2186 .name = "dpll2_m2_ck",
2187 .type = TI_CLK_DIVIDER,
2188 .data = &dpll2_m2_ck_data,
2189};
2190
2191static const char *mcbsp4_mux_fck_parents[] = {
2192 "per_96m_fck",
2193 "mcbsp_clks",
2194};
2195
2196static struct ti_clk_mux mcbsp4_mux_fck_data = {
2197 .bit_shift = 2,
2198 .num_parents = ARRAY_SIZE(mcbsp4_mux_fck_parents),
2199 .reg = 0x2d8,
2200 .module = TI_CLKM_SCRM,
2201 .parents = mcbsp4_mux_fck_parents,
2202};
2203
2204static const char *mcbsp1_mux_fck_parents[] = {
2205 "core_96m_fck",
2206 "mcbsp_clks",
2207};
2208
2209static struct ti_clk_mux mcbsp1_mux_fck_data = {
2210 .bit_shift = 2,
2211 .num_parents = ARRAY_SIZE(mcbsp1_mux_fck_parents),
2212 .reg = 0x274,
2213 .module = TI_CLKM_SCRM,
2214 .parents = mcbsp1_mux_fck_parents,
2215};
2216
2217static struct ti_clk_gate gpt8_gate_fck_data = {
2218 .parent = "sys_ck",
2219 .bit_shift = 9,
2220 .reg = 0x1000,
2221 .module = TI_CLKM_CM,
2222};
2223
2224static struct ti_clk_gate gpt8_ick_data = {
2225 .parent = "per_l4_ick",
2226 .bit_shift = 9,
2227 .reg = 0x1010,
2228 .module = TI_CLKM_CM,
2229 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2230};
2231
2232static struct ti_clk gpt8_ick = {
2233 .name = "gpt8_ick",
2234 .clkdm_name = "per_clkdm",
2235 .type = TI_CLK_GATE,
2236 .data = &gpt8_ick_data,
2237};
2238
2239static const char *gpt10_mux_fck_parents[] = {
2240 "omap_32k_fck",
2241 "sys_ck",
2242};
2243
2244static struct ti_clk_mux gpt10_mux_fck_data = {
2245 .bit_shift = 6,
2246 .num_parents = ARRAY_SIZE(gpt10_mux_fck_parents),
2247 .reg = 0xa40,
2248 .module = TI_CLKM_CM,
2249 .parents = gpt10_mux_fck_parents,
2250};
2251
2252static struct ti_clk_gate mmchs3_ick_data = {
2253 .parent = "core_l4_ick",
2254 .bit_shift = 30,
2255 .reg = 0xa10,
2256 .module = TI_CLKM_CM,
2257 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2258};
2259
2260static struct ti_clk mmchs3_ick = {
2261 .name = "mmchs3_ick",
2262 .clkdm_name = "core_l4_clkdm",
2263 .type = TI_CLK_GATE,
2264 .data = &mmchs3_ick_data,
2265};
2266
2267static struct ti_clk_gate gpio3_ick_data = {
2268 .parent = "per_l4_ick",
2269 .bit_shift = 14,
2270 .reg = 0x1010,
2271 .module = TI_CLKM_CM,
2272 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2273};
2274
2275static struct ti_clk gpio3_ick = {
2276 .name = "gpio3_ick",
2277 .clkdm_name = "per_clkdm",
2278 .type = TI_CLK_GATE,
2279 .data = &gpio3_ick_data,
2280};
2281
2282static const char *traceclk_src_fck_parents[] = {
2283 "sys_ck",
2284 "emu_core_alwon_ck",
2285 "emu_per_alwon_ck",
2286 "emu_mpu_alwon_ck",
2287};
2288
2289static struct ti_clk_mux traceclk_src_fck_data = {
2290 .bit_shift = 2,
2291 .num_parents = ARRAY_SIZE(traceclk_src_fck_parents),
2292 .reg = 0x1140,
2293 .module = TI_CLKM_CM,
2294 .parents = traceclk_src_fck_parents,
2295};
2296
2297static struct ti_clk traceclk_src_fck = {
2298 .name = "traceclk_src_fck",
2299 .type = TI_CLK_MUX,
2300 .data = &traceclk_src_fck_data,
2301};
2302
2303static struct ti_clk_divider traceclk_fck_data = {
2304 .parent = "traceclk_src_fck",
2305 .bit_shift = 11,
2306 .max_div = 7,
2307 .reg = 0x1140,
2308 .module = TI_CLKM_CM,
2309 .flags = CLKF_INDEX_STARTS_AT_ONE,
2310};
2311
2312static struct ti_clk traceclk_fck = {
2313 .name = "traceclk_fck",
2314 .type = TI_CLK_DIVIDER,
2315 .data = &traceclk_fck_data,
2316};
2317
2318static struct ti_clk_gate mcbsp5_gate_fck_data = {
2319 .parent = "mcbsp_clks",
2320 .bit_shift = 10,
2321 .reg = 0xa00,
2322 .module = TI_CLKM_CM,
2323};
2324
2325static struct ti_clk_gate sad2d_ick_data = {
2326 .parent = "l3_ick",
2327 .bit_shift = 3,
2328 .reg = 0xa10,
2329 .module = TI_CLKM_CM,
2330 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2331};
2332
2333static struct ti_clk sad2d_ick = {
2334 .name = "sad2d_ick",
2335 .clkdm_name = "d2d_clkdm",
2336 .type = TI_CLK_GATE,
2337 .data = &sad2d_ick_data,
2338};
2339
2340static const char *gpt1_mux_fck_parents[] = {
2341 "omap_32k_fck",
2342 "sys_ck",
2343};
2344
2345static struct ti_clk_mux gpt1_mux_fck_data = {
2346 .num_parents = ARRAY_SIZE(gpt1_mux_fck_parents),
2347 .reg = 0xc40,
2348 .module = TI_CLKM_CM,
2349 .parents = gpt1_mux_fck_parents,
2350};
2351
2352static struct ti_clk_gate hecc_ck_data = {
2353 .parent = "sys_ck",
2354 .bit_shift = 3,
2355 .reg = 0x59c,
2356 .module = TI_CLKM_SCRM,
2357 .flags = CLKF_AM35XX,
2358};
2359
2360static struct ti_clk hecc_ck = {
2361 .name = "hecc_ck",
2362 .clkdm_name = "core_l3_clkdm",
2363 .type = TI_CLK_GATE,
2364 .data = &hecc_ck_data,
2365};
2366
2367static struct ti_clk_gate gpt1_gate_fck_data = {
2368 .parent = "sys_ck",
2369 .bit_shift = 0,
2370 .reg = 0xc00,
2371 .module = TI_CLKM_CM,
2372};
2373
2374static struct ti_clk_composite gpt1_fck_data = {
2375 .mux = &gpt1_mux_fck_data,
2376 .gate = &gpt1_gate_fck_data,
2377};
2378
2379static struct ti_clk gpt1_fck = {
2380 .name = "gpt1_fck",
2381 .type = TI_CLK_COMPOSITE,
2382 .data = &gpt1_fck_data,
2383};
2384
2385static struct ti_clk_gate dpll4_m2x2_ck_omap36xx_data = {
2386 .parent = "dpll4_m2x2_mul_ck",
2387 .bit_shift = 0x1b,
2388 .reg = 0xd00,
2389 .module = TI_CLKM_CM,
2390 .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
2391};
2392
2393static struct ti_clk dpll4_m2x2_ck_omap36xx = {
2394 .name = "dpll4_m2x2_ck",
2395 .type = TI_CLK_GATE,
2396 .data = &dpll4_m2x2_ck_omap36xx_data,
2397 .patch = &dpll4_m2x2_ck,
2398};
2399
2400static struct ti_clk_divider gfx_l3_fck_data = {
2401 .parent = "l3_ick",
2402 .max_div = 7,
2403 .reg = 0xb40,
2404 .module = TI_CLKM_CM,
2405 .flags = CLKF_INDEX_STARTS_AT_ONE,
2406};
2407
2408static struct ti_clk gfx_l3_fck = {
2409 .name = "gfx_l3_fck",
2410 .type = TI_CLK_DIVIDER,
2411 .data = &gfx_l3_fck_data,
2412};
2413
2414static struct ti_clk_gate gfx_cg1_ck_data = {
2415 .parent = "gfx_l3_fck",
2416 .bit_shift = 1,
2417 .reg = 0xb00,
2418 .module = TI_CLKM_CM,
2419 .flags = CLKF_WAIT,
2420};
2421
2422static struct ti_clk gfx_cg1_ck = {
2423 .name = "gfx_cg1_ck",
2424 .clkdm_name = "gfx_3430es1_clkdm",
2425 .type = TI_CLK_GATE,
2426 .data = &gfx_cg1_ck_data,
2427};
2428
2429static struct ti_clk_gate mailboxes_ick_data = {
2430 .parent = "core_l4_ick",
2431 .bit_shift = 7,
2432 .reg = 0xa10,
2433 .module = TI_CLKM_CM,
2434 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2435};
2436
2437static struct ti_clk mailboxes_ick = {
2438 .name = "mailboxes_ick",
2439 .clkdm_name = "core_l4_clkdm",
2440 .type = TI_CLK_GATE,
2441 .data = &mailboxes_ick_data,
2442};
2443
2444static struct ti_clk_gate sha11_ick_data = {
2445 .parent = "security_l4_ick2",
2446 .bit_shift = 1,
2447 .reg = 0xa14,
2448 .module = TI_CLKM_CM,
2449 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2450};
2451
2452static struct ti_clk sha11_ick = {
2453 .name = "sha11_ick",
2454 .type = TI_CLK_GATE,
2455 .data = &sha11_ick_data,
2456};
2457
2458static struct ti_clk_gate hsotgusb_ick_am35xx_data = {
2459 .parent = "ipss_ick",
2460 .bit_shift = 0,
2461 .reg = 0x59c,
2462 .module = TI_CLKM_SCRM,
2463 .flags = CLKF_AM35XX,
2464};
2465
2466static struct ti_clk hsotgusb_ick_am35xx = {
2467 .name = "hsotgusb_ick_am35xx",
2468 .clkdm_name = "core_l3_clkdm",
2469 .type = TI_CLK_GATE,
2470 .data = &hsotgusb_ick_am35xx_data,
2471};
2472
2473static struct ti_clk_gate mmchs3_fck_data = {
2474 .parent = "core_96m_fck",
2475 .bit_shift = 30,
2476 .reg = 0xa00,
2477 .module = TI_CLKM_CM,
2478 .flags = CLKF_WAIT,
2479};
2480
2481static struct ti_clk mmchs3_fck = {
2482 .name = "mmchs3_fck",
2483 .clkdm_name = "core_l4_clkdm",
2484 .type = TI_CLK_GATE,
2485 .data = &mmchs3_fck_data,
2486};
2487
2488static struct ti_clk_divider pclk_fck_data = {
2489 .parent = "emu_src_ck",
2490 .bit_shift = 8,
2491 .max_div = 7,
2492 .reg = 0x1140,
2493 .module = TI_CLKM_CM,
2494 .flags = CLKF_INDEX_STARTS_AT_ONE,
2495};
2496
2497static struct ti_clk pclk_fck = {
2498 .name = "pclk_fck",
2499 .type = TI_CLK_DIVIDER,
2500 .data = &pclk_fck_data,
2501};
2502
2503static const char *dpll4_ck_omap36xx_parents[] = {
2504 "sys_ck",
2505 "sys_ck",
2506};
2507
2508static struct ti_clk_dpll dpll4_ck_omap36xx_data = {
2509 .num_parents = ARRAY_SIZE(dpll4_ck_omap36xx_parents),
2510 .control_reg = 0xd00,
2511 .idlest_reg = 0xd20,
2512 .mult_div1_reg = 0xd44,
2513 .autoidle_reg = 0xd30,
2514 .module = TI_CLKM_CM,
2515 .parents = dpll4_ck_omap36xx_parents,
2516 .modes = 0x82,
2517 .div1_mask = 0x7f,
2518 .idlest_mask = 0x2,
2519 .auto_recal_bit = 0x13,
2520 .max_divider = 0x80,
2521 .min_divider = 0x1,
2522 .recal_en_bit = 0x6,
2523 .max_multiplier = 0xfff,
2524 .enable_mask = 0x70000,
2525 .mult_mask = 0xfff00,
2526 .recal_st_bit = 0x6,
2527 .autoidle_mask = 0x38,
2528 .sddiv_mask = 0xff000000,
2529 .dco_mask = 0xe00000,
2530 .flags = CLKF_PER | CLKF_J_TYPE,
2531};
2532
2533static struct ti_clk dpll4_ck_omap36xx = {
2534 .name = "dpll4_ck",
2535 .type = TI_CLK_DPLL,
2536 .data = &dpll4_ck_omap36xx_data,
2537 .patch = &dpll4_ck,
2538};
2539
2540static struct ti_clk_gate uart3_fck_data = {
2541 .parent = "per_48m_fck",
2542 .bit_shift = 11,
2543 .reg = 0x1000,
2544 .module = TI_CLKM_CM,
2545 .flags = CLKF_WAIT,
2546};
2547
2548static struct ti_clk uart3_fck = {
2549 .name = "uart3_fck",
2550 .clkdm_name = "per_clkdm",
2551 .type = TI_CLK_GATE,
2552 .data = &uart3_fck_data,
2553};
2554
2555static struct ti_clk_fixed_factor wkup_32k_fck_data = {
2556 .parent = "omap_32k_fck",
2557 .div = 1,
2558 .mult = 1,
2559};
2560
2561static struct ti_clk wkup_32k_fck = {
2562 .name = "wkup_32k_fck",
2563 .type = TI_CLK_FIXED_FACTOR,
2564 .data = &wkup_32k_fck_data,
2565};
2566
2567static struct ti_clk_gate sys_clkout1_data = {
2568 .parent = "osc_sys_ck",
2569 .bit_shift = 7,
2570 .reg = 0xd70,
2571 .module = TI_CLKM_PRM,
2572};
2573
2574static struct ti_clk sys_clkout1 = {
2575 .name = "sys_clkout1",
2576 .type = TI_CLK_GATE,
2577 .data = &sys_clkout1_data,
2578};
2579
2580static struct ti_clk_fixed_factor gpmc_fck_data = {
2581 .parent = "core_l3_ick",
2582 .div = 1,
2583 .mult = 1,
2584};
2585
2586static struct ti_clk gpmc_fck = {
2587 .name = "gpmc_fck",
2588 .type = TI_CLK_FIXED_FACTOR,
2589 .data = &gpmc_fck_data,
2590};
2591
2592static struct ti_clk_fixed_factor dpll5_m2_d20_ck_data = {
2593 .parent = "dpll5_m2_ck",
2594 .div = 20,
2595 .mult = 1,
2596};
2597
2598static struct ti_clk dpll5_m2_d20_ck = {
2599 .name = "dpll5_m2_d20_ck",
2600 .type = TI_CLK_FIXED_FACTOR,
2601 .data = &dpll5_m2_d20_ck_data,
2602};
2603
2604static struct ti_clk_gate dpll4_m5x2_ck_omap36xx_data = {
2605 .parent = "dpll4_m5x2_mul_ck",
2606 .bit_shift = 0x1e,
2607 .reg = 0xd00,
2608 .module = TI_CLKM_CM,
2609 .flags = CLKF_HSDIV | CLKF_SET_RATE_PARENT | CLKF_SET_BIT_TO_DISABLE,
2610};
2611
2612static struct ti_clk dpll4_m5x2_ck_omap36xx = {
2613 .name = "dpll4_m5x2_ck",
2614 .type = TI_CLK_GATE,
2615 .data = &dpll4_m5x2_ck_omap36xx_data,
2616 .patch = &dpll4_m5x2_ck,
2617};
2618
2619static struct ti_clk_gate ssi_ssr_gate_fck_3430es2_data = {
2620 .parent = "corex2_fck",
2621 .bit_shift = 0,
2622 .reg = 0xa00,
2623 .module = TI_CLKM_CM,
2624 .flags = CLKF_NO_WAIT,
2625};
2626
2627static struct ti_clk_gate uart1_ick_data = {
2628 .parent = "core_l4_ick",
2629 .bit_shift = 13,
2630 .reg = 0xa10,
2631 .module = TI_CLKM_CM,
2632 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2633};
2634
2635static struct ti_clk uart1_ick = {
2636 .name = "uart1_ick",
2637 .clkdm_name = "core_l4_clkdm",
2638 .type = TI_CLK_GATE,
2639 .data = &uart1_ick_data,
2640};
2641
2642static struct ti_clk_gate iva2_ck_data = {
2643 .parent = "dpll2_m2_ck",
2644 .bit_shift = 0,
2645 .reg = 0x0,
2646 .module = TI_CLKM_CM,
2647 .flags = CLKF_WAIT,
2648};
2649
2650static struct ti_clk iva2_ck = {
2651 .name = "iva2_ck",
2652 .clkdm_name = "iva2_clkdm",
2653 .type = TI_CLK_GATE,
2654 .data = &iva2_ck_data,
2655};
2656
2657static struct ti_clk_gate pka_ick_data = {
2658 .parent = "security_l3_ick",
2659 .bit_shift = 4,
2660 .reg = 0xa14,
2661 .module = TI_CLKM_CM,
2662 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2663};
2664
2665static struct ti_clk pka_ick = {
2666 .name = "pka_ick",
2667 .type = TI_CLK_GATE,
2668 .data = &pka_ick_data,
2669};
2670
2671static struct ti_clk_gate gpt12_ick_data = {
2672 .parent = "wkup_l4_ick",
2673 .bit_shift = 1,
2674 .reg = 0xc10,
2675 .module = TI_CLKM_CM,
2676 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2677};
2678
2679static struct ti_clk gpt12_ick = {
2680 .name = "gpt12_ick",
2681 .clkdm_name = "wkup_clkdm",
2682 .type = TI_CLK_GATE,
2683 .data = &gpt12_ick_data,
2684};
2685
2686static const char *mcbsp5_mux_fck_parents[] = {
2687 "core_96m_fck",
2688 "mcbsp_clks",
2689};
2690
2691static struct ti_clk_mux mcbsp5_mux_fck_data = {
2692 .bit_shift = 4,
2693 .num_parents = ARRAY_SIZE(mcbsp5_mux_fck_parents),
2694 .reg = 0x2d8,
2695 .module = TI_CLKM_SCRM,
2696 .parents = mcbsp5_mux_fck_parents,
2697};
2698
2699static struct ti_clk_composite mcbsp5_fck_data = {
2700 .mux = &mcbsp5_mux_fck_data,
2701 .gate = &mcbsp5_gate_fck_data,
2702};
2703
2704static struct ti_clk mcbsp5_fck = {
2705 .name = "mcbsp5_fck",
2706 .type = TI_CLK_COMPOSITE,
2707 .data = &mcbsp5_fck_data,
2708};
2709
2710static struct ti_clk_gate usbhost_48m_fck_data = {
2711 .parent = "omap_48m_fck",
2712 .bit_shift = 0,
2713 .reg = 0x1400,
2714 .module = TI_CLKM_CM,
2715 .flags = CLKF_DSS,
2716};
2717
2718static struct ti_clk usbhost_48m_fck = {
2719 .name = "usbhost_48m_fck",
2720 .clkdm_name = "usbhost_clkdm",
2721 .type = TI_CLK_GATE,
2722 .data = &usbhost_48m_fck_data,
2723};
2724
2725static struct ti_clk_gate des1_ick_data = {
2726 .parent = "security_l4_ick2",
2727 .bit_shift = 0,
2728 .reg = 0xa14,
2729 .module = TI_CLKM_CM,
2730 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2731};
2732
2733static struct ti_clk des1_ick = {
2734 .name = "des1_ick",
2735 .type = TI_CLK_GATE,
2736 .data = &des1_ick_data,
2737};
2738
2739static struct ti_clk_gate sgx_gate_fck_data = {
2740 .parent = "core_ck",
2741 .bit_shift = 1,
2742 .reg = 0xb00,
2743 .module = TI_CLKM_CM,
2744};
2745
2746static struct ti_clk_fixed_factor core_d4_ck_data = {
2747 .parent = "core_ck",
2748 .div = 4,
2749 .mult = 1,
2750};
2751
2752static struct ti_clk core_d4_ck = {
2753 .name = "core_d4_ck",
2754 .type = TI_CLK_FIXED_FACTOR,
2755 .data = &core_d4_ck_data,
2756};
2757
2758static struct ti_clk_fixed_factor omap_192m_alwon_fck_data = {
2759 .parent = "dpll4_m2x2_ck",
2760 .div = 1,
2761 .mult = 1,
2762};
2763
2764static struct ti_clk omap_192m_alwon_fck = {
2765 .name = "omap_192m_alwon_fck",
2766 .type = TI_CLK_FIXED_FACTOR,
2767 .data = &omap_192m_alwon_fck_data,
2768};
2769
2770static struct ti_clk_fixed_factor core_d2_ck_data = {
2771 .parent = "core_ck",
2772 .div = 2,
2773 .mult = 1,
2774};
2775
2776static struct ti_clk core_d2_ck = {
2777 .name = "core_d2_ck",
2778 .type = TI_CLK_FIXED_FACTOR,
2779 .data = &core_d2_ck_data,
2780};
2781
2782static struct ti_clk_fixed_factor corex2_d3_fck_data = {
2783 .parent = "corex2_fck",
2784 .div = 3,
2785 .mult = 1,
2786};
2787
2788static struct ti_clk corex2_d3_fck = {
2789 .name = "corex2_d3_fck",
2790 .type = TI_CLK_FIXED_FACTOR,
2791 .data = &corex2_d3_fck_data,
2792};
2793
2794static struct ti_clk_fixed_factor corex2_d5_fck_data = {
2795 .parent = "corex2_fck",
2796 .div = 5,
2797 .mult = 1,
2798};
2799
2800static struct ti_clk corex2_d5_fck = {
2801 .name = "corex2_d5_fck",
2802 .type = TI_CLK_FIXED_FACTOR,
2803 .data = &corex2_d5_fck_data,
2804};
2805
2806static const char *sgx_mux_fck_parents[] = {
2807 "core_d3_ck",
2808 "core_d4_ck",
2809 "core_d6_ck",
2810 "cm_96m_fck",
2811 "omap_192m_alwon_fck",
2812 "core_d2_ck",
2813 "corex2_d3_fck",
2814 "corex2_d5_fck",
2815};
2816
2817static struct ti_clk_mux sgx_mux_fck_data = {
2818 .num_parents = ARRAY_SIZE(sgx_mux_fck_parents),
2819 .reg = 0xb40,
2820 .module = TI_CLKM_CM,
2821 .parents = sgx_mux_fck_parents,
2822};
2823
2824static struct ti_clk_composite sgx_fck_data = {
2825 .mux = &sgx_mux_fck_data,
2826 .gate = &sgx_gate_fck_data,
2827};
2828
2829static struct ti_clk sgx_fck = {
2830 .name = "sgx_fck",
2831 .type = TI_CLK_COMPOSITE,
2832 .data = &sgx_fck_data,
2833};
2834
2835static struct ti_clk_gate mcspi1_fck_data = {
2836 .parent = "core_48m_fck",
2837 .bit_shift = 18,
2838 .reg = 0xa00,
2839 .module = TI_CLKM_CM,
2840 .flags = CLKF_WAIT,
2841};
2842
2843static struct ti_clk mcspi1_fck = {
2844 .name = "mcspi1_fck",
2845 .clkdm_name = "core_l4_clkdm",
2846 .type = TI_CLK_GATE,
2847 .data = &mcspi1_fck_data,
2848};
2849
2850static struct ti_clk_gate mmchs2_fck_data = {
2851 .parent = "core_96m_fck",
2852 .bit_shift = 25,
2853 .reg = 0xa00,
2854 .module = TI_CLKM_CM,
2855 .flags = CLKF_WAIT,
2856};
2857
2858static struct ti_clk mmchs2_fck = {
2859 .name = "mmchs2_fck",
2860 .clkdm_name = "core_l4_clkdm",
2861 .type = TI_CLK_GATE,
2862 .data = &mmchs2_fck_data,
2863};
2864
2865static struct ti_clk_gate mcspi2_fck_data = {
2866 .parent = "core_48m_fck",
2867 .bit_shift = 19,
2868 .reg = 0xa00,
2869 .module = TI_CLKM_CM,
2870 .flags = CLKF_WAIT,
2871};
2872
2873static struct ti_clk mcspi2_fck = {
2874 .name = "mcspi2_fck",
2875 .clkdm_name = "core_l4_clkdm",
2876 .type = TI_CLK_GATE,
2877 .data = &mcspi2_fck_data,
2878};
2879
2880static struct ti_clk_gate vpfe_fck_data = {
2881 .parent = "pclk_ck",
2882 .bit_shift = 10,
2883 .reg = 0x59c,
2884 .module = TI_CLKM_SCRM,
2885};
2886
2887static struct ti_clk vpfe_fck = {
2888 .name = "vpfe_fck",
2889 .type = TI_CLK_GATE,
2890 .data = &vpfe_fck_data,
2891};
2892
2893static struct ti_clk_gate gpt4_gate_fck_data = {
2894 .parent = "sys_ck",
2895 .bit_shift = 5,
2896 .reg = 0x1000,
2897 .module = TI_CLKM_CM,
2898};
2899
2900static struct ti_clk_gate mcbsp1_gate_fck_data = {
2901 .parent = "mcbsp_clks",
2902 .bit_shift = 9,
2903 .reg = 0xa00,
2904 .module = TI_CLKM_CM,
2905};
2906
2907static struct ti_clk_gate gpt5_gate_fck_data = {
2908 .parent = "sys_ck",
2909 .bit_shift = 6,
2910 .reg = 0x1000,
2911 .module = TI_CLKM_CM,
2912};
2913
2914static const char *gpt5_mux_fck_parents[] = {
2915 "omap_32k_fck",
2916 "sys_ck",
2917};
2918
2919static struct ti_clk_mux gpt5_mux_fck_data = {
2920 .bit_shift = 3,
2921 .num_parents = ARRAY_SIZE(gpt5_mux_fck_parents),
2922 .reg = 0x1040,
2923 .module = TI_CLKM_CM,
2924 .parents = gpt5_mux_fck_parents,
2925};
2926
2927static struct ti_clk_composite gpt5_fck_data = {
2928 .mux = &gpt5_mux_fck_data,
2929 .gate = &gpt5_gate_fck_data,
2930};
2931
2932static struct ti_clk gpt5_fck = {
2933 .name = "gpt5_fck",
2934 .type = TI_CLK_COMPOSITE,
2935 .data = &gpt5_fck_data,
2936};
2937
2938static struct ti_clk_gate ts_fck_data = {
2939 .parent = "omap_32k_fck",
2940 .bit_shift = 1,
2941 .reg = 0xa08,
2942 .module = TI_CLKM_CM,
2943};
2944
2945static struct ti_clk ts_fck = {
2946 .name = "ts_fck",
2947 .clkdm_name = "core_l4_clkdm",
2948 .type = TI_CLK_GATE,
2949 .data = &ts_fck_data,
2950};
2951
2952static struct ti_clk_fixed_factor wdt1_fck_data = {
2953 .parent = "secure_32k_fck",
2954 .div = 1,
2955 .mult = 1,
2956};
2957
2958static struct ti_clk wdt1_fck = {
2959 .name = "wdt1_fck",
2960 .type = TI_CLK_FIXED_FACTOR,
2961 .data = &wdt1_fck_data,
2962};
2963
2964static struct ti_clk_gate dpll4_m6x2_ck_omap36xx_data = {
2965 .parent = "dpll4_m6x2_mul_ck",
2966 .bit_shift = 0x1f,
2967 .reg = 0xd00,
2968 .module = TI_CLKM_CM,
2969 .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
2970};
2971
2972static struct ti_clk dpll4_m6x2_ck_omap36xx = {
2973 .name = "dpll4_m6x2_ck",
2974 .type = TI_CLK_GATE,
2975 .data = &dpll4_m6x2_ck_omap36xx_data,
2976 .patch = &dpll4_m6x2_ck,
2977};
2978
2979static const char *gpt4_mux_fck_parents[] = {
2980 "omap_32k_fck",
2981 "sys_ck",
2982};
2983
2984static struct ti_clk_mux gpt4_mux_fck_data = {
2985 .bit_shift = 2,
2986 .num_parents = ARRAY_SIZE(gpt4_mux_fck_parents),
2987 .reg = 0x1040,
2988 .module = TI_CLKM_CM,
2989 .parents = gpt4_mux_fck_parents,
2990};
2991
2992static struct ti_clk_gate usbhost_ick_data = {
2993 .parent = "l4_ick",
2994 .bit_shift = 0,
2995 .reg = 0x1410,
2996 .module = TI_CLKM_CM,
2997 .flags = CLKF_DSS | CLKF_OMAP3 | CLKF_INTERFACE,
2998};
2999
3000static struct ti_clk usbhost_ick = {
3001 .name = "usbhost_ick",
3002 .clkdm_name = "usbhost_clkdm",
3003 .type = TI_CLK_GATE,
3004 .data = &usbhost_ick_data,
3005};
3006
3007static struct ti_clk_gate mcbsp2_ick_data = {
3008 .parent = "per_l4_ick",
3009 .bit_shift = 0,
3010 .reg = 0x1010,
3011 .module = TI_CLKM_CM,
3012 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3013};
3014
3015static struct ti_clk mcbsp2_ick = {
3016 .name = "mcbsp2_ick",
3017 .clkdm_name = "per_clkdm",
3018 .type = TI_CLK_GATE,
3019 .data = &mcbsp2_ick_data,
3020};
3021
3022static struct ti_clk_gate omapctrl_ick_data = {
3023 .parent = "core_l4_ick",
3024 .bit_shift = 6,
3025 .reg = 0xa10,
3026 .module = TI_CLKM_CM,
3027 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3028};
3029
3030static struct ti_clk omapctrl_ick = {
3031 .name = "omapctrl_ick",
3032 .clkdm_name = "core_l4_clkdm",
3033 .type = TI_CLK_GATE,
3034 .data = &omapctrl_ick_data,
3035};
3036
3037static struct ti_clk_fixed_factor omap_96m_d4_fck_data = {
3038 .parent = "omap_96m_fck",
3039 .div = 4,
3040 .mult = 1,
3041};
3042
3043static struct ti_clk omap_96m_d4_fck = {
3044 .name = "omap_96m_d4_fck",
3045 .type = TI_CLK_FIXED_FACTOR,
3046 .data = &omap_96m_d4_fck_data,
3047};
3048
3049static struct ti_clk_gate gpt6_ick_data = {
3050 .parent = "per_l4_ick",
3051 .bit_shift = 7,
3052 .reg = 0x1010,
3053 .module = TI_CLKM_CM,
3054 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3055};
3056
3057static struct ti_clk gpt6_ick = {
3058 .name = "gpt6_ick",
3059 .clkdm_name = "per_clkdm",
3060 .type = TI_CLK_GATE,
3061 .data = &gpt6_ick_data,
3062};
3063
3064static struct ti_clk_gate dpll3_m3x2_ck_omap36xx_data = {
3065 .parent = "dpll3_m3x2_mul_ck",
3066 .bit_shift = 0xc,
3067 .reg = 0xd00,
3068 .module = TI_CLKM_CM,
3069 .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
3070};
3071
3072static struct ti_clk dpll3_m3x2_ck_omap36xx = {
3073 .name = "dpll3_m3x2_ck",
3074 .type = TI_CLK_GATE,
3075 .data = &dpll3_m3x2_ck_omap36xx_data,
3076 .patch = &dpll3_m3x2_ck,
3077};
3078
3079static struct ti_clk_gate i2c3_ick_data = {
3080 .parent = "core_l4_ick",
3081 .bit_shift = 17,
3082 .reg = 0xa10,
3083 .module = TI_CLKM_CM,
3084 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3085};
3086
3087static struct ti_clk i2c3_ick = {
3088 .name = "i2c3_ick",
3089 .clkdm_name = "core_l4_clkdm",
3090 .type = TI_CLK_GATE,
3091 .data = &i2c3_ick_data,
3092};
3093
3094static struct ti_clk_gate gpio6_ick_data = {
3095 .parent = "per_l4_ick",
3096 .bit_shift = 17,
3097 .reg = 0x1010,
3098 .module = TI_CLKM_CM,
3099 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3100};
3101
3102static struct ti_clk gpio6_ick = {
3103 .name = "gpio6_ick",
3104 .clkdm_name = "per_clkdm",
3105 .type = TI_CLK_GATE,
3106 .data = &gpio6_ick_data,
3107};
3108
3109static struct ti_clk_gate mspro_ick_data = {
3110 .parent = "core_l4_ick",
3111 .bit_shift = 23,
3112 .reg = 0xa10,
3113 .module = TI_CLKM_CM,
3114 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3115};
3116
3117static struct ti_clk mspro_ick = {
3118 .name = "mspro_ick",
3119 .clkdm_name = "core_l4_clkdm",
3120 .type = TI_CLK_GATE,
3121 .data = &mspro_ick_data,
3122};
3123
3124static struct ti_clk_composite mcbsp1_fck_data = {
3125 .mux = &mcbsp1_mux_fck_data,
3126 .gate = &mcbsp1_gate_fck_data,
3127};
3128
3129static struct ti_clk mcbsp1_fck = {
3130 .name = "mcbsp1_fck",
3131 .type = TI_CLK_COMPOSITE,
3132 .data = &mcbsp1_fck_data,
3133};
3134
3135static struct ti_clk_gate gpt3_gate_fck_data = {
3136 .parent = "sys_ck",
3137 .bit_shift = 4,
3138 .reg = 0x1000,
3139 .module = TI_CLKM_CM,
3140};
3141
3142static struct ti_clk_fixed rmii_ck_data = {
3143 .frequency = 50000000,
3144};
3145
3146static struct ti_clk rmii_ck = {
3147 .name = "rmii_ck",
3148 .type = TI_CLK_FIXED,
3149 .data = &rmii_ck_data,
3150};
3151
3152static struct ti_clk_gate gpt6_gate_fck_data = {
3153 .parent = "sys_ck",
3154 .bit_shift = 7,
3155 .reg = 0x1000,
3156 .module = TI_CLKM_CM,
3157};
3158
3159static struct ti_clk_composite gpt6_fck_data = {
3160 .mux = &gpt6_mux_fck_data,
3161 .gate = &gpt6_gate_fck_data,
3162};
3163
3164static struct ti_clk gpt6_fck = {
3165 .name = "gpt6_fck",
3166 .type = TI_CLK_COMPOSITE,
3167 .data = &gpt6_fck_data,
3168};
3169
3170static struct ti_clk_fixed_factor dpll5_m2_d4_ck_data = {
3171 .parent = "dpll5_m2_ck",
3172 .div = 4,
3173 .mult = 1,
3174};
3175
3176static struct ti_clk dpll5_m2_d4_ck = {
3177 .name = "dpll5_m2_d4_ck",
3178 .type = TI_CLK_FIXED_FACTOR,
3179 .data = &dpll5_m2_d4_ck_data,
3180};
3181
3182static struct ti_clk_fixed_factor sys_d2_ck_data = {
3183 .parent = "sys_ck",
3184 .div = 2,
3185 .mult = 1,
3186};
3187
3188static struct ti_clk sys_d2_ck = {
3189 .name = "sys_d2_ck",
3190 .type = TI_CLK_FIXED_FACTOR,
3191 .data = &sys_d2_ck_data,
3192};
3193
3194static struct ti_clk_fixed_factor omap_96m_d2_fck_data = {
3195 .parent = "omap_96m_fck",
3196 .div = 2,
3197 .mult = 1,
3198};
3199
3200static struct ti_clk omap_96m_d2_fck = {
3201 .name = "omap_96m_d2_fck",
3202 .type = TI_CLK_FIXED_FACTOR,
3203 .data = &omap_96m_d2_fck_data,
3204};
3205
3206static struct ti_clk_fixed_factor dpll5_m2_d8_ck_data = {
3207 .parent = "dpll5_m2_ck",
3208 .div = 8,
3209 .mult = 1,
3210};
3211
3212static struct ti_clk dpll5_m2_d8_ck = {
3213 .name = "dpll5_m2_d8_ck",
3214 .type = TI_CLK_FIXED_FACTOR,
3215 .data = &dpll5_m2_d8_ck_data,
3216};
3217
3218static struct ti_clk_fixed_factor dpll5_m2_d16_ck_data = {
3219 .parent = "dpll5_m2_ck",
3220 .div = 16,
3221 .mult = 1,
3222};
3223
3224static struct ti_clk dpll5_m2_d16_ck = {
3225 .name = "dpll5_m2_d16_ck",
3226 .type = TI_CLK_FIXED_FACTOR,
3227 .data = &dpll5_m2_d16_ck_data,
3228};
3229
3230static const char *usim_mux_fck_parents[] = {
3231 "sys_ck",
3232 "sys_d2_ck",
3233 "omap_96m_d2_fck",
3234 "omap_96m_d4_fck",
3235 "omap_96m_d8_fck",
3236 "omap_96m_d10_fck",
3237 "dpll5_m2_d4_ck",
3238 "dpll5_m2_d8_ck",
3239 "dpll5_m2_d16_ck",
3240 "dpll5_m2_d20_ck",
3241};
3242
3243static struct ti_clk_mux usim_mux_fck_data = {
3244 .bit_shift = 3,
3245 .num_parents = ARRAY_SIZE(usim_mux_fck_parents),
3246 .reg = 0xc40,
3247 .module = TI_CLKM_CM,
3248 .parents = usim_mux_fck_parents,
3249 .flags = CLKF_INDEX_STARTS_AT_ONE,
3250};
3251
3252static struct ti_clk_composite usim_fck_data = {
3253 .mux = &usim_mux_fck_data,
3254 .gate = &usim_gate_fck_data,
3255};
3256
3257static struct ti_clk usim_fck = {
3258 .name = "usim_fck",
3259 .type = TI_CLK_COMPOSITE,
3260 .data = &usim_fck_data,
3261};
3262
3263static int ssi_ssr_div_fck_3430es2_divs[] = {
3264 0,
3265 1,
3266 2,
3267 3,
3268 4,
3269 0,
3270 6,
3271 0,
3272 8,
3273};
3274
3275static struct ti_clk_divider ssi_ssr_div_fck_3430es2_data = {
3276 .num_dividers = ARRAY_SIZE(ssi_ssr_div_fck_3430es2_divs),
3277 .parent = "corex2_fck",
3278 .bit_shift = 8,
3279 .dividers = ssi_ssr_div_fck_3430es2_divs,
3280 .reg = 0xa40,
3281 .module = TI_CLKM_CM,
3282};
3283
3284static struct ti_clk_composite ssi_ssr_fck_3430es2_data = {
3285 .gate = &ssi_ssr_gate_fck_3430es2_data,
3286 .divider = &ssi_ssr_div_fck_3430es2_data,
3287};
3288
3289static struct ti_clk ssi_ssr_fck_3430es2 = {
3290 .name = "ssi_ssr_fck",
3291 .type = TI_CLK_COMPOSITE,
3292 .data = &ssi_ssr_fck_3430es2_data,
3293};
3294
3295static struct ti_clk_gate dss1_alwon_fck_3430es1_data = {
3296 .parent = "dpll4_m4x2_ck",
3297 .bit_shift = 0,
3298 .reg = 0xe00,
3299 .module = TI_CLKM_CM,
3300 .flags = CLKF_SET_RATE_PARENT,
3301};
3302
3303static struct ti_clk dss1_alwon_fck_3430es1 = {
3304 .name = "dss1_alwon_fck",
3305 .clkdm_name = "dss_clkdm",
3306 .type = TI_CLK_GATE,
3307 .data = &dss1_alwon_fck_3430es1_data,
3308};
3309
3310static struct ti_clk_gate gpt3_ick_data = {
3311 .parent = "per_l4_ick",
3312 .bit_shift = 4,
3313 .reg = 0x1010,
3314 .module = TI_CLKM_CM,
3315 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3316};
3317
3318static struct ti_clk gpt3_ick = {
3319 .name = "gpt3_ick",
3320 .clkdm_name = "per_clkdm",
3321 .type = TI_CLK_GATE,
3322 .data = &gpt3_ick_data,
3323};
3324
3325static struct ti_clk_fixed_factor omap_12m_fck_data = {
3326 .parent = "omap_48m_fck",
3327 .div = 4,
3328 .mult = 1,
3329};
3330
3331static struct ti_clk omap_12m_fck = {
3332 .name = "omap_12m_fck",
3333 .type = TI_CLK_FIXED_FACTOR,
3334 .data = &omap_12m_fck_data,
3335};
3336
3337static struct ti_clk_fixed_factor core_12m_fck_data = {
3338 .parent = "omap_12m_fck",
3339 .div = 1,
3340 .mult = 1,
3341};
3342
3343static struct ti_clk core_12m_fck = {
3344 .name = "core_12m_fck",
3345 .type = TI_CLK_FIXED_FACTOR,
3346 .data = &core_12m_fck_data,
3347};
3348
3349static struct ti_clk_gate hdq_fck_data = {
3350 .parent = "core_12m_fck",
3351 .bit_shift = 22,
3352 .reg = 0xa00,
3353 .module = TI_CLKM_CM,
3354 .flags = CLKF_WAIT,
3355};
3356
3357static struct ti_clk hdq_fck = {
3358 .name = "hdq_fck",
3359 .clkdm_name = "core_l4_clkdm",
3360 .type = TI_CLK_GATE,
3361 .data = &hdq_fck_data,
3362};
3363
3364static struct ti_clk_gate usbtll_fck_data = {
3365 .parent = "dpll5_m2_ck",
3366 .bit_shift = 2,
3367 .reg = 0xa08,
3368 .module = TI_CLKM_CM,
3369 .flags = CLKF_WAIT,
3370};
3371
3372static struct ti_clk usbtll_fck = {
3373 .name = "usbtll_fck",
3374 .clkdm_name = "core_l4_clkdm",
3375 .type = TI_CLK_GATE,
3376 .data = &usbtll_fck_data,
3377};
3378
3379static struct ti_clk_gate hsotgusb_fck_am35xx_data = {
3380 .parent = "sys_ck",
3381 .bit_shift = 8,
3382 .reg = 0x59c,
3383 .module = TI_CLKM_SCRM,
3384};
3385
3386static struct ti_clk hsotgusb_fck_am35xx = {
3387 .name = "hsotgusb_fck_am35xx",
3388 .clkdm_name = "core_l3_clkdm",
3389 .type = TI_CLK_GATE,
3390 .data = &hsotgusb_fck_am35xx_data,
3391};
3392
3393static struct ti_clk_gate hsotgusb_ick_3430es2_data = {
3394 .parent = "core_l3_ick",
3395 .bit_shift = 4,
3396 .reg = 0xa10,
3397 .module = TI_CLKM_CM,
3398 .flags = CLKF_HSOTGUSB | CLKF_OMAP3 | CLKF_INTERFACE,
3399};
3400
3401static struct ti_clk hsotgusb_ick_3430es2 = {
3402 .name = "hsotgusb_ick_3430es2",
3403 .clkdm_name = "core_l3_clkdm",
3404 .type = TI_CLK_GATE,
3405 .data = &hsotgusb_ick_3430es2_data,
3406};
3407
3408static struct ti_clk_gate gfx_l3_ck_data = {
3409 .parent = "l3_ick",
3410 .bit_shift = 0,
3411 .reg = 0xb10,
3412 .module = TI_CLKM_CM,
3413 .flags = CLKF_WAIT,
3414};
3415
3416static struct ti_clk gfx_l3_ck = {
3417 .name = "gfx_l3_ck",
3418 .clkdm_name = "gfx_3430es1_clkdm",
3419 .type = TI_CLK_GATE,
3420 .data = &gfx_l3_ck_data,
3421};
3422
3423static struct ti_clk_fixed_factor gfx_l3_ick_data = {
3424 .parent = "gfx_l3_ck",
3425 .div = 1,
3426 .mult = 1,
3427};
3428
3429static struct ti_clk gfx_l3_ick = {
3430 .name = "gfx_l3_ick",
3431 .type = TI_CLK_FIXED_FACTOR,
3432 .data = &gfx_l3_ick_data,
3433};
3434
3435static struct ti_clk_gate mcbsp1_ick_data = {
3436 .parent = "core_l4_ick",
3437 .bit_shift = 9,
3438 .reg = 0xa10,
3439 .module = TI_CLKM_CM,
3440 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3441};
3442
3443static struct ti_clk mcbsp1_ick = {
3444 .name = "mcbsp1_ick",
3445 .clkdm_name = "core_l4_clkdm",
3446 .type = TI_CLK_GATE,
3447 .data = &mcbsp1_ick_data,
3448};
3449
3450static struct ti_clk_fixed_factor gpt12_fck_data = {
3451 .parent = "secure_32k_fck",
3452 .div = 1,
3453 .mult = 1,
3454};
3455
3456static struct ti_clk gpt12_fck = {
3457 .name = "gpt12_fck",
3458 .type = TI_CLK_FIXED_FACTOR,
3459 .data = &gpt12_fck_data,
3460};
3461
3462static struct ti_clk_gate gfx_cg2_ck_data = {
3463 .parent = "gfx_l3_fck",
3464 .bit_shift = 2,
3465 .reg = 0xb00,
3466 .module = TI_CLKM_CM,
3467 .flags = CLKF_WAIT,
3468};
3469
3470static struct ti_clk gfx_cg2_ck = {
3471 .name = "gfx_cg2_ck",
3472 .clkdm_name = "gfx_3430es1_clkdm",
3473 .type = TI_CLK_GATE,
3474 .data = &gfx_cg2_ck_data,
3475};
3476
3477static struct ti_clk_gate i2c2_ick_data = {
3478 .parent = "core_l4_ick",
3479 .bit_shift = 16,
3480 .reg = 0xa10,
3481 .module = TI_CLKM_CM,
3482 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3483};
3484
3485static struct ti_clk i2c2_ick = {
3486 .name = "i2c2_ick",
3487 .clkdm_name = "core_l4_clkdm",
3488 .type = TI_CLK_GATE,
3489 .data = &i2c2_ick_data,
3490};
3491
3492static struct ti_clk_gate gpio4_dbck_data = {
3493 .parent = "per_32k_alwon_fck",
3494 .bit_shift = 15,
3495 .reg = 0x1000,
3496 .module = TI_CLKM_CM,
3497};
3498
3499static struct ti_clk gpio4_dbck = {
3500 .name = "gpio4_dbck",
3501 .clkdm_name = "per_clkdm",
3502 .type = TI_CLK_GATE,
3503 .data = &gpio4_dbck_data,
3504};
3505
3506static struct ti_clk_gate i2c3_fck_data = {
3507 .parent = "core_96m_fck",
3508 .bit_shift = 17,
3509 .reg = 0xa00,
3510 .module = TI_CLKM_CM,
3511 .flags = CLKF_WAIT,
3512};
3513
3514static struct ti_clk i2c3_fck = {
3515 .name = "i2c3_fck",
3516 .clkdm_name = "core_l4_clkdm",
3517 .type = TI_CLK_GATE,
3518 .data = &i2c3_fck_data,
3519};
3520
3521static struct ti_clk_composite gpt3_fck_data = {
3522 .mux = &gpt3_mux_fck_data,
3523 .gate = &gpt3_gate_fck_data,
3524};
3525
3526static struct ti_clk gpt3_fck = {
3527 .name = "gpt3_fck",
3528 .type = TI_CLK_COMPOSITE,
3529 .data = &gpt3_fck_data,
3530};
3531
3532static struct ti_clk_gate i2c1_ick_data = {
3533 .parent = "core_l4_ick",
3534 .bit_shift = 15,
3535 .reg = 0xa10,
3536 .module = TI_CLKM_CM,
3537 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3538};
3539
3540static struct ti_clk i2c1_ick = {
3541 .name = "i2c1_ick",
3542 .clkdm_name = "core_l4_clkdm",
3543 .type = TI_CLK_GATE,
3544 .data = &i2c1_ick_data,
3545};
3546
3547static struct ti_clk_gate omap_32ksync_ick_data = {
3548 .parent = "wkup_l4_ick",
3549 .bit_shift = 2,
3550 .reg = 0xc10,
3551 .module = TI_CLKM_CM,
3552 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3553};
3554
3555static struct ti_clk omap_32ksync_ick = {
3556 .name = "omap_32ksync_ick",
3557 .clkdm_name = "wkup_clkdm",
3558 .type = TI_CLK_GATE,
3559 .data = &omap_32ksync_ick_data,
3560};
3561
3562static struct ti_clk_gate aes2_ick_data = {
3563 .parent = "core_l4_ick",
3564 .bit_shift = 28,
3565 .reg = 0xa10,
3566 .module = TI_CLKM_CM,
3567 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3568};
3569
3570static struct ti_clk aes2_ick = {
3571 .name = "aes2_ick",
3572 .clkdm_name = "core_l4_clkdm",
3573 .type = TI_CLK_GATE,
3574 .data = &aes2_ick_data,
3575};
3576
3577static const char *gpt8_mux_fck_parents[] = {
3578 "omap_32k_fck",
3579 "sys_ck",
3580};
3581
3582static struct ti_clk_mux gpt8_mux_fck_data = {
3583 .bit_shift = 6,
3584 .num_parents = ARRAY_SIZE(gpt8_mux_fck_parents),
3585 .reg = 0x1040,
3586 .module = TI_CLKM_CM,
3587 .parents = gpt8_mux_fck_parents,
3588};
3589
3590static struct ti_clk_composite gpt8_fck_data = {
3591 .mux = &gpt8_mux_fck_data,
3592 .gate = &gpt8_gate_fck_data,
3593};
3594
3595static struct ti_clk gpt8_fck = {
3596 .name = "gpt8_fck",
3597 .type = TI_CLK_COMPOSITE,
3598 .data = &gpt8_fck_data,
3599};
3600
3601static struct ti_clk_gate mcbsp4_gate_fck_data = {
3602 .parent = "mcbsp_clks",
3603 .bit_shift = 2,
3604 .reg = 0x1000,
3605 .module = TI_CLKM_CM,
3606};
3607
3608static struct ti_clk_composite mcbsp4_fck_data = {
3609 .mux = &mcbsp4_mux_fck_data,
3610 .gate = &mcbsp4_gate_fck_data,
3611};
3612
3613static struct ti_clk mcbsp4_fck = {
3614 .name = "mcbsp4_fck",
3615 .type = TI_CLK_COMPOSITE,
3616 .data = &mcbsp4_fck_data,
3617};
3618
3619static struct ti_clk_gate gpio2_dbck_data = {
3620 .parent = "per_32k_alwon_fck",
3621 .bit_shift = 13,
3622 .reg = 0x1000,
3623 .module = TI_CLKM_CM,
3624};
3625
3626static struct ti_clk gpio2_dbck = {
3627 .name = "gpio2_dbck",
3628 .clkdm_name = "per_clkdm",
3629 .type = TI_CLK_GATE,
3630 .data = &gpio2_dbck_data,
3631};
3632
3633static struct ti_clk_gate usbtll_ick_data = {
3634 .parent = "core_l4_ick",
3635 .bit_shift = 2,
3636 .reg = 0xa18,
3637 .module = TI_CLKM_CM,
3638 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3639};
3640
3641static struct ti_clk usbtll_ick = {
3642 .name = "usbtll_ick",
3643 .clkdm_name = "core_l4_clkdm",
3644 .type = TI_CLK_GATE,
3645 .data = &usbtll_ick_data,
3646};
3647
3648static struct ti_clk_gate mcspi4_ick_data = {
3649 .parent = "core_l4_ick",
3650 .bit_shift = 21,
3651 .reg = 0xa10,
3652 .module = TI_CLKM_CM,
3653 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3654};
3655
3656static struct ti_clk mcspi4_ick = {
3657 .name = "mcspi4_ick",
3658 .clkdm_name = "core_l4_clkdm",
3659 .type = TI_CLK_GATE,
3660 .data = &mcspi4_ick_data,
3661};
3662
3663static struct ti_clk_gate dss_96m_fck_data = {
3664 .parent = "omap_96m_fck",
3665 .bit_shift = 2,
3666 .reg = 0xe00,
3667 .module = TI_CLKM_CM,
3668};
3669
3670static struct ti_clk dss_96m_fck = {
3671 .name = "dss_96m_fck",
3672 .clkdm_name = "dss_clkdm",
3673 .type = TI_CLK_GATE,
3674 .data = &dss_96m_fck_data,
3675};
3676
3677static struct ti_clk_divider rm_ick_data = {
3678 .parent = "l4_ick",
3679 .bit_shift = 1,
3680 .max_div = 3,
3681 .reg = 0xc40,
3682 .module = TI_CLKM_CM,
3683 .flags = CLKF_INDEX_STARTS_AT_ONE,
3684};
3685
3686static struct ti_clk rm_ick = {
3687 .name = "rm_ick",
3688 .type = TI_CLK_DIVIDER,
3689 .data = &rm_ick_data,
3690};
3691
3692static struct ti_clk_gate hdq_ick_data = {
3693 .parent = "core_l4_ick",
3694 .bit_shift = 22,
3695 .reg = 0xa10,
3696 .module = TI_CLKM_CM,
3697 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3698};
3699
3700static struct ti_clk hdq_ick = {
3701 .name = "hdq_ick",
3702 .clkdm_name = "core_l4_clkdm",
3703 .type = TI_CLK_GATE,
3704 .data = &hdq_ick_data,
3705};
3706
3707static struct ti_clk_fixed_factor dpll3_x2_ck_data = {
3708 .parent = "dpll3_ck",
3709 .div = 1,
3710 .mult = 2,
3711};
3712
3713static struct ti_clk dpll3_x2_ck = {
3714 .name = "dpll3_x2_ck",
3715 .type = TI_CLK_FIXED_FACTOR,
3716 .data = &dpll3_x2_ck_data,
3717};
3718
3719static struct ti_clk_gate mad2d_ick_data = {
3720 .parent = "l3_ick",
3721 .bit_shift = 3,
3722 .reg = 0xa18,
3723 .module = TI_CLKM_CM,
3724 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3725};
3726
3727static struct ti_clk mad2d_ick = {
3728 .name = "mad2d_ick",
3729 .clkdm_name = "d2d_clkdm",
3730 .type = TI_CLK_GATE,
3731 .data = &mad2d_ick_data,
3732};
3733
3734static struct ti_clk_gate fshostusb_fck_data = {
3735 .parent = "core_48m_fck",
3736 .bit_shift = 5,
3737 .reg = 0xa00,
3738 .module = TI_CLKM_CM,
3739 .flags = CLKF_WAIT,
3740};
3741
3742static struct ti_clk fshostusb_fck = {
3743 .name = "fshostusb_fck",
3744 .clkdm_name = "core_l4_clkdm",
3745 .type = TI_CLK_GATE,
3746 .data = &fshostusb_fck_data,
3747};
3748
3749static struct ti_clk_gate sr1_fck_data = {
3750 .parent = "sys_ck",
3751 .bit_shift = 6,
3752 .reg = 0xc00,
3753 .module = TI_CLKM_CM,
3754 .flags = CLKF_WAIT,
3755};
3756
3757static struct ti_clk sr1_fck = {
3758 .name = "sr1_fck",
3759 .clkdm_name = "wkup_clkdm",
3760 .type = TI_CLK_GATE,
3761 .data = &sr1_fck_data,
3762};
3763
3764static struct ti_clk_gate des2_ick_data = {
3765 .parent = "core_l4_ick",
3766 .bit_shift = 26,
3767 .reg = 0xa10,
3768 .module = TI_CLKM_CM,
3769 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3770};
3771
3772static struct ti_clk des2_ick = {
3773 .name = "des2_ick",
3774 .clkdm_name = "core_l4_clkdm",
3775 .type = TI_CLK_GATE,
3776 .data = &des2_ick_data,
3777};
3778
3779static struct ti_clk_gate sdrc_ick_data = {
3780 .parent = "core_l3_ick",
3781 .bit_shift = 1,
3782 .reg = 0xa10,
3783 .module = TI_CLKM_CM,
3784 .flags = CLKF_WAIT,
3785};
3786
3787static struct ti_clk sdrc_ick = {
3788 .name = "sdrc_ick",
3789 .clkdm_name = "core_l3_clkdm",
3790 .type = TI_CLK_GATE,
3791 .data = &sdrc_ick_data,
3792};
3793
3794static struct ti_clk_composite gpt4_fck_data = {
3795 .mux = &gpt4_mux_fck_data,
3796 .gate = &gpt4_gate_fck_data,
3797};
3798
3799static struct ti_clk gpt4_fck = {
3800 .name = "gpt4_fck",
3801 .type = TI_CLK_COMPOSITE,
3802 .data = &gpt4_fck_data,
3803};
3804
3805static struct ti_clk_gate dpll4_m3x2_ck_omap36xx_data = {
3806 .parent = "dpll4_m3x2_mul_ck",
3807 .bit_shift = 0x1c,
3808 .reg = 0xd00,
3809 .module = TI_CLKM_CM,
3810 .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
3811};
3812
3813static struct ti_clk dpll4_m3x2_ck_omap36xx = {
3814 .name = "dpll4_m3x2_ck",
3815 .type = TI_CLK_GATE,
3816 .data = &dpll4_m3x2_ck_omap36xx_data,
3817 .patch = &dpll4_m3x2_ck,
3818};
3819
3820static struct ti_clk_gate cpefuse_fck_data = {
3821 .parent = "sys_ck",
3822 .bit_shift = 0,
3823 .reg = 0xa08,
3824 .module = TI_CLKM_CM,
3825};
3826
3827static struct ti_clk cpefuse_fck = {
3828 .name = "cpefuse_fck",
3829 .clkdm_name = "core_l4_clkdm",
3830 .type = TI_CLK_GATE,
3831 .data = &cpefuse_fck_data,
3832};
3833
3834static struct ti_clk_gate mcspi3_ick_data = {
3835 .parent = "core_l4_ick",
3836 .bit_shift = 20,
3837 .reg = 0xa10,
3838 .module = TI_CLKM_CM,
3839 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3840};
3841
3842static struct ti_clk mcspi3_ick = {
3843 .name = "mcspi3_ick",
3844 .clkdm_name = "core_l4_clkdm",
3845 .type = TI_CLK_GATE,
3846 .data = &mcspi3_ick_data,
3847};
3848
3849static struct ti_clk_fixed_factor ssi_sst_fck_3430es2_data = {
3850 .parent = "ssi_ssr_fck",
3851 .div = 2,
3852 .mult = 1,
3853};
3854
3855static struct ti_clk ssi_sst_fck_3430es2 = {
3856 .name = "ssi_sst_fck",
3857 .type = TI_CLK_FIXED_FACTOR,
3858 .data = &ssi_sst_fck_3430es2_data,
3859};
3860
3861static struct ti_clk_gate gpio1_dbck_data = {
3862 .parent = "wkup_32k_fck",
3863 .bit_shift = 3,
3864 .reg = 0xc00,
3865 .module = TI_CLKM_CM,
3866};
3867
3868static struct ti_clk gpio1_dbck = {
3869 .name = "gpio1_dbck",
3870 .clkdm_name = "wkup_clkdm",
3871 .type = TI_CLK_GATE,
3872 .data = &gpio1_dbck_data,
3873};
3874
3875static struct ti_clk_gate gpt4_ick_data = {
3876 .parent = "per_l4_ick",
3877 .bit_shift = 5,
3878 .reg = 0x1010,
3879 .module = TI_CLKM_CM,
3880 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3881};
3882
3883static struct ti_clk gpt4_ick = {
3884 .name = "gpt4_ick",
3885 .clkdm_name = "per_clkdm",
3886 .type = TI_CLK_GATE,
3887 .data = &gpt4_ick_data,
3888};
3889
3890static struct ti_clk_gate gpt2_ick_data = {
3891 .parent = "per_l4_ick",
3892 .bit_shift = 3,
3893 .reg = 0x1010,
3894 .module = TI_CLKM_CM,
3895 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3896};
3897
3898static struct ti_clk gpt2_ick = {
3899 .name = "gpt2_ick",
3900 .clkdm_name = "per_clkdm",
3901 .type = TI_CLK_GATE,
3902 .data = &gpt2_ick_data,
3903};
3904
3905static struct ti_clk_gate mmchs1_fck_data = {
3906 .parent = "core_96m_fck",
3907 .bit_shift = 24,
3908 .reg = 0xa00,
3909 .module = TI_CLKM_CM,
3910 .flags = CLKF_WAIT,
3911};
3912
3913static struct ti_clk mmchs1_fck = {
3914 .name = "mmchs1_fck",
3915 .clkdm_name = "core_l4_clkdm",
3916 .type = TI_CLK_GATE,
3917 .data = &mmchs1_fck_data,
3918};
3919
3920static struct ti_clk_fixed dummy_apb_pclk_data = {
3921 .frequency = 0x0,
3922};
3923
3924static struct ti_clk dummy_apb_pclk = {
3925 .name = "dummy_apb_pclk",
3926 .type = TI_CLK_FIXED,
3927 .data = &dummy_apb_pclk_data,
3928};
3929
3930static struct ti_clk_gate gpio6_dbck_data = {
3931 .parent = "per_32k_alwon_fck",
3932 .bit_shift = 17,
3933 .reg = 0x1000,
3934 .module = TI_CLKM_CM,
3935};
3936
3937static struct ti_clk gpio6_dbck = {
3938 .name = "gpio6_dbck",
3939 .clkdm_name = "per_clkdm",
3940 .type = TI_CLK_GATE,
3941 .data = &gpio6_dbck_data,
3942};
3943
3944static struct ti_clk_gate uart2_ick_data = {
3945 .parent = "core_l4_ick",
3946 .bit_shift = 14,
3947 .reg = 0xa10,
3948 .module = TI_CLKM_CM,
3949 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3950};
3951
3952static struct ti_clk uart2_ick = {
3953 .name = "uart2_ick",
3954 .clkdm_name = "core_l4_clkdm",
3955 .type = TI_CLK_GATE,
3956 .data = &uart2_ick_data,
3957};
3958
3959static struct ti_clk_fixed_factor dpll4_x2_ck_data = {
3960 .parent = "dpll4_ck",
3961 .div = 1,
3962 .mult = 2,
3963};
3964
3965static struct ti_clk dpll4_x2_ck = {
3966 .name = "dpll4_x2_ck",
3967 .type = TI_CLK_FIXED_FACTOR,
3968 .data = &dpll4_x2_ck_data,
3969};
3970
3971static struct ti_clk_gate gpt7_ick_data = {
3972 .parent = "per_l4_ick",
3973 .bit_shift = 8,
3974 .reg = 0x1010,
3975 .module = TI_CLKM_CM,
3976 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3977};
3978
3979static struct ti_clk gpt7_ick = {
3980 .name = "gpt7_ick",
3981 .clkdm_name = "per_clkdm",
3982 .type = TI_CLK_GATE,
3983 .data = &gpt7_ick_data,
3984};
3985
3986static struct ti_clk_gate dss_tv_fck_data = {
3987 .parent = "omap_54m_fck",
3988 .bit_shift = 2,
3989 .reg = 0xe00,
3990 .module = TI_CLKM_CM,
3991};
3992
3993static struct ti_clk dss_tv_fck = {
3994 .name = "dss_tv_fck",
3995 .clkdm_name = "dss_clkdm",
3996 .type = TI_CLK_GATE,
3997 .data = &dss_tv_fck_data,
3998};
3999
4000static struct ti_clk_gate mcbsp5_ick_data = {
4001 .parent = "core_l4_ick",
4002 .bit_shift = 10,
4003 .reg = 0xa10,
4004 .module = TI_CLKM_CM,
4005 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4006};
4007
4008static struct ti_clk mcbsp5_ick = {
4009 .name = "mcbsp5_ick",
4010 .clkdm_name = "core_l4_clkdm",
4011 .type = TI_CLK_GATE,
4012 .data = &mcbsp5_ick_data,
4013};
4014
4015static struct ti_clk_gate mcspi1_ick_data = {
4016 .parent = "core_l4_ick",
4017 .bit_shift = 18,
4018 .reg = 0xa10,
4019 .module = TI_CLKM_CM,
4020 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4021};
4022
4023static struct ti_clk mcspi1_ick = {
4024 .name = "mcspi1_ick",
4025 .clkdm_name = "core_l4_clkdm",
4026 .type = TI_CLK_GATE,
4027 .data = &mcspi1_ick_data,
4028};
4029
4030static struct ti_clk_gate d2d_26m_fck_data = {
4031 .parent = "sys_ck",
4032 .bit_shift = 3,
4033 .reg = 0xa00,
4034 .module = TI_CLKM_CM,
4035 .flags = CLKF_WAIT,
4036};
4037
4038static struct ti_clk d2d_26m_fck = {
4039 .name = "d2d_26m_fck",
4040 .clkdm_name = "d2d_clkdm",
4041 .type = TI_CLK_GATE,
4042 .data = &d2d_26m_fck_data,
4043};
4044
4045static struct ti_clk_gate wdt3_ick_data = {
4046 .parent = "per_l4_ick",
4047 .bit_shift = 12,
4048 .reg = 0x1010,
4049 .module = TI_CLKM_CM,
4050 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4051};
4052
4053static struct ti_clk wdt3_ick = {
4054 .name = "wdt3_ick",
4055 .clkdm_name = "per_clkdm",
4056 .type = TI_CLK_GATE,
4057 .data = &wdt3_ick_data,
4058};
4059
4060static struct ti_clk_divider pclkx2_fck_data = {
4061 .parent = "emu_src_ck",
4062 .bit_shift = 6,
4063 .max_div = 3,
4064 .reg = 0x1140,
4065 .module = TI_CLKM_CM,
4066 .flags = CLKF_INDEX_STARTS_AT_ONE,
4067};
4068
4069static struct ti_clk pclkx2_fck = {
4070 .name = "pclkx2_fck",
4071 .type = TI_CLK_DIVIDER,
4072 .data = &pclkx2_fck_data,
4073};
4074
4075static struct ti_clk_gate sha12_ick_data = {
4076 .parent = "core_l4_ick",
4077 .bit_shift = 27,
4078 .reg = 0xa10,
4079 .module = TI_CLKM_CM,
4080 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4081};
4082
4083static struct ti_clk sha12_ick = {
4084 .name = "sha12_ick",
4085 .clkdm_name = "core_l4_clkdm",
4086 .type = TI_CLK_GATE,
4087 .data = &sha12_ick_data,
4088};
4089
4090static struct ti_clk_gate emac_fck_data = {
4091 .parent = "rmii_ck",
4092 .bit_shift = 9,
4093 .reg = 0x59c,
4094 .module = TI_CLKM_SCRM,
4095};
4096
4097static struct ti_clk emac_fck = {
4098 .name = "emac_fck",
4099 .type = TI_CLK_GATE,
4100 .data = &emac_fck_data,
4101};
4102
4103static struct ti_clk_composite gpt10_fck_data = {
4104 .mux = &gpt10_mux_fck_data,
4105 .gate = &gpt10_gate_fck_data,
4106};
4107
4108static struct ti_clk gpt10_fck = {
4109 .name = "gpt10_fck",
4110 .type = TI_CLK_COMPOSITE,
4111 .data = &gpt10_fck_data,
4112};
4113
4114static struct ti_clk_gate wdt2_fck_data = {
4115 .parent = "wkup_32k_fck",
4116 .bit_shift = 5,
4117 .reg = 0xc00,
4118 .module = TI_CLKM_CM,
4119 .flags = CLKF_WAIT,
4120};
4121
4122static struct ti_clk wdt2_fck = {
4123 .name = "wdt2_fck",
4124 .clkdm_name = "wkup_clkdm",
4125 .type = TI_CLK_GATE,
4126 .data = &wdt2_fck_data,
4127};
4128
4129static struct ti_clk_gate cam_ick_data = {
4130 .parent = "l4_ick",
4131 .bit_shift = 0,
4132 .reg = 0xf10,
4133 .module = TI_CLKM_CM,
4134 .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
4135};
4136
4137static struct ti_clk cam_ick = {
4138 .name = "cam_ick",
4139 .clkdm_name = "cam_clkdm",
4140 .type = TI_CLK_GATE,
4141 .data = &cam_ick_data,
4142};
4143
4144static struct ti_clk_gate ssi_ick_3430es2_data = {
4145 .parent = "ssi_l4_ick",
4146 .bit_shift = 0,
4147 .reg = 0xa10,
4148 .module = TI_CLKM_CM,
4149 .flags = CLKF_SSI | CLKF_OMAP3 | CLKF_INTERFACE,
4150};
4151
4152static struct ti_clk ssi_ick_3430es2 = {
4153 .name = "ssi_ick",
4154 .clkdm_name = "core_l4_clkdm",
4155 .type = TI_CLK_GATE,
4156 .data = &ssi_ick_3430es2_data,
4157};
4158
4159static struct ti_clk_gate gpio4_ick_data = {
4160 .parent = "per_l4_ick",
4161 .bit_shift = 15,
4162 .reg = 0x1010,
4163 .module = TI_CLKM_CM,
4164 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4165};
4166
4167static struct ti_clk gpio4_ick = {
4168 .name = "gpio4_ick",
4169 .clkdm_name = "per_clkdm",
4170 .type = TI_CLK_GATE,
4171 .data = &gpio4_ick_data,
4172};
4173
4174static struct ti_clk_gate wdt1_ick_data = {
4175 .parent = "wkup_l4_ick",
4176 .bit_shift = 4,
4177 .reg = 0xc10,
4178 .module = TI_CLKM_CM,
4179 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4180};
4181
4182static struct ti_clk wdt1_ick = {
4183 .name = "wdt1_ick",
4184 .clkdm_name = "wkup_clkdm",
4185 .type = TI_CLK_GATE,
4186 .data = &wdt1_ick_data,
4187};
4188
4189static struct ti_clk_gate rng_ick_data = {
4190 .parent = "security_l4_ick2",
4191 .bit_shift = 2,
4192 .reg = 0xa14,
4193 .module = TI_CLKM_CM,
4194 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4195};
4196
4197static struct ti_clk rng_ick = {
4198 .name = "rng_ick",
4199 .type = TI_CLK_GATE,
4200 .data = &rng_ick_data,
4201};
4202
4203static struct ti_clk_gate icr_ick_data = {
4204 .parent = "core_l4_ick",
4205 .bit_shift = 29,
4206 .reg = 0xa10,
4207 .module = TI_CLKM_CM,
4208 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4209};
4210
4211static struct ti_clk icr_ick = {
4212 .name = "icr_ick",
4213 .clkdm_name = "core_l4_clkdm",
4214 .type = TI_CLK_GATE,
4215 .data = &icr_ick_data,
4216};
4217
4218static struct ti_clk_gate sgx_ick_data = {
4219 .parent = "l3_ick",
4220 .bit_shift = 0,
4221 .reg = 0xb10,
4222 .module = TI_CLKM_CM,
4223 .flags = CLKF_WAIT,
4224};
4225
4226static struct ti_clk sgx_ick = {
4227 .name = "sgx_ick",
4228 .clkdm_name = "sgx_clkdm",
4229 .type = TI_CLK_GATE,
4230 .data = &sgx_ick_data,
4231};
4232
4233static struct ti_clk_divider sys_clkout2_data = {
4234 .parent = "clkout2_src_ck",
4235 .bit_shift = 3,
4236 .max_div = 64,
4237 .reg = 0xd70,
4238 .module = TI_CLKM_CM,
4239 .flags = CLKF_INDEX_POWER_OF_TWO,
4240};
4241
4242static struct ti_clk sys_clkout2 = {
4243 .name = "sys_clkout2",
4244 .type = TI_CLK_DIVIDER,
4245 .data = &sys_clkout2_data,
4246};
4247
4248static struct ti_clk_alias omap34xx_omap36xx_clks[] = {
4249 CLK(NULL, "security_l4_ick2", &security_l4_ick2),
4250 CLK(NULL, "aes1_ick", &aes1_ick),
4251 CLK("omap_rng", "ick", &rng_ick),
4252 CLK("omap3-rom-rng", "ick", &rng_ick),
4253 CLK(NULL, "sha11_ick", &sha11_ick),
4254 CLK(NULL, "des1_ick", &des1_ick),
4255 CLK(NULL, "cam_mclk", &cam_mclk),
4256 CLK(NULL, "cam_ick", &cam_ick),
4257 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck),
4258 CLK(NULL, "security_l3_ick", &security_l3_ick),
4259 CLK(NULL, "pka_ick", &pka_ick),
4260 CLK(NULL, "icr_ick", &icr_ick),
4261 CLK(NULL, "des2_ick", &des2_ick),
4262 CLK(NULL, "mspro_ick", &mspro_ick),
4263 CLK(NULL, "mailboxes_ick", &mailboxes_ick),
4264 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
4265 CLK(NULL, "sr1_fck", &sr1_fck),
4266 CLK(NULL, "sr2_fck", &sr2_fck),
4267 CLK(NULL, "sr_l4_ick", &sr_l4_ick),
4268 CLK(NULL, "dpll2_fck", &dpll2_fck),
4269 CLK(NULL, "dpll2_ck", &dpll2_ck),
4270 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck),
4271 CLK(NULL, "iva2_ck", &iva2_ck),
4272 CLK(NULL, "modem_fck", &modem_fck),
4273 CLK(NULL, "sad2d_ick", &sad2d_ick),
4274 CLK(NULL, "mad2d_ick", &mad2d_ick),
4275 CLK(NULL, "mspro_fck", &mspro_fck),
4276 { NULL },
4277};
4278
4279static struct ti_clk_alias omap36xx_omap3430es2plus_clks[] = {
4280 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2),
4281 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2),
4282 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2),
4283 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2),
4284 CLK(NULL, "ssi_ick", &ssi_ick_3430es2),
4285 CLK(NULL, "sys_d2_ck", &sys_d2_ck),
4286 CLK(NULL, "omap_96m_d2_fck", &omap_96m_d2_fck),
4287 CLK(NULL, "omap_96m_d4_fck", &omap_96m_d4_fck),
4288 CLK(NULL, "omap_96m_d8_fck", &omap_96m_d8_fck),
4289 CLK(NULL, "omap_96m_d10_fck", &omap_96m_d10_fck),
4290 CLK(NULL, "dpll5_m2_d4_ck", &dpll5_m2_d4_ck),
4291 CLK(NULL, "dpll5_m2_d8_ck", &dpll5_m2_d8_ck),
4292 CLK(NULL, "dpll5_m2_d16_ck", &dpll5_m2_d16_ck),
4293 CLK(NULL, "dpll5_m2_d20_ck", &dpll5_m2_d20_ck),
4294 CLK(NULL, "usim_fck", &usim_fck),
4295 CLK(NULL, "usim_ick", &usim_ick),
4296 { NULL },
4297};
4298
4299static struct ti_clk_alias omap3xxx_clks[] = {
4300 CLK(NULL, "apb_pclk", &dummy_apb_pclk),
4301 CLK(NULL, "omap_32k_fck", &omap_32k_fck),
4302 CLK(NULL, "virt_12m_ck", &virt_12m_ck),
4303 CLK(NULL, "virt_13m_ck", &virt_13m_ck),
4304 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
4305 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
4306 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck),
4307 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck),
4308 CLK(NULL, "osc_sys_ck", &osc_sys_ck),
4309 CLK("twl", "fck", &osc_sys_ck),
4310 CLK(NULL, "sys_ck", &sys_ck),
4311 CLK(NULL, "timer_sys_ck", &sys_ck),
4312 CLK(NULL, "dpll4_ck", &dpll4_ck),
4313 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck),
4314 CLK(NULL, "dpll4_m2x2_mul_ck", &dpll4_m2x2_mul_ck),
4315 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck),
4316 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck),
4317 CLK(NULL, "dpll3_ck", &dpll3_ck),
4318 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck),
4319 CLK(NULL, "dpll3_m3x2_mul_ck", &dpll3_m3x2_mul_ck),
4320 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck),
4321 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck),
4322 CLK(NULL, "sys_altclk", &sys_altclk),
4323 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
4324 CLK(NULL, "sys_clkout1", &sys_clkout1),
4325 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck),
4326 CLK(NULL, "core_ck", &core_ck),
4327 CLK(NULL, "dpll1_fck", &dpll1_fck),
4328 CLK(NULL, "dpll1_ck", &dpll1_ck),
4329 CLK(NULL, "cpufreq_ck", &dpll1_ck),
4330 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck),
4331 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck),
4332 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck),
4333 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck),
4334 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck),
4335 CLK(NULL, "cm_96m_fck", &cm_96m_fck),
4336 CLK(NULL, "omap_96m_fck", &omap_96m_fck),
4337 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck),
4338 CLK(NULL, "dpll4_m3x2_mul_ck", &dpll4_m3x2_mul_ck),
4339 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck),
4340 CLK(NULL, "omap_54m_fck", &omap_54m_fck),
4341 CLK(NULL, "cm_96m_d2_fck", &cm_96m_d2_fck),
4342 CLK(NULL, "omap_48m_fck", &omap_48m_fck),
4343 CLK(NULL, "omap_12m_fck", &omap_12m_fck),
4344 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck),
4345 CLK(NULL, "dpll4_m4x2_mul_ck", &dpll4_m4x2_mul_ck),
4346 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck),
4347 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck),
4348 CLK(NULL, "dpll4_m5x2_mul_ck", &dpll4_m5x2_mul_ck),
4349 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck),
4350 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck),
4351 CLK(NULL, "dpll4_m6x2_mul_ck", &dpll4_m6x2_mul_ck),
4352 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck),
4353 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck),
4354 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck),
4355 CLK(NULL, "sys_clkout2", &sys_clkout2),
4356 CLK(NULL, "corex2_fck", &corex2_fck),
4357 CLK(NULL, "mpu_ck", &mpu_ck),
4358 CLK(NULL, "arm_fck", &arm_fck),
4359 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck),
4360 CLK(NULL, "l3_ick", &l3_ick),
4361 CLK(NULL, "l4_ick", &l4_ick),
4362 CLK(NULL, "rm_ick", &rm_ick),
4363 CLK(NULL, "timer_32k_ck", &omap_32k_fck),
4364 CLK(NULL, "gpt10_fck", &gpt10_fck),
4365 CLK(NULL, "gpt11_fck", &gpt11_fck),
4366 CLK(NULL, "core_96m_fck", &core_96m_fck),
4367 CLK(NULL, "mmchs2_fck", &mmchs2_fck),
4368 CLK(NULL, "mmchs1_fck", &mmchs1_fck),
4369 CLK(NULL, "i2c3_fck", &i2c3_fck),
4370 CLK(NULL, "i2c2_fck", &i2c2_fck),
4371 CLK(NULL, "i2c1_fck", &i2c1_fck),
4372 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
4373 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
4374 CLK(NULL, "core_48m_fck", &core_48m_fck),
4375 CLK(NULL, "mcspi4_fck", &mcspi4_fck),
4376 CLK(NULL, "mcspi3_fck", &mcspi3_fck),
4377 CLK(NULL, "mcspi2_fck", &mcspi2_fck),
4378 CLK(NULL, "mcspi1_fck", &mcspi1_fck),
4379 CLK(NULL, "uart2_fck", &uart2_fck),
4380 CLK(NULL, "uart1_fck", &uart1_fck),
4381 CLK(NULL, "core_12m_fck", &core_12m_fck),
4382 CLK("omap_hdq.0", "fck", &hdq_fck),
4383 CLK(NULL, "hdq_fck", &hdq_fck),
4384 CLK(NULL, "core_l3_ick", &core_l3_ick),
4385 CLK(NULL, "sdrc_ick", &sdrc_ick),
4386 CLK(NULL, "gpmc_fck", &gpmc_fck),
4387 CLK(NULL, "core_l4_ick", &core_l4_ick),
4388 CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
4389 CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
4390 CLK(NULL, "mmchs2_ick", &mmchs2_ick),
4391 CLK(NULL, "mmchs1_ick", &mmchs1_ick),
4392 CLK("omap_hdq.0", "ick", &hdq_ick),
4393 CLK(NULL, "hdq_ick", &hdq_ick),
4394 CLK("omap2_mcspi.4", "ick", &mcspi4_ick),
4395 CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
4396 CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
4397 CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
4398 CLK(NULL, "mcspi4_ick", &mcspi4_ick),
4399 CLK(NULL, "mcspi3_ick", &mcspi3_ick),
4400 CLK(NULL, "mcspi2_ick", &mcspi2_ick),
4401 CLK(NULL, "mcspi1_ick", &mcspi1_ick),
4402 CLK("omap_i2c.3", "ick", &i2c3_ick),
4403 CLK("omap_i2c.2", "ick", &i2c2_ick),
4404 CLK("omap_i2c.1", "ick", &i2c1_ick),
4405 CLK(NULL, "i2c3_ick", &i2c3_ick),
4406 CLK(NULL, "i2c2_ick", &i2c2_ick),
4407 CLK(NULL, "i2c1_ick", &i2c1_ick),
4408 CLK(NULL, "uart2_ick", &uart2_ick),
4409 CLK(NULL, "uart1_ick", &uart1_ick),
4410 CLK(NULL, "gpt11_ick", &gpt11_ick),
4411 CLK(NULL, "gpt10_ick", &gpt10_ick),
4412 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
4413 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
4414 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
4415 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
4416 CLK(NULL, "omapctrl_ick", &omapctrl_ick),
4417 CLK(NULL, "dss_tv_fck", &dss_tv_fck),
4418 CLK(NULL, "dss_96m_fck", &dss_96m_fck),
4419 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck),
4420 CLK(NULL, "init_60m_fclk", &dummy_ck),
4421 CLK(NULL, "gpt1_fck", &gpt1_fck),
4422 CLK(NULL, "aes2_ick", &aes2_ick),
4423 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck),
4424 CLK(NULL, "gpio1_dbck", &gpio1_dbck),
4425 CLK(NULL, "sha12_ick", &sha12_ick),
4426 CLK(NULL, "wdt2_fck", &wdt2_fck),
4427 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick),
4428 CLK("omap_wdt", "ick", &wdt2_ick),
4429 CLK(NULL, "wdt2_ick", &wdt2_ick),
4430 CLK(NULL, "wdt1_ick", &wdt1_ick),
4431 CLK(NULL, "gpio1_ick", &gpio1_ick),
4432 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick),
4433 CLK(NULL, "gpt12_ick", &gpt12_ick),
4434 CLK(NULL, "gpt1_ick", &gpt1_ick),
4435 CLK(NULL, "per_96m_fck", &per_96m_fck),
4436 CLK(NULL, "per_48m_fck", &per_48m_fck),
4437 CLK(NULL, "uart3_fck", &uart3_fck),
4438 CLK(NULL, "gpt2_fck", &gpt2_fck),
4439 CLK(NULL, "gpt3_fck", &gpt3_fck),
4440 CLK(NULL, "gpt4_fck", &gpt4_fck),
4441 CLK(NULL, "gpt5_fck", &gpt5_fck),
4442 CLK(NULL, "gpt6_fck", &gpt6_fck),
4443 CLK(NULL, "gpt7_fck", &gpt7_fck),
4444 CLK(NULL, "gpt8_fck", &gpt8_fck),
4445 CLK(NULL, "gpt9_fck", &gpt9_fck),
4446 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck),
4447 CLK(NULL, "gpio6_dbck", &gpio6_dbck),
4448 CLK(NULL, "gpio5_dbck", &gpio5_dbck),
4449 CLK(NULL, "gpio4_dbck", &gpio4_dbck),
4450 CLK(NULL, "gpio3_dbck", &gpio3_dbck),
4451 CLK(NULL, "gpio2_dbck", &gpio2_dbck),
4452 CLK(NULL, "wdt3_fck", &wdt3_fck),
4453 CLK(NULL, "per_l4_ick", &per_l4_ick),
4454 CLK(NULL, "gpio6_ick", &gpio6_ick),
4455 CLK(NULL, "gpio5_ick", &gpio5_ick),
4456 CLK(NULL, "gpio4_ick", &gpio4_ick),
4457 CLK(NULL, "gpio3_ick", &gpio3_ick),
4458 CLK(NULL, "gpio2_ick", &gpio2_ick),
4459 CLK(NULL, "wdt3_ick", &wdt3_ick),
4460 CLK(NULL, "uart3_ick", &uart3_ick),
4461 CLK(NULL, "uart4_ick", &uart4_ick),
4462 CLK(NULL, "gpt9_ick", &gpt9_ick),
4463 CLK(NULL, "gpt8_ick", &gpt8_ick),
4464 CLK(NULL, "gpt7_ick", &gpt7_ick),
4465 CLK(NULL, "gpt6_ick", &gpt6_ick),
4466 CLK(NULL, "gpt5_ick", &gpt5_ick),
4467 CLK(NULL, "gpt4_ick", &gpt4_ick),
4468 CLK(NULL, "gpt3_ick", &gpt3_ick),
4469 CLK(NULL, "gpt2_ick", &gpt2_ick),
4470 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
4471 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
4472 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
4473 CLK(NULL, "mcbsp4_ick", &mcbsp2_ick),
4474 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
4475 CLK(NULL, "mcbsp2_ick", &mcbsp4_ick),
4476 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
4477 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
4478 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
4479 CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck),
4480 CLK("etb", "emu_src_ck", &emu_src_ck),
4481 CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck),
4482 CLK(NULL, "emu_src_ck", &emu_src_ck),
4483 CLK(NULL, "pclk_fck", &pclk_fck),
4484 CLK(NULL, "pclkx2_fck", &pclkx2_fck),
4485 CLK(NULL, "atclk_fck", &atclk_fck),
4486 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck),
4487 CLK(NULL, "traceclk_fck", &traceclk_fck),
4488 CLK(NULL, "secure_32k_fck", &secure_32k_fck),
4489 CLK(NULL, "gpt12_fck", &gpt12_fck),
4490 CLK(NULL, "wdt1_fck", &wdt1_fck),
4491 { NULL },
4492};
4493
4494static struct ti_clk_alias omap36xx_am35xx_omap3430es2plus_clks[] = {
4495 CLK(NULL, "dpll5_ck", &dpll5_ck),
4496 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck),
4497 CLK(NULL, "core_d3_ck", &core_d3_ck),
4498 CLK(NULL, "core_d4_ck", &core_d4_ck),
4499 CLK(NULL, "core_d6_ck", &core_d6_ck),
4500 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck),
4501 CLK(NULL, "core_d2_ck", &core_d2_ck),
4502 CLK(NULL, "corex2_d3_fck", &corex2_d3_fck),
4503 CLK(NULL, "corex2_d5_fck", &corex2_d5_fck),
4504 CLK(NULL, "sgx_fck", &sgx_fck),
4505 CLK(NULL, "sgx_ick", &sgx_ick),
4506 CLK(NULL, "cpefuse_fck", &cpefuse_fck),
4507 CLK(NULL, "ts_fck", &ts_fck),
4508 CLK(NULL, "usbtll_fck", &usbtll_fck),
4509 CLK(NULL, "usbtll_ick", &usbtll_ick),
4510 CLK("omap_hsmmc.2", "ick", &mmchs3_ick),
4511 CLK(NULL, "mmchs3_ick", &mmchs3_ick),
4512 CLK(NULL, "mmchs3_fck", &mmchs3_fck),
4513 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2),
4514 CLK("omapdss_dss", "ick", &dss_ick_3430es2),
4515 CLK(NULL, "dss_ick", &dss_ick_3430es2),
4516 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck),
4517 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck),
4518 CLK(NULL, "usbhost_ick", &usbhost_ick),
4519 { NULL },
4520};
4521
4522static struct ti_clk_alias omap3430es1_clks[] = {
4523 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck),
4524 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck),
4525 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick),
4526 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck),
4527 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck),
4528 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck),
4529 CLK(NULL, "fshostusb_fck", &fshostusb_fck),
4530 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1),
4531 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1),
4532 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1),
4533 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1),
4534 CLK(NULL, "fac_ick", &fac_ick),
4535 CLK(NULL, "ssi_ick", &ssi_ick_3430es1),
4536 CLK(NULL, "usb_l4_ick", &usb_l4_ick),
4537 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1),
4538 CLK("omapdss_dss", "ick", &dss_ick_3430es1),
4539 CLK(NULL, "dss_ick", &dss_ick_3430es1),
4540 { NULL },
4541};
4542
4543static struct ti_clk_alias omap36xx_clks[] = {
4544 CLK(NULL, "uart4_fck", &uart4_fck),
4545 { NULL },
4546};
4547
4548static struct ti_clk_alias am35xx_clks[] = {
4549 CLK(NULL, "ipss_ick", &ipss_ick),
4550 CLK(NULL, "rmii_ck", &rmii_ck),
4551 CLK(NULL, "pclk_ck", &pclk_ck),
4552 CLK(NULL, "emac_ick", &emac_ick),
4553 CLK(NULL, "emac_fck", &emac_fck),
4554 CLK("davinci_emac.0", NULL, &emac_ick),
4555 CLK("davinci_mdio.0", NULL, &emac_fck),
4556 CLK("vpfe-capture", "master", &vpfe_ick),
4557 CLK("vpfe-capture", "slave", &vpfe_fck),
4558 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx),
4559 CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx),
4560 CLK(NULL, "hecc_ck", &hecc_ck),
4561 CLK(NULL, "uart4_ick", &uart4_ick_am35xx),
4562 CLK(NULL, "uart4_fck", &uart4_fck_am35xx),
4563 { NULL },
4564};
4565
4566static struct ti_clk *omap36xx_clk_patches[] = {
4567 &dpll4_m3x2_ck_omap36xx,
4568 &dpll3_m3x2_ck_omap36xx,
4569 &dpll4_m6x2_ck_omap36xx,
4570 &dpll4_m2x2_ck_omap36xx,
4571 &dpll4_m5x2_ck_omap36xx,
4572 &dpll4_ck_omap36xx,
4573 NULL,
4574};
4575
4576static const char *enable_init_clks[] = {
4577 "sdrc_ick",
4578 "gpmc_fck",
4579 "omapctrl_ick",
4580};
4581
4582static void __init omap3_clk_legacy_common_init(void)
4583{
4584 omap2_clk_disable_autoidle_all();
4585
4586 omap2_clk_enable_init_clocks(enable_init_clks,
4587 ARRAY_SIZE(enable_init_clks));
4588
4589 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
4590 (clk_get_rate(osc_sys_ck.clk) / 1000000),
4591 (clk_get_rate(osc_sys_ck.clk) / 100000) % 10,
4592 (clk_get_rate(core_ck.clk) / 1000000),
4593 (clk_get_rate(arm_fck.clk) / 1000000));
4594}
4595
4596int __init omap3430es1_clk_legacy_init(void)
4597{
4598 int r;
4599
4600 r = ti_clk_register_legacy_clks(omap3430es1_clks);
4601 r |= ti_clk_register_legacy_clks(omap34xx_omap36xx_clks);
4602 r |= ti_clk_register_legacy_clks(omap3xxx_clks);
4603
4604 omap3_clk_legacy_common_init();
4605
4606 return r;
4607}
4608
4609int __init omap3430_clk_legacy_init(void)
4610{
4611 int r;
4612
4613 r = ti_clk_register_legacy_clks(omap34xx_omap36xx_clks);
4614 r |= ti_clk_register_legacy_clks(omap36xx_omap3430es2plus_clks);
4615 r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks);
4616 r |= ti_clk_register_legacy_clks(omap3xxx_clks);
4617
4618 omap3_clk_legacy_common_init();
4619 omap3_clk_lock_dpll5();
4620
4621 return r;
4622}
4623
4624int __init omap36xx_clk_legacy_init(void)
4625{
4626 int r;
4627
4628 ti_clk_patch_legacy_clks(omap36xx_clk_patches);
4629 r = ti_clk_register_legacy_clks(omap36xx_clks);
4630 r |= ti_clk_register_legacy_clks(omap36xx_omap3430es2plus_clks);
4631 r |= ti_clk_register_legacy_clks(omap34xx_omap36xx_clks);
4632 r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks);
4633 r |= ti_clk_register_legacy_clks(omap3xxx_clks);
4634
4635 omap3_clk_legacy_common_init();
4636 omap3_clk_lock_dpll5();
4637
4638 return r;
4639}
4640
4641int __init am35xx_clk_legacy_init(void)
4642{
4643 int r;
4644
4645 r = ti_clk_register_legacy_clks(am35xx_clks);
4646 r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks);
4647 r |= ti_clk_register_legacy_clks(omap3xxx_clks);
4648
4649 omap3_clk_legacy_common_init();
4650 omap3_clk_lock_dpll5();
4651
4652 return r;
4653}
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index 337abe5909e1..546dae405402 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -22,6 +22,8 @@
22#include <linux/of_address.h> 22#include <linux/of_address.h>
23#include <linux/list.h> 23#include <linux/list.h>
24 24
25#include "clock.h"
26
25#undef pr_fmt 27#undef pr_fmt
26#define pr_fmt(fmt) "%s: " fmt, __func__ 28#define pr_fmt(fmt) "%s: " fmt, __func__
27 29
@@ -183,3 +185,126 @@ void ti_dt_clk_init_retry_clks(void)
183 retries--; 185 retries--;
184 } 186 }
185} 187}
188
189void __init ti_clk_patch_legacy_clks(struct ti_clk **patch)
190{
191 while (*patch) {
192 memcpy((*patch)->patch, *patch, sizeof(**patch));
193 patch++;
194 }
195}
196
197struct clk __init *ti_clk_register_clk(struct ti_clk *setup)
198{
199 struct clk *clk;
200 struct ti_clk_fixed *fixed;
201 struct ti_clk_fixed_factor *fixed_factor;
202 struct clk_hw *clk_hw;
203
204 if (setup->clk)
205 return setup->clk;
206
207 switch (setup->type) {
208 case TI_CLK_FIXED:
209 fixed = setup->data;
210
211 clk = clk_register_fixed_rate(NULL, setup->name, NULL,
212 CLK_IS_ROOT, fixed->frequency);
213 break;
214 case TI_CLK_MUX:
215 clk = ti_clk_register_mux(setup);
216 break;
217 case TI_CLK_DIVIDER:
218 clk = ti_clk_register_divider(setup);
219 break;
220 case TI_CLK_COMPOSITE:
221 clk = ti_clk_register_composite(setup);
222 break;
223 case TI_CLK_FIXED_FACTOR:
224 fixed_factor = setup->data;
225
226 clk = clk_register_fixed_factor(NULL, setup->name,
227 fixed_factor->parent,
228 0, fixed_factor->mult,
229 fixed_factor->div);
230 break;
231 case TI_CLK_GATE:
232 clk = ti_clk_register_gate(setup);
233 break;
234 case TI_CLK_DPLL:
235 clk = ti_clk_register_dpll(setup);
236 break;
237 default:
238 pr_err("bad type for %s!\n", setup->name);
239 clk = ERR_PTR(-EINVAL);
240 }
241
242 if (!IS_ERR(clk)) {
243 setup->clk = clk;
244 if (setup->clkdm_name) {
245 if (__clk_get_flags(clk) & CLK_IS_BASIC) {
246 pr_warn("can't setup clkdm for basic clk %s\n",
247 setup->name);
248 } else {
249 clk_hw = __clk_get_hw(clk);
250 to_clk_hw_omap(clk_hw)->clkdm_name =
251 setup->clkdm_name;
252 omap2_init_clk_clkdm(clk_hw);
253 }
254 }
255 }
256
257 return clk;
258}
259
260int __init ti_clk_register_legacy_clks(struct ti_clk_alias *clks)
261{
262 struct clk *clk;
263 bool retry;
264 struct ti_clk_alias *retry_clk;
265 struct ti_clk_alias *tmp;
266
267 while (clks->clk) {
268 clk = ti_clk_register_clk(clks->clk);
269 if (IS_ERR(clk)) {
270 if (PTR_ERR(clk) == -EAGAIN) {
271 list_add(&clks->link, &retry_list);
272 } else {
273 pr_err("register for %s failed: %ld\n",
274 clks->clk->name, PTR_ERR(clk));
275 return PTR_ERR(clk);
276 }
277 } else {
278 clks->lk.clk = clk;
279 clkdev_add(&clks->lk);
280 }
281 clks++;
282 }
283
284 retry = true;
285
286 while (!list_empty(&retry_list) && retry) {
287 retry = false;
288 list_for_each_entry_safe(retry_clk, tmp, &retry_list, link) {
289 pr_debug("retry-init: %s\n", retry_clk->clk->name);
290 clk = ti_clk_register_clk(retry_clk->clk);
291 if (IS_ERR(clk)) {
292 if (PTR_ERR(clk) == -EAGAIN) {
293 continue;
294 } else {
295 pr_err("register for %s failed: %ld\n",
296 retry_clk->clk->name,
297 PTR_ERR(clk));
298 return PTR_ERR(clk);
299 }
300 } else {
301 retry = true;
302 retry_clk->lk.clk = clk;
303 clkdev_add(&retry_clk->lk);
304 list_del(&retry_clk->link);
305 }
306 }
307 }
308
309 return 0;
310}
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
new file mode 100644
index 000000000000..404158d2d7f8
--- /dev/null
+++ b/drivers/clk/ti/clock.h
@@ -0,0 +1,172 @@
1/*
2 * TI Clock driver internal definitions
3 *
4 * Copyright (C) 2014 Texas Instruments, Inc
5 * Tero Kristo (t-kristo@ti.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16#ifndef __DRIVERS_CLK_TI_CLOCK__
17#define __DRIVERS_CLK_TI_CLOCK__
18
19enum {
20 TI_CLK_FIXED,
21 TI_CLK_MUX,
22 TI_CLK_DIVIDER,
23 TI_CLK_COMPOSITE,
24 TI_CLK_FIXED_FACTOR,
25 TI_CLK_GATE,
26 TI_CLK_DPLL,
27};
28
29/* Global flags */
30#define CLKF_INDEX_POWER_OF_TWO (1 << 0)
31#define CLKF_INDEX_STARTS_AT_ONE (1 << 1)
32#define CLKF_SET_RATE_PARENT (1 << 2)
33#define CLKF_OMAP3 (1 << 3)
34#define CLKF_AM35XX (1 << 4)
35
36/* Gate flags */
37#define CLKF_SET_BIT_TO_DISABLE (1 << 5)
38#define CLKF_INTERFACE (1 << 6)
39#define CLKF_SSI (1 << 7)
40#define CLKF_DSS (1 << 8)
41#define CLKF_HSOTGUSB (1 << 9)
42#define CLKF_WAIT (1 << 10)
43#define CLKF_NO_WAIT (1 << 11)
44#define CLKF_HSDIV (1 << 12)
45#define CLKF_CLKDM (1 << 13)
46
47/* DPLL flags */
48#define CLKF_LOW_POWER_STOP (1 << 5)
49#define CLKF_LOCK (1 << 6)
50#define CLKF_LOW_POWER_BYPASS (1 << 7)
51#define CLKF_PER (1 << 8)
52#define CLKF_CORE (1 << 9)
53#define CLKF_J_TYPE (1 << 10)
54
55#define CLK(dev, con, ck) \
56 { \
57 .lk = { \
58 .dev_id = dev, \
59 .con_id = con, \
60 }, \
61 .clk = ck, \
62 }
63
64struct ti_clk {
65 const char *name;
66 const char *clkdm_name;
67 int type;
68 void *data;
69 struct ti_clk *patch;
70 struct clk *clk;
71};
72
73struct ti_clk_alias {
74 struct ti_clk *clk;
75 struct clk_lookup lk;
76 struct list_head link;
77};
78
79struct ti_clk_fixed {
80 u32 frequency;
81 u16 flags;
82};
83
84struct ti_clk_mux {
85 u8 bit_shift;
86 int num_parents;
87 u16 reg;
88 u8 module;
89 const char **parents;
90 u16 flags;
91};
92
93struct ti_clk_divider {
94 const char *parent;
95 u8 bit_shift;
96 u16 max_div;
97 u16 reg;
98 u8 module;
99 int *dividers;
100 int num_dividers;
101 u16 flags;
102};
103
104struct ti_clk_fixed_factor {
105 const char *parent;
106 u16 div;
107 u16 mult;
108 u16 flags;
109};
110
111struct ti_clk_gate {
112 const char *parent;
113 u8 bit_shift;
114 u16 reg;
115 u8 module;
116 u16 flags;
117};
118
119struct ti_clk_composite {
120 struct ti_clk_divider *divider;
121 struct ti_clk_mux *mux;
122 struct ti_clk_gate *gate;
123 u16 flags;
124};
125
126struct ti_clk_clkdm_gate {
127 const char *parent;
128 u16 flags;
129};
130
131struct ti_clk_dpll {
132 int num_parents;
133 u16 control_reg;
134 u16 idlest_reg;
135 u16 autoidle_reg;
136 u16 mult_div1_reg;
137 u8 module;
138 const char **parents;
139 u16 flags;
140 u8 modes;
141 u32 mult_mask;
142 u32 div1_mask;
143 u32 enable_mask;
144 u32 autoidle_mask;
145 u32 freqsel_mask;
146 u32 idlest_mask;
147 u32 dco_mask;
148 u32 sddiv_mask;
149 u16 max_multiplier;
150 u16 max_divider;
151 u8 min_divider;
152 u8 auto_recal_bit;
153 u8 recal_en_bit;
154 u8 recal_st_bit;
155};
156
157struct clk *ti_clk_register_gate(struct ti_clk *setup);
158struct clk *ti_clk_register_interface(struct ti_clk *setup);
159struct clk *ti_clk_register_mux(struct ti_clk *setup);
160struct clk *ti_clk_register_divider(struct ti_clk *setup);
161struct clk *ti_clk_register_composite(struct ti_clk *setup);
162struct clk *ti_clk_register_dpll(struct ti_clk *setup);
163
164struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup);
165struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup);
166struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
167
168void ti_clk_patch_legacy_clks(struct ti_clk **patch);
169struct clk *ti_clk_register_clk(struct ti_clk *setup);
170int ti_clk_register_legacy_clks(struct ti_clk_alias *clks);
171
172#endif
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
index 19d8980ba458..3a9665fce041 100644
--- a/drivers/clk/ti/composite.c
+++ b/drivers/clk/ti/composite.c
@@ -23,6 +23,8 @@
23#include <linux/clk/ti.h> 23#include <linux/clk/ti.h>
24#include <linux/list.h> 24#include <linux/list.h>
25 25
26#include "clock.h"
27
26#undef pr_fmt 28#undef pr_fmt
27#define pr_fmt(fmt) "%s: " fmt, __func__ 29#define pr_fmt(fmt) "%s: " fmt, __func__
28 30
@@ -116,8 +118,44 @@ static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx)
116 118
117#define to_clk_hw_comp(_hw) container_of(_hw, struct clk_hw_omap_comp, hw) 119#define to_clk_hw_comp(_hw) container_of(_hw, struct clk_hw_omap_comp, hw)
118 120
119static void __init ti_clk_register_composite(struct clk_hw *hw, 121struct clk *ti_clk_register_composite(struct ti_clk *setup)
120 struct device_node *node) 122{
123 struct ti_clk_composite *comp;
124 struct clk_hw *gate;
125 struct clk_hw *mux;
126 struct clk_hw *div;
127 int num_parents = 1;
128 const char **parent_names = NULL;
129 struct clk *clk;
130
131 comp = setup->data;
132
133 div = ti_clk_build_component_div(comp->divider);
134 gate = ti_clk_build_component_gate(comp->gate);
135 mux = ti_clk_build_component_mux(comp->mux);
136
137 if (div)
138 parent_names = &comp->divider->parent;
139
140 if (gate)
141 parent_names = &comp->gate->parent;
142
143 if (mux) {
144 num_parents = comp->mux->num_parents;
145 parent_names = comp->mux->parents;
146 }
147
148 clk = clk_register_composite(NULL, setup->name,
149 parent_names, num_parents, mux,
150 &ti_clk_mux_ops, div,
151 &ti_composite_divider_ops, gate,
152 &ti_composite_gate_ops, 0);
153
154 return clk;
155}
156
157static void __init _register_composite(struct clk_hw *hw,
158 struct device_node *node)
121{ 159{
122 struct clk *clk; 160 struct clk *clk;
123 struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw); 161 struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw);
@@ -136,7 +174,7 @@ static void __init ti_clk_register_composite(struct clk_hw *hw,
136 pr_debug("component %s not ready for %s, retry\n", 174 pr_debug("component %s not ready for %s, retry\n",
137 cclk->comp_nodes[i]->name, node->name); 175 cclk->comp_nodes[i]->name, node->name);
138 if (!ti_clk_retry_init(node, hw, 176 if (!ti_clk_retry_init(node, hw,
139 ti_clk_register_composite)) 177 _register_composite))
140 return; 178 return;
141 179
142 goto cleanup; 180 goto cleanup;
@@ -216,7 +254,7 @@ static void __init of_ti_composite_clk_setup(struct device_node *node)
216 for (i = 0; i < num_clks; i++) 254 for (i = 0; i < num_clks; i++)
217 cclk->comp_nodes[i] = _get_component_node(node, i); 255 cclk->comp_nodes[i] = _get_component_node(node, i);
218 256
219 ti_clk_register_composite(&cclk->hw, node); 257 _register_composite(&cclk->hw, node);
220} 258}
221CLK_OF_DECLARE(ti_composite_clock, "ti,composite-clock", 259CLK_OF_DECLARE(ti_composite_clock, "ti,composite-clock",
222 of_ti_composite_clk_setup); 260 of_ti_composite_clk_setup);
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
index bff2b5b8ff59..6211893c0980 100644
--- a/drivers/clk/ti/divider.c
+++ b/drivers/clk/ti/divider.c
@@ -21,6 +21,7 @@
21#include <linux/of.h> 21#include <linux/of.h>
22#include <linux/of_address.h> 22#include <linux/of_address.h>
23#include <linux/clk/ti.h> 23#include <linux/clk/ti.h>
24#include "clock.h"
24 25
25#undef pr_fmt 26#undef pr_fmt
26#define pr_fmt(fmt) "%s: " fmt, __func__ 27#define pr_fmt(fmt) "%s: " fmt, __func__
@@ -301,6 +302,134 @@ static struct clk *_register_divider(struct device *dev, const char *name,
301} 302}
302 303
303static struct clk_div_table * 304static struct clk_div_table *
305_get_div_table_from_setup(struct ti_clk_divider *setup, u8 *width)
306{
307 int valid_div = 0;
308 struct clk_div_table *table;
309 int i;
310 int div;
311 u32 val;
312 u8 flags;
313
314 if (!setup->num_dividers) {
315 /* Clk divider table not provided, determine min/max divs */
316 flags = setup->flags;
317
318 if (flags & CLKF_INDEX_STARTS_AT_ONE)
319 val = 1;
320 else
321 val = 0;
322
323 div = 1;
324
325 while (div < setup->max_div) {
326 if (flags & CLKF_INDEX_POWER_OF_TWO)
327 div <<= 1;
328 else
329 div++;
330 val++;
331 }
332
333 *width = fls(val);
334
335 return NULL;
336 }
337
338 for (i = 0; i < setup->num_dividers; i++)
339 if (setup->dividers[i])
340 valid_div++;
341
342 table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL);
343 if (!table)
344 return ERR_PTR(-ENOMEM);
345
346 valid_div = 0;
347 *width = 0;
348
349 for (i = 0; i < setup->num_dividers; i++)
350 if (setup->dividers[i]) {
351 table[valid_div].div = setup->dividers[i];
352 table[valid_div].val = i;
353 valid_div++;
354 *width = i;
355 }
356
357 *width = fls(*width);
358
359 return table;
360}
361
362struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup)
363{
364 struct clk_divider *div;
365 struct clk_omap_reg *reg;
366
367 if (!setup)
368 return NULL;
369
370 div = kzalloc(sizeof(*div), GFP_KERNEL);
371 if (!div)
372 return ERR_PTR(-ENOMEM);
373
374 reg = (struct clk_omap_reg *)&div->reg;
375 reg->index = setup->module;
376 reg->offset = setup->reg;
377
378 if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
379 div->flags |= CLK_DIVIDER_ONE_BASED;
380
381 if (setup->flags & CLKF_INDEX_POWER_OF_TWO)
382 div->flags |= CLK_DIVIDER_POWER_OF_TWO;
383
384 div->table = _get_div_table_from_setup(setup, &div->width);
385
386 div->shift = setup->bit_shift;
387
388 return &div->hw;
389}
390
391struct clk *ti_clk_register_divider(struct ti_clk *setup)
392{
393 struct ti_clk_divider *div;
394 struct clk_omap_reg *reg_setup;
395 u32 reg;
396 u8 width;
397 u32 flags = 0;
398 u8 div_flags = 0;
399 struct clk_div_table *table;
400 struct clk *clk;
401
402 div = setup->data;
403
404 reg_setup = (struct clk_omap_reg *)&reg;
405
406 reg_setup->index = div->module;
407 reg_setup->offset = div->reg;
408
409 if (div->flags & CLKF_INDEX_STARTS_AT_ONE)
410 div_flags |= CLK_DIVIDER_ONE_BASED;
411
412 if (div->flags & CLKF_INDEX_POWER_OF_TWO)
413 div_flags |= CLK_DIVIDER_POWER_OF_TWO;
414
415 if (div->flags & CLKF_SET_RATE_PARENT)
416 flags |= CLK_SET_RATE_PARENT;
417
418 table = _get_div_table_from_setup(div, &width);
419 if (IS_ERR(table))
420 return (struct clk *)table;
421
422 clk = _register_divider(NULL, setup->name, div->parent,
423 flags, (void __iomem *)reg, div->bit_shift,
424 width, div_flags, table, NULL);
425
426 if (IS_ERR(clk))
427 kfree(table);
428
429 return clk;
430}
431
432static struct clk_div_table *
304__init ti_clk_get_div_table(struct device_node *node) 433__init ti_clk_get_div_table(struct device_node *node)
305{ 434{
306 struct clk_div_table *table; 435 struct clk_div_table *table;
@@ -455,7 +584,8 @@ static void __init of_ti_divider_clk_setup(struct device_node *node)
455 goto cleanup; 584 goto cleanup;
456 585
457 clk = _register_divider(NULL, node->name, parent_name, flags, reg, 586 clk = _register_divider(NULL, node->name, parent_name, flags, reg,
458 shift, width, clk_divider_flags, table, NULL); 587 shift, width, clk_divider_flags, table,
588 NULL);
459 589
460 if (!IS_ERR(clk)) { 590 if (!IS_ERR(clk)) {
461 of_clk_add_provider(node, of_clk_src_simple_get, clk); 591 of_clk_add_provider(node, of_clk_src_simple_get, clk);
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index 85ac0dd501de..47ebff772b13 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -21,6 +21,7 @@
21#include <linux/of.h> 21#include <linux/of.h>
22#include <linux/of_address.h> 22#include <linux/of_address.h>
23#include <linux/clk/ti.h> 23#include <linux/clk/ti.h>
24#include "clock.h"
24 25
25#undef pr_fmt 26#undef pr_fmt
26#define pr_fmt(fmt) "%s: " fmt, __func__ 27#define pr_fmt(fmt) "%s: " fmt, __func__
@@ -130,7 +131,7 @@ static const struct clk_ops dpll_x2_ck_ops = {
130}; 131};
131 132
132/** 133/**
133 * ti_clk_register_dpll - low level registration of a DPLL clock 134 * _register_dpll - low level registration of a DPLL clock
134 * @hw: hardware clock definition for the clock 135 * @hw: hardware clock definition for the clock
135 * @node: device node for the clock 136 * @node: device node for the clock
136 * 137 *
@@ -138,8 +139,8 @@ static const struct clk_ops dpll_x2_ck_ops = {
138 * clk-bypass is missing), the clock is added to retry list and 139 * clk-bypass is missing), the clock is added to retry list and
139 * the initialization is retried on later stage. 140 * the initialization is retried on later stage.
140 */ 141 */
141static void __init ti_clk_register_dpll(struct clk_hw *hw, 142static void __init _register_dpll(struct clk_hw *hw,
142 struct device_node *node) 143 struct device_node *node)
143{ 144{
144 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); 145 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
145 struct dpll_data *dd = clk_hw->dpll_data; 146 struct dpll_data *dd = clk_hw->dpll_data;
@@ -151,7 +152,7 @@ static void __init ti_clk_register_dpll(struct clk_hw *hw,
151 if (IS_ERR(dd->clk_ref) || IS_ERR(dd->clk_bypass)) { 152 if (IS_ERR(dd->clk_ref) || IS_ERR(dd->clk_bypass)) {
152 pr_debug("clk-ref or clk-bypass missing for %s, retry later\n", 153 pr_debug("clk-ref or clk-bypass missing for %s, retry later\n",
153 node->name); 154 node->name);
154 if (!ti_clk_retry_init(node, hw, ti_clk_register_dpll)) 155 if (!ti_clk_retry_init(node, hw, _register_dpll))
155 return; 156 return;
156 157
157 goto cleanup; 158 goto cleanup;
@@ -175,20 +176,116 @@ cleanup:
175 kfree(clk_hw); 176 kfree(clk_hw);
176} 177}
177 178
179void __iomem *_get_reg(u8 module, u16 offset)
180{
181 u32 reg;
182 struct clk_omap_reg *reg_setup;
183
184 reg_setup = (struct clk_omap_reg *)&reg;
185
186 reg_setup->index = module;
187 reg_setup->offset = offset;
188
189 return (void __iomem *)reg;
190}
191
192struct clk *ti_clk_register_dpll(struct ti_clk *setup)
193{
194 struct clk_hw_omap *clk_hw;
195 struct clk_init_data init = { NULL };
196 struct dpll_data *dd;
197 struct clk *clk;
198 struct ti_clk_dpll *dpll;
199 const struct clk_ops *ops = &omap3_dpll_ck_ops;
200 struct clk *clk_ref;
201 struct clk *clk_bypass;
202
203 dpll = setup->data;
204
205 if (dpll->num_parents < 2)
206 return ERR_PTR(-EINVAL);
207
208 clk_ref = clk_get_sys(NULL, dpll->parents[0]);
209 clk_bypass = clk_get_sys(NULL, dpll->parents[1]);
210
211 if (IS_ERR_OR_NULL(clk_ref) || IS_ERR_OR_NULL(clk_bypass))
212 return ERR_PTR(-EAGAIN);
213
214 dd = kzalloc(sizeof(*dd), GFP_KERNEL);
215 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
216 if (!dd || !clk_hw) {
217 clk = ERR_PTR(-ENOMEM);
218 goto cleanup;
219 }
220
221 clk_hw->dpll_data = dd;
222 clk_hw->ops = &clkhwops_omap3_dpll;
223 clk_hw->hw.init = &init;
224 clk_hw->flags = MEMMAP_ADDRESSING;
225
226 init.name = setup->name;
227 init.ops = ops;
228
229 init.num_parents = dpll->num_parents;
230 init.parent_names = dpll->parents;
231
232 dd->control_reg = _get_reg(dpll->module, dpll->control_reg);
233 dd->idlest_reg = _get_reg(dpll->module, dpll->idlest_reg);
234 dd->mult_div1_reg = _get_reg(dpll->module, dpll->mult_div1_reg);
235 dd->autoidle_reg = _get_reg(dpll->module, dpll->autoidle_reg);
236
237 dd->modes = dpll->modes;
238 dd->div1_mask = dpll->div1_mask;
239 dd->idlest_mask = dpll->idlest_mask;
240 dd->mult_mask = dpll->mult_mask;
241 dd->autoidle_mask = dpll->autoidle_mask;
242 dd->enable_mask = dpll->enable_mask;
243 dd->sddiv_mask = dpll->sddiv_mask;
244 dd->dco_mask = dpll->dco_mask;
245 dd->max_divider = dpll->max_divider;
246 dd->min_divider = dpll->min_divider;
247 dd->max_multiplier = dpll->max_multiplier;
248 dd->auto_recal_bit = dpll->auto_recal_bit;
249 dd->recal_en_bit = dpll->recal_en_bit;
250 dd->recal_st_bit = dpll->recal_st_bit;
251
252 dd->clk_ref = clk_ref;
253 dd->clk_bypass = clk_bypass;
254
255 if (dpll->flags & CLKF_CORE)
256 ops = &omap3_dpll_core_ck_ops;
257
258 if (dpll->flags & CLKF_PER)
259 ops = &omap3_dpll_per_ck_ops;
260
261 if (dpll->flags & CLKF_J_TYPE)
262 dd->flags |= DPLL_J_TYPE;
263
264 clk = clk_register(NULL, &clk_hw->hw);
265
266 if (!IS_ERR(clk))
267 return clk;
268
269cleanup:
270 kfree(dd);
271 kfree(clk_hw);
272 return clk;
273}
274
178#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 275#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
179 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \ 276 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
180 defined(CONFIG_SOC_AM43XX) 277 defined(CONFIG_SOC_AM43XX)
181/** 278/**
182 * ti_clk_register_dpll_x2 - Registers a DPLLx2 clock 279 * _register_dpll_x2 - Registers a DPLLx2 clock
183 * @node: device node for this clock 280 * @node: device node for this clock
184 * @ops: clk_ops for this clock 281 * @ops: clk_ops for this clock
185 * @hw_ops: clk_hw_ops for this clock 282 * @hw_ops: clk_hw_ops for this clock
186 * 283 *
187 * Initializes a DPLL x 2 clock from device tree data. 284 * Initializes a DPLL x 2 clock from device tree data.
188 */ 285 */
189static void ti_clk_register_dpll_x2(struct device_node *node, 286static void _register_dpll_x2(struct device_node *node,
190 const struct clk_ops *ops, 287 const struct clk_ops *ops,
191 const struct clk_hw_omap_ops *hw_ops) 288 const struct clk_hw_omap_ops *hw_ops)
192{ 289{
193 struct clk *clk; 290 struct clk *clk;
194 struct clk_init_data init = { NULL }; 291 struct clk_init_data init = { NULL };
@@ -318,7 +415,7 @@ static void __init of_ti_dpll_setup(struct device_node *node,
318 if (dpll_mode) 415 if (dpll_mode)
319 dd->modes = dpll_mode; 416 dd->modes = dpll_mode;
320 417
321 ti_clk_register_dpll(&clk_hw->hw, node); 418 _register_dpll(&clk_hw->hw, node);
322 return; 419 return;
323 420
324cleanup: 421cleanup:
@@ -332,7 +429,7 @@ cleanup:
332 defined(CONFIG_SOC_DRA7XX) 429 defined(CONFIG_SOC_DRA7XX)
333static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node) 430static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
334{ 431{
335 ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx); 432 _register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
336} 433}
337CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock", 434CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
338 of_ti_omap4_dpll_x2_setup); 435 of_ti_omap4_dpll_x2_setup);
@@ -341,7 +438,7 @@ CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
341#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 438#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
342static void __init of_ti_am3_dpll_x2_setup(struct device_node *node) 439static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
343{ 440{
344 ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, NULL); 441 _register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
345} 442}
346CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock", 443CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
347 of_ti_am3_dpll_x2_setup); 444 of_ti_am3_dpll_x2_setup);
diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c
index b326d2797feb..d4f6cb20e16e 100644
--- a/drivers/clk/ti/gate.c
+++ b/drivers/clk/ti/gate.c
@@ -22,6 +22,8 @@
22#include <linux/of_address.h> 22#include <linux/of_address.h>
23#include <linux/clk/ti.h> 23#include <linux/clk/ti.h>
24 24
25#include "clock.h"
26
25#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) 27#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
26 28
27#undef pr_fmt 29#undef pr_fmt
@@ -90,63 +92,162 @@ static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
90 return ret; 92 return ret;
91} 93}
92 94
93static void __init _of_ti_gate_clk_setup(struct device_node *node, 95static struct clk *_register_gate(struct device *dev, const char *name,
94 const struct clk_ops *ops, 96 const char *parent_name, unsigned long flags,
95 const struct clk_hw_omap_ops *hw_ops) 97 void __iomem *reg, u8 bit_idx,
98 u8 clk_gate_flags, const struct clk_ops *ops,
99 const struct clk_hw_omap_ops *hw_ops)
96{ 100{
97 struct clk *clk;
98 struct clk_init_data init = { NULL }; 101 struct clk_init_data init = { NULL };
99 struct clk_hw_omap *clk_hw; 102 struct clk_hw_omap *clk_hw;
100 const char *clk_name = node->name; 103 struct clk *clk;
101 const char *parent_name;
102 u32 val;
103 104
104 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 105 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
105 if (!clk_hw) 106 if (!clk_hw)
106 return; 107 return ERR_PTR(-ENOMEM);
107 108
108 clk_hw->hw.init = &init; 109 clk_hw->hw.init = &init;
109 110
110 init.name = clk_name; 111 init.name = name;
111 init.ops = ops; 112 init.ops = ops;
112 113
113 if (ops != &omap_gate_clkdm_clk_ops) { 114 clk_hw->enable_reg = reg;
114 clk_hw->enable_reg = ti_clk_get_reg_addr(node, 0); 115 clk_hw->enable_bit = bit_idx;
115 if (!clk_hw->enable_reg) 116 clk_hw->ops = hw_ops;
116 goto cleanup;
117 117
118 if (!of_property_read_u32(node, "ti,bit-shift", &val)) 118 clk_hw->flags = MEMMAP_ADDRESSING | clk_gate_flags;
119 clk_hw->enable_bit = val; 119
120 init.parent_names = &parent_name;
121 init.num_parents = 1;
122
123 init.flags = flags;
124
125 clk = clk_register(NULL, &clk_hw->hw);
126
127 if (IS_ERR(clk))
128 kfree(clk_hw);
129
130 return clk;
131}
132
133struct clk *ti_clk_register_gate(struct ti_clk *setup)
134{
135 const struct clk_ops *ops = &omap_gate_clk_ops;
136 const struct clk_hw_omap_ops *hw_ops = NULL;
137 u32 reg;
138 struct clk_omap_reg *reg_setup;
139 u32 flags = 0;
140 u8 clk_gate_flags = 0;
141 struct ti_clk_gate *gate;
142
143 gate = setup->data;
144
145 if (gate->flags & CLKF_INTERFACE)
146 return ti_clk_register_interface(setup);
147
148 reg_setup = (struct clk_omap_reg *)&reg;
149
150 if (gate->flags & CLKF_SET_RATE_PARENT)
151 flags |= CLK_SET_RATE_PARENT;
152
153 if (gate->flags & CLKF_SET_BIT_TO_DISABLE)
154 clk_gate_flags |= INVERT_ENABLE;
155
156 if (gate->flags & CLKF_HSDIV) {
157 ops = &omap_gate_clk_hsdiv_restore_ops;
158 hw_ops = &clkhwops_wait;
120 } 159 }
121 160
122 clk_hw->ops = hw_ops; 161 if (gate->flags & CLKF_DSS)
162 hw_ops = &clkhwops_omap3430es2_dss_usbhost_wait;
163
164 if (gate->flags & CLKF_WAIT)
165 hw_ops = &clkhwops_wait;
166
167 if (gate->flags & CLKF_CLKDM)
168 ops = &omap_gate_clkdm_clk_ops;
169
170 if (gate->flags & CLKF_AM35XX)
171 hw_ops = &clkhwops_am35xx_ipss_module_wait;
172
173 reg_setup->index = gate->module;
174 reg_setup->offset = gate->reg;
175
176 return _register_gate(NULL, setup->name, gate->parent, flags,
177 (void __iomem *)reg, gate->bit_shift,
178 clk_gate_flags, ops, hw_ops);
179}
123 180
124 clk_hw->flags = MEMMAP_ADDRESSING; 181struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup)
182{
183 struct clk_hw_omap *gate;
184 struct clk_omap_reg *reg;
185 const struct clk_hw_omap_ops *ops = &clkhwops_wait;
186
187 if (!setup)
188 return NULL;
189
190 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
191 if (!gate)
192 return ERR_PTR(-ENOMEM);
193
194 reg = (struct clk_omap_reg *)&gate->enable_reg;
195 reg->index = setup->module;
196 reg->offset = setup->reg;
197
198 gate->enable_bit = setup->bit_shift;
199
200 if (setup->flags & CLKF_NO_WAIT)
201 ops = NULL;
202
203 if (setup->flags & CLKF_INTERFACE)
204 ops = &clkhwops_iclk_wait;
205
206 gate->ops = ops;
207 gate->flags = MEMMAP_ADDRESSING;
208
209 return &gate->hw;
210}
211
212static void __init _of_ti_gate_clk_setup(struct device_node *node,
213 const struct clk_ops *ops,
214 const struct clk_hw_omap_ops *hw_ops)
215{
216 struct clk *clk;
217 const char *parent_name;
218 void __iomem *reg = NULL;
219 u8 enable_bit = 0;
220 u32 val;
221 u32 flags = 0;
222 u8 clk_gate_flags = 0;
223
224 if (ops != &omap_gate_clkdm_clk_ops) {
225 reg = ti_clk_get_reg_addr(node, 0);
226 if (!reg)
227 return;
228
229 if (!of_property_read_u32(node, "ti,bit-shift", &val))
230 enable_bit = val;
231 }
125 232
126 if (of_clk_get_parent_count(node) != 1) { 233 if (of_clk_get_parent_count(node) != 1) {
127 pr_err("%s must have 1 parent\n", clk_name); 234 pr_err("%s must have 1 parent\n", node->name);
128 goto cleanup; 235 return;
129 } 236 }
130 237
131 parent_name = of_clk_get_parent_name(node, 0); 238 parent_name = of_clk_get_parent_name(node, 0);
132 init.parent_names = &parent_name;
133 init.num_parents = 1;
134 239
135 if (of_property_read_bool(node, "ti,set-rate-parent")) 240 if (of_property_read_bool(node, "ti,set-rate-parent"))
136 init.flags |= CLK_SET_RATE_PARENT; 241 flags |= CLK_SET_RATE_PARENT;
137 242
138 if (of_property_read_bool(node, "ti,set-bit-to-disable")) 243 if (of_property_read_bool(node, "ti,set-bit-to-disable"))
139 clk_hw->flags |= INVERT_ENABLE; 244 clk_gate_flags |= INVERT_ENABLE;
140 245
141 clk = clk_register(NULL, &clk_hw->hw); 246 clk = _register_gate(NULL, node->name, parent_name, flags, reg,
247 enable_bit, clk_gate_flags, ops, hw_ops);
142 248
143 if (!IS_ERR(clk)) { 249 if (!IS_ERR(clk))
144 of_clk_add_provider(node, of_clk_src_simple_get, clk); 250 of_clk_add_provider(node, of_clk_src_simple_get, clk);
145 return;
146 }
147
148cleanup:
149 kfree(clk_hw);
150} 251}
151 252
152static void __init 253static void __init
diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c
index 9c3e8c4aaa40..d71cd9b5de46 100644
--- a/drivers/clk/ti/interface.c
+++ b/drivers/clk/ti/interface.c
@@ -20,6 +20,7 @@
20#include <linux/of.h> 20#include <linux/of.h>
21#include <linux/of_address.h> 21#include <linux/of_address.h>
22#include <linux/clk/ti.h> 22#include <linux/clk/ti.h>
23#include "clock.h"
23 24
24#undef pr_fmt 25#undef pr_fmt
25#define pr_fmt(fmt) "%s: " fmt, __func__ 26#define pr_fmt(fmt) "%s: " fmt, __func__
@@ -31,53 +32,100 @@ static const struct clk_ops ti_interface_clk_ops = {
31 .is_enabled = &omap2_dflt_clk_is_enabled, 32 .is_enabled = &omap2_dflt_clk_is_enabled,
32}; 33};
33 34
34static void __init _of_ti_interface_clk_setup(struct device_node *node, 35static struct clk *_register_interface(struct device *dev, const char *name,
35 const struct clk_hw_omap_ops *ops) 36 const char *parent_name,
37 void __iomem *reg, u8 bit_idx,
38 const struct clk_hw_omap_ops *ops)
36{ 39{
37 struct clk *clk;
38 struct clk_init_data init = { NULL }; 40 struct clk_init_data init = { NULL };
39 struct clk_hw_omap *clk_hw; 41 struct clk_hw_omap *clk_hw;
40 const char *parent_name; 42 struct clk *clk;
41 u32 val;
42 43
43 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 44 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
44 if (!clk_hw) 45 if (!clk_hw)
45 return; 46 return ERR_PTR(-ENOMEM);
46 47
47 clk_hw->hw.init = &init; 48 clk_hw->hw.init = &init;
48 clk_hw->ops = ops; 49 clk_hw->ops = ops;
49 clk_hw->flags = MEMMAP_ADDRESSING; 50 clk_hw->flags = MEMMAP_ADDRESSING;
51 clk_hw->enable_reg = reg;
52 clk_hw->enable_bit = bit_idx;
50 53
51 clk_hw->enable_reg = ti_clk_get_reg_addr(node, 0); 54 init.name = name;
52 if (!clk_hw->enable_reg)
53 goto cleanup;
54
55 if (!of_property_read_u32(node, "ti,bit-shift", &val))
56 clk_hw->enable_bit = val;
57
58 init.name = node->name;
59 init.ops = &ti_interface_clk_ops; 55 init.ops = &ti_interface_clk_ops;
60 init.flags = 0; 56 init.flags = 0;
61 57
62 parent_name = of_clk_get_parent_name(node, 0);
63 if (!parent_name) {
64 pr_err("%s must have a parent\n", node->name);
65 goto cleanup;
66 }
67
68 init.num_parents = 1; 58 init.num_parents = 1;
69 init.parent_names = &parent_name; 59 init.parent_names = &parent_name;
70 60
71 clk = clk_register(NULL, &clk_hw->hw); 61 clk = clk_register(NULL, &clk_hw->hw);
72 62
73 if (!IS_ERR(clk)) { 63 if (IS_ERR(clk))
74 of_clk_add_provider(node, of_clk_src_simple_get, clk); 64 kfree(clk_hw);
65 else
75 omap2_init_clk_hw_omap_clocks(clk); 66 omap2_init_clk_hw_omap_clocks(clk);
67
68 return clk;
69}
70
71struct clk *ti_clk_register_interface(struct ti_clk *setup)
72{
73 const struct clk_hw_omap_ops *ops = &clkhwops_iclk_wait;
74 u32 reg;
75 struct clk_omap_reg *reg_setup;
76 struct ti_clk_gate *gate;
77
78 gate = setup->data;
79 reg_setup = (struct clk_omap_reg *)&reg;
80 reg_setup->index = gate->module;
81 reg_setup->offset = gate->reg;
82
83 if (gate->flags & CLKF_NO_WAIT)
84 ops = &clkhwops_iclk;
85
86 if (gate->flags & CLKF_HSOTGUSB)
87 ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait;
88
89 if (gate->flags & CLKF_DSS)
90 ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait;
91
92 if (gate->flags & CLKF_SSI)
93 ops = &clkhwops_omap3430es2_iclk_ssi_wait;
94
95 if (gate->flags & CLKF_AM35XX)
96 ops = &clkhwops_am35xx_ipss_wait;
97
98 return _register_interface(NULL, setup->name, gate->parent,
99 (void __iomem *)reg, gate->bit_shift, ops);
100}
101
102static void __init _of_ti_interface_clk_setup(struct device_node *node,
103 const struct clk_hw_omap_ops *ops)
104{
105 struct clk *clk;
106 const char *parent_name;
107 void __iomem *reg;
108 u8 enable_bit = 0;
109 u32 val;
110
111 reg = ti_clk_get_reg_addr(node, 0);
112 if (!reg)
113 return;
114
115 if (!of_property_read_u32(node, "ti,bit-shift", &val))
116 enable_bit = val;
117
118 parent_name = of_clk_get_parent_name(node, 0);
119 if (!parent_name) {
120 pr_err("%s must have a parent\n", node->name);
76 return; 121 return;
77 } 122 }
78 123
79cleanup: 124 clk = _register_interface(NULL, node->name, parent_name, reg,
80 kfree(clk_hw); 125 enable_bit, ops);
126
127 if (!IS_ERR(clk))
128 of_clk_add_provider(node, of_clk_src_simple_get, clk);
81} 129}
82 130
83static void __init of_ti_interface_clk_setup(struct device_node *node) 131static void __init of_ti_interface_clk_setup(struct device_node *node)
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
index e9d650e51287..728e253606bc 100644
--- a/drivers/clk/ti/mux.c
+++ b/drivers/clk/ti/mux.c
@@ -21,6 +21,7 @@
21#include <linux/of.h> 21#include <linux/of.h>
22#include <linux/of_address.h> 22#include <linux/of_address.h>
23#include <linux/clk/ti.h> 23#include <linux/clk/ti.h>
24#include "clock.h"
24 25
25#undef pr_fmt 26#undef pr_fmt
26#define pr_fmt(fmt) "%s: " fmt, __func__ 27#define pr_fmt(fmt) "%s: " fmt, __func__
@@ -144,6 +145,39 @@ static struct clk *_register_mux(struct device *dev, const char *name,
144 return clk; 145 return clk;
145} 146}
146 147
148struct clk *ti_clk_register_mux(struct ti_clk *setup)
149{
150 struct ti_clk_mux *mux;
151 u32 flags;
152 u8 mux_flags = 0;
153 struct clk_omap_reg *reg_setup;
154 u32 reg;
155 u32 mask;
156
157 reg_setup = (struct clk_omap_reg *)&reg;
158
159 mux = setup->data;
160 flags = CLK_SET_RATE_NO_REPARENT;
161
162 mask = mux->num_parents;
163 if (!(mux->flags & CLKF_INDEX_STARTS_AT_ONE))
164 mask--;
165
166 mask = (1 << fls(mask)) - 1;
167 reg_setup->index = mux->module;
168 reg_setup->offset = mux->reg;
169
170 if (mux->flags & CLKF_INDEX_STARTS_AT_ONE)
171 mux_flags |= CLK_MUX_INDEX_ONE;
172
173 if (mux->flags & CLKF_SET_RATE_PARENT)
174 flags |= CLK_SET_RATE_PARENT;
175
176 return _register_mux(NULL, setup->name, mux->parents, mux->num_parents,
177 flags, (void __iomem *)reg, mux->bit_shift, mask,
178 mux_flags, NULL, NULL);
179}
180
147/** 181/**
148 * of_mux_clk_setup - Setup function for simple mux rate clock 182 * of_mux_clk_setup - Setup function for simple mux rate clock
149 * @node: DT node for the clock 183 * @node: DT node for the clock
@@ -194,8 +228,9 @@ static void of_mux_clk_setup(struct device_node *node)
194 228
195 mask = (1 << fls(mask)) - 1; 229 mask = (1 << fls(mask)) - 1;
196 230
197 clk = _register_mux(NULL, node->name, parent_names, num_parents, flags, 231 clk = _register_mux(NULL, node->name, parent_names, num_parents,
198 reg, shift, mask, clk_mux_flags, NULL, NULL); 232 flags, reg, shift, mask, clk_mux_flags, NULL,
233 NULL);
199 234
200 if (!IS_ERR(clk)) 235 if (!IS_ERR(clk))
201 of_clk_add_provider(node, of_clk_src_simple_get, clk); 236 of_clk_add_provider(node, of_clk_src_simple_get, clk);
@@ -205,6 +240,37 @@ cleanup:
205} 240}
206CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup); 241CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
207 242
243struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup)
244{
245 struct clk_mux *mux;
246 struct clk_omap_reg *reg;
247 int num_parents;
248
249 if (!setup)
250 return NULL;
251
252 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
253 if (!mux)
254 return ERR_PTR(-ENOMEM);
255
256 reg = (struct clk_omap_reg *)&mux->reg;
257
258 mux->shift = setup->bit_shift;
259
260 reg->index = setup->module;
261 reg->offset = setup->reg;
262
263 if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
264 mux->flags |= CLK_MUX_INDEX_ONE;
265
266 num_parents = setup->num_parents;
267
268 mux->mask = num_parents - 1;
269 mux->mask = (1 << fls(mux->mask)) - 1;
270
271 return &mux->hw;
272}
273
208static void __init of_ti_composite_mux_clk_setup(struct device_node *node) 274static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
209{ 275{
210 struct clk_mux *mux; 276 struct clk_mux *mux;
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 172d13fd8bea..310122dcd9b5 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -218,6 +218,13 @@ struct ti_dt_clk {
218/* Maximum number of clock memmaps */ 218/* Maximum number of clock memmaps */
219#define CLK_MAX_MEMMAPS 4 219#define CLK_MAX_MEMMAPS 4
220 220
221/* Static memmap indices */
222enum {
223 TI_CLKM_CM = 0,
224 TI_CLKM_PRM,
225 TI_CLKM_SCRM,
226};
227
221typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *); 228typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);
222 229
223/** 230/**
@@ -349,4 +356,9 @@ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
349extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; 356extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
350extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; 357extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
351 358
359int omap3430_clk_legacy_init(void);
360int omap3430es1_clk_legacy_init(void);
361int omap36xx_clk_legacy_init(void);
362int am35xx_clk_legacy_init(void);
363
352#endif 364#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 03:52:05 -0400