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authorTony Lindgren <tony@atomide.com>2019-03-26 13:54:40 -0400
committerTony Lindgren <tony@atomide.com>2019-04-08 13:10:59 -0400
commita071e407ffbe32f7afe77ce5ffdb926d8682f17c (patch)
tree974ec0b8676f801dc55034da7ecd63385d58416d /arch/arm/mach-omap2/omap_hwmod_43xx_data.c
parentcb682853c98ff0205ea40e961ef667d2fff5599a (diff)
ARM: OMAP2+: Drop gpio platform data for am33xx and am43xx
We can now drop legacy platform data one interconnect target module at a time in favor of the device tree based data that has been added earlier. Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_43xx_data.c')
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_43xx_data.c87
1 files changed, 0 insertions, 87 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index fa3c6b7e7086..dbdf1fa00fb0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -87,26 +87,6 @@ static struct omap_hwmod am43xx_control_hwmod = {
87 }, 87 },
88}; 88};
89 89
90static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
91 { .role = "dbclk", .clk = "gpio0_dbclk" },
92};
93
94static struct omap_hwmod am43xx_gpio0_hwmod = {
95 .name = "gpio1",
96 .class = &am33xx_gpio_hwmod_class,
97 .clkdm_name = "l4_wkup_clkdm",
98 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
99 .main_clk = "sys_clkin_ck",
100 .prcm = {
101 .omap4 = {
102 .clkctrl_offs = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
103 .modulemode = MODULEMODE_SWCTRL,
104 },
105 },
106 .opt_clks = gpio0_opt_clks,
107 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
108};
109
110static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = { 90static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
111 .rev_offs = 0x0, 91 .rev_offs = 0x0,
112 .sysc_offs = 0x4, 92 .sysc_offs = 0x4,
@@ -264,46 +244,6 @@ static struct omap_hwmod am43xx_spi4_hwmod = {
264 }, 244 },
265}; 245};
266 246
267static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
268 { .role = "dbclk", .clk = "gpio4_dbclk" },
269};
270
271static struct omap_hwmod am43xx_gpio4_hwmod = {
272 .name = "gpio5",
273 .class = &am33xx_gpio_hwmod_class,
274 .clkdm_name = "l4ls_clkdm",
275 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
276 .main_clk = "l4ls_gclk",
277 .prcm = {
278 .omap4 = {
279 .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
280 .modulemode = MODULEMODE_SWCTRL,
281 },
282 },
283 .opt_clks = gpio4_opt_clks,
284 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
285};
286
287static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
288 { .role = "dbclk", .clk = "gpio5_dbclk" },
289};
290
291static struct omap_hwmod am43xx_gpio5_hwmod = {
292 .name = "gpio6",
293 .class = &am33xx_gpio_hwmod_class,
294 .clkdm_name = "l4ls_clkdm",
295 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
296 .main_clk = "l4ls_gclk",
297 .prcm = {
298 .omap4 = {
299 .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
300 .modulemode = MODULEMODE_SWCTRL,
301 },
302 },
303 .opt_clks = gpio5_opt_clks,
304 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
305};
306
307static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = { 247static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
308 .name = "ocp2scp", 248 .name = "ocp2scp",
309}; 249};
@@ -650,13 +590,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
650 .user = OCP_USER_MPU, 590 .user = OCP_USER_MPU,
651}; 591};
652 592
653static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
654 .master = &am33xx_l4_wkup_hwmod,
655 .slave = &am43xx_gpio0_hwmod,
656 .clk = "sys_clkin_ck",
657 .user = OCP_USER_MPU | OCP_USER_SDMA,
658};
659
660static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = { 593static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = {
661 .master = &am33xx_l4_wkup_hwmod, 594 .master = &am33xx_l4_wkup_hwmod,
662 .slave = &am43xx_adc_tsc_hwmod, 595 .slave = &am43xx_adc_tsc_hwmod,
@@ -769,20 +702,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
769 .user = OCP_USER_MPU, 702 .user = OCP_USER_MPU,
770}; 703};
771 704
772static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
773 .master = &am33xx_l4_ls_hwmod,
774 .slave = &am43xx_gpio4_hwmod,
775 .clk = "l4ls_gclk",
776 .user = OCP_USER_MPU | OCP_USER_SDMA,
777};
778
779static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
780 .master = &am33xx_l4_ls_hwmod,
781 .slave = &am43xx_gpio5_hwmod,
782 .clk = "l4ls_gclk",
783 .user = OCP_USER_MPU | OCP_USER_SDMA,
784};
785
786static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = { 705static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = {
787 .master = &am33xx_l4_ls_hwmod, 706 .master = &am33xx_l4_ls_hwmod,
788 .slave = &am43xx_ocp2scp0_hwmod, 707 .slave = &am43xx_ocp2scp0_hwmod,
@@ -900,8 +819,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
900 &am43xx_l4_ls__mcspi2, 819 &am43xx_l4_ls__mcspi2,
901 &am43xx_l4_ls__mcspi3, 820 &am43xx_l4_ls__mcspi3,
902 &am43xx_l4_ls__mcspi4, 821 &am43xx_l4_ls__mcspi4,
903 &am43xx_l4_ls__gpio4,
904 &am43xx_l4_ls__gpio5,
905 &am43xx_l3_main__pruss, 822 &am43xx_l3_main__pruss,
906 &am33xx_mpu__l3_main, 823 &am33xx_mpu__l3_main,
907 &am33xx_mpu__prcm, 824 &am33xx_mpu__prcm,
@@ -922,15 +839,11 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
922 &am43xx_l4_wkup__smartreflex1, 839 &am43xx_l4_wkup__smartreflex1,
923 &am43xx_l4_wkup__uart1, 840 &am43xx_l4_wkup__uart1,
924 &am43xx_l4_wkup__timer1, 841 &am43xx_l4_wkup__timer1,
925 &am43xx_l4_wkup__gpio0,
926 &am43xx_l4_wkup__wd_timer1, 842 &am43xx_l4_wkup__wd_timer1,
927 &am43xx_l4_wkup__adc_tsc, 843 &am43xx_l4_wkup__adc_tsc,
928 &am43xx_l3_s__qspi, 844 &am43xx_l3_s__qspi,
929 &am33xx_l4_per__dcan0, 845 &am33xx_l4_per__dcan0,
930 &am33xx_l4_per__dcan1, 846 &am33xx_l4_per__dcan1,
931 &am33xx_l4_per__gpio1,
932 &am33xx_l4_per__gpio2,
933 &am33xx_l4_per__gpio3,
934 &am33xx_l4_per__mailbox, 847 &am33xx_l4_per__mailbox,
935 &am33xx_l4_per__rng, 848 &am33xx_l4_per__rng,
936 &am33xx_l4_ls__mcasp0, 849 &am33xx_l4_ls__mcasp0,