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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2016-06-20 11:25:44 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2016-06-20 11:25:44 -0400
commitaf52739b922f656eb1f39016fabaabe4baeda2e2 (patch)
tree79a7aa810d0493cd0cf4adebac26d37f12e8b545 /arch/arc/mm/dma.c
parent25ed6a5e97809129a1bc852b6b5c7d03baa112c4 (diff)
parent33688abb2802ff3a230bd2441f765477b94cc89e (diff)
Merge 4.7-rc4 into staging-next
We want the fixes in here, and we can resolve a merge issue in drivers/iio/industrialio-trigger.c Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/arc/mm/dma.c')
-rw-r--r--arch/arc/mm/dma.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arc/mm/dma.c b/arch/arc/mm/dma.c
index 8c8e36fa5659..73d7e4c75b7d 100644
--- a/arch/arc/mm/dma.c
+++ b/arch/arc/mm/dma.c
@@ -10,7 +10,7 @@
10 * DMA Coherent API Notes 10 * DMA Coherent API Notes
11 * 11 *
12 * I/O is inherently non-coherent on ARC. So a coherent DMA buffer is 12 * I/O is inherently non-coherent on ARC. So a coherent DMA buffer is
13 * implemented by accessintg it using a kernel virtual address, with 13 * implemented by accessing it using a kernel virtual address, with
14 * Cache bit off in the TLB entry. 14 * Cache bit off in the TLB entry.
15 * 15 *
16 * The default DMA address == Phy address which is 0x8000_0000 based. 16 * The default DMA address == Phy address which is 0x8000_0000 based.