drm/amdgpu: cleanup vm_size handling

It's pointless to have the same value twice, just always use max_pfn.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

6 files changed, 17 insertions, 24 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 1e727da2bb64..122379dfc7d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2576,27 +2576,27 @@ void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
  * @adev: amdgpu_device pointer
  * @vm_size: the default vm size if it's set auto
  */
-void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size,
+void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
                            uint32_t fragment_size_default)
 {
         /* adjust vm size firstly */
-        if (amdgpu_vm_size == -1)
-                adev->vm_manager.vm_size = vm_size;
-        else
-                adev->vm_manager.vm_size = amdgpu_vm_size;
+        if (amdgpu_vm_size != -1)
+                vm_size = amdgpu_vm_size;
+
+        adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
 
         /* block size depends on vm size */
         if (amdgpu_vm_block_size == -1)
                 adev->vm_manager.block_size =
-                        amdgpu_vm_get_block_size(adev->vm_manager.vm_size);
+                        amdgpu_vm_get_block_size(vm_size);
         else
                 adev->vm_manager.block_size = amdgpu_vm_block_size;
 
         amdgpu_vm_set_fragment_size(adev, fragment_size_default);
 
-        DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n",
-                adev->vm_manager.vm_size, adev->vm_manager.block_size,
-                adev->vm_manager.fragment_size);
+        DRM_INFO("vm size is %u GB, block size is %u-bit, fragment size is %u-bit\n",
+                 vm_size, adev->vm_manager.block_size,
+                 adev->vm_manager.fragment_size);
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index bae77353447b..e8f8896d18db 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -221,7 +221,6 @@ struct amdgpu_vm_manager {
 
         uint64_t                                max_pfn;
         uint32_t                                num_level;
-        uint64_t                                vm_size;
         uint32_t                                block_size;
         uint32_t                                fragment_size;
         /* vram base address for page table entry  */
@@ -313,9 +312,9 @@ struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
                       struct amdgpu_bo_va *bo_va);
 void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
-                                uint32_t fragment_size_default);
-void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size,
-                                uint32_t fragment_size_default);
+                                 uint32_t fragment_size_default);
+void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
+                           uint32_t fragment_size_default);
 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
                                   struct amdgpu_job *job);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index d2a43db22cff..c8e47c36608e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -838,7 +838,6 @@ static int gmc_v6_0_sw_init(void *handle)
                 return r;
 
         amdgpu_vm_adjust_size(adev, 64, 9);
-        adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 
         adev->mc.mc_mask = 0xffffffffffULL;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 6c6a7e14359c..2b7338e22409 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -978,7 +978,6 @@ static int gmc_v7_0_sw_init(void *handle)
          * Max GPUVM size for cayman and SI is 40 bits.
          */
         amdgpu_vm_adjust_size(adev, 64, 9);
-        adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 
         /* Set the internal MC address mask
          * This is the max address of the GPU's
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index edbe0df24d90..e30a96a8f49b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1075,7 +1075,6 @@ static int gmc_v8_0_sw_init(void *handle)
          * Max GPUVM size for cayman and SI is 40 bits.
          */
         amdgpu_vm_adjust_size(adev, 64, 9);
-        adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 
         /* Set the internal MC address mask
          * This is the max address of the GPU's
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 69c9af7af6f4..b067b46a418f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -564,7 +564,7 @@ static int gmc_v9_0_sw_init(void *handle)
         case CHIP_RAVEN:
                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
                 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
-                        adev->vm_manager.vm_size = 1U << 18;
+                        adev->vm_manager.max_pfn = 1ULL << 36;
                         adev->vm_manager.block_size = 9;
                         adev->vm_manager.num_level = 3;
                         amdgpu_vm_set_fragment_size(adev, 9);
@@ -582,7 +582,7 @@ static int gmc_v9_0_sw_init(void *handle)
                  * vm size is 256TB (48bit), maximum size of Vega10,
                  * block size 512 (9bit)
                  */
-                adev->vm_manager.vm_size = 1U << 18;
+                adev->vm_manager.max_pfn = 1ULL << 36;
                 adev->vm_manager.block_size = 9;
                 adev->vm_manager.num_level = 3;
                 amdgpu_vm_set_fragment_size(adev, 9);
@@ -591,10 +591,9 @@ static int gmc_v9_0_sw_init(void *handle)
                 break;
         }
 
-        DRM_INFO("vm size is %llu GB, block size is %u-bit,fragment size is %u-bit\n",
-                        adev->vm_manager.vm_size,
-                        adev->vm_manager.block_size,
-                        adev->vm_manager.fragment_size);
+        DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n",
+                 adev->vm_manager.max_pfn >> 18, adev->vm_manager.block_size,
+                 adev->vm_manager.fragment_size);
 
         /* This interrupt is VMC page fault.*/
         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
@@ -605,8 +604,6 @@ static int gmc_v9_0_sw_init(void *handle)
         if (r)
                 return r;
 
-        adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
-
         /* Set the internal MC address mask
          * This is the max address of the GPU's
          * internal address space.