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authorRyder Lee <ryder.lee@mediatek.com>2018-09-05 06:22:19 -0400
committerMatthias Brugger <matthias.bgg@gmail.com>2018-09-25 11:44:34 -0400
commitfce695cbd5eba4fcbfa59bd5d15f333c96845c97 (patch)
treeaec9a4d2d86da660804f7c21648f2c8654662c34
parent8ff2017b942828ffbb49a3c620fdb31c85cbc824 (diff)
arm: dts: mt7623: add iommu/smi device nodes
Add iommu/smi device nodes for MT7623. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
-rw-r--r--arch/arm/boot/dts/mt7623.dtsi59
1 files changed, 59 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index b7ccf8b840d9..a46987bd7085 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -13,6 +13,7 @@
13#include <dt-bindings/power/mt2701-power.h> 13#include <dt-bindings/power/mt2701-power.h>
14#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/phy/phy.h> 15#include <dt-bindings/phy/phy.h>
16#include <dt-bindings/memory/mt2701-larb-port.h>
16#include <dt-bindings/reset/mt2701-resets.h> 17#include <dt-bindings/reset/mt2701-resets.h>
17#include <dt-bindings/thermal/thermal.h> 18#include <dt-bindings/thermal/thermal.h>
18 19
@@ -286,6 +287,17 @@
286 clock-names = "system-clk", "rtc-clk"; 287 clock-names = "system-clk", "rtc-clk";
287 }; 288 };
288 289
290 smi_common: smi@1000c000 {
291 compatible = "mediatek,mt7623-smi-common",
292 "mediatek,mt2701-smi-common";
293 reg = <0 0x1000c000 0 0x1000>;
294 clocks = <&infracfg CLK_INFRA_SMI>,
295 <&mmsys CLK_MM_SMI_COMMON>,
296 <&infracfg CLK_INFRA_SMI>;
297 clock-names = "apb", "smi", "async";
298 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
299 };
300
289 pwrap: pwrap@1000d000 { 301 pwrap: pwrap@1000d000 {
290 compatible = "mediatek,mt7623-pwrap", 302 compatible = "mediatek,mt7623-pwrap",
291 "mediatek,mt2701-pwrap"; 303 "mediatek,mt2701-pwrap";
@@ -317,6 +329,17 @@
317 reg = <0 0x10200100 0 0x1c>; 329 reg = <0 0x10200100 0 0x1c>;
318 }; 330 };
319 331
332 iommu: mmsys_iommu@10205000 {
333 compatible = "mediatek,mt7623-m4u",
334 "mediatek,mt2701-m4u";
335 reg = <0 0x10205000 0 0x1000>;
336 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
337 clocks = <&infracfg CLK_INFRA_M4U>;
338 clock-names = "bclk";
339 mediatek,larbs = <&larb0 &larb1 &larb2>;
340 #iommu-cells = <1>;
341 };
342
320 efuse: efuse@10206000 { 343 efuse: efuse@10206000 {
321 compatible = "mediatek,mt7623-efuse", 344 compatible = "mediatek,mt7623-efuse",
322 "mediatek,mt8173-efuse"; 345 "mediatek,mt8173-efuse";
@@ -709,6 +732,18 @@
709 #clock-cells = <1>; 732 #clock-cells = <1>;
710 }; 733 };
711 734
735 larb0: larb@14010000 {
736 compatible = "mediatek,mt7623-smi-larb",
737 "mediatek,mt2701-smi-larb";
738 reg = <0 0x14010000 0 0x1000>;
739 mediatek,smi = <&smi_common>;
740 mediatek,larb-id = <0>;
741 clocks = <&mmsys CLK_MM_SMI_LARB0>,
742 <&mmsys CLK_MM_SMI_LARB0>;
743 clock-names = "apb", "smi";
744 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
745 };
746
712 imgsys: syscon@15000000 { 747 imgsys: syscon@15000000 {
713 compatible = "mediatek,mt7623-imgsys", 748 compatible = "mediatek,mt7623-imgsys",
714 "mediatek,mt2701-imgsys", 749 "mediatek,mt2701-imgsys",
@@ -717,6 +752,18 @@
717 #clock-cells = <1>; 752 #clock-cells = <1>;
718 }; 753 };
719 754
755 larb2: larb@15001000 {
756 compatible = "mediatek,mt7623-smi-larb",
757 "mediatek,mt2701-smi-larb";
758 reg = <0 0x15001000 0 0x1000>;
759 mediatek,smi = <&smi_common>;
760 mediatek,larb-id = <2>;
761 clocks = <&imgsys CLK_IMG_SMI_COMM>,
762 <&imgsys CLK_IMG_SMI_COMM>;
763 clock-names = "apb", "smi";
764 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
765 };
766
720 vdecsys: syscon@16000000 { 767 vdecsys: syscon@16000000 {
721 compatible = "mediatek,mt7623-vdecsys", 768 compatible = "mediatek,mt7623-vdecsys",
722 "mediatek,mt2701-vdecsys", 769 "mediatek,mt2701-vdecsys",
@@ -725,6 +772,18 @@
725 #clock-cells = <1>; 772 #clock-cells = <1>;
726 }; 773 };
727 774
775 larb1: larb@16010000 {
776 compatible = "mediatek,mt7623-smi-larb",
777 "mediatek,mt2701-smi-larb";
778 reg = <0 0x16010000 0 0x1000>;
779 mediatek,smi = <&smi_common>;
780 mediatek,larb-id = <1>;
781 clocks = <&vdecsys CLK_VDEC_CKGEN>,
782 <&vdecsys CLK_VDEC_LARB>;
783 clock-names = "apb", "smi";
784 power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
785 };
786
728 hifsys: syscon@1a000000 { 787 hifsys: syscon@1a000000 {
729 compatible = "mediatek,mt7623-hifsys", 788 compatible = "mediatek,mt7623-hifsys",
730 "mediatek,mt2701-hifsys", 789 "mediatek,mt2701-hifsys",