perf/x86/intel: Use PAGE_SIZE for PEBS buffer size on Core2

Using PAGE_SIZE buffers makes the WRMSR to PERF_GLOBAL_CTRL in
intel_pmu_enable_all() mysteriously hang on Core2. As a workaround, we
don't do this.

The hard lockup is easily triggered by running 'perf test attr'
repeatedly. Most of the time it gets stuck on sample session with
small periods.

  # perf test attr -vv
  14: struct perf_event_attr setup                             :
  --- start ---
  ...
    'PERF_TEST_ATTR=/tmp/tmpuEKz3B /usr/bin/perf record -o /tmp/tmpuEKz3B/perf.data -c 123 kill >/dev/null 2>&1' ret 1

Reported-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: Jiri Olsa <jolsa@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Cc: <stable@vger.kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: Wang Nan <wangnan0@huawei.com>
Link: http://lkml.kernel.org/r/20160301190352.GA8355@krava.redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>

2 files changed, 12 insertions, 2 deletions

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index c8a243d6fc82..22ece02d01b6 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -269,7 +269,7 @@ static int alloc_pebs_buffer(int cpu)
         if (!x86_pmu.pebs)
                 return 0;
 
-        buffer = kzalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL, node);
+        buffer = kzalloc_node(x86_pmu.pebs_buffer_size, GFP_KERNEL, node);
         if (unlikely(!buffer))
                 return -ENOMEM;
 
@@ -286,7 +286,7 @@ static int alloc_pebs_buffer(int cpu)
                 per_cpu(insn_buffer, cpu) = ibuffer;
         }
 
-        max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
+        max = x86_pmu.pebs_buffer_size / x86_pmu.pebs_record_size;
 
         ds->pebs_buffer_base = (u64)(unsigned long)buffer;
         ds->pebs_index = ds->pebs_buffer_base;
@@ -1319,6 +1319,7 @@ void __init intel_ds_init(void)
 
         x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
         x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
+        x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
         if (x86_pmu.pebs) {
                 char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
                 int format = x86_pmu.intel_cap.pebs_format;
@@ -1327,6 +1328,14 @@ void __init intel_ds_init(void)
                 case 0:
                         pr_cont("PEBS fmt0%c, ", pebs_type);
                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
+                        /*
+                         * Using >PAGE_SIZE buffers makes the WRMSR to
+                         * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
+                         * mysteriously hang on Core2.
+                         *
+                         * As a workaround, we don't do this.
+                         */
+                        x86_pmu.pebs_buffer_size = PAGE_SIZE;
                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
                         break;
 
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 7bb61e32fb29..1ab6279fed1d 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -586,6 +586,7 @@ struct x86_pmu {
                         pebs_broken     :1,
                         pebs_prec_dist  :1;
         int             pebs_record_size;
+        int             pebs_buffer_size;
         void            (*drain_pebs)(struct pt_regs *regs);
         struct event_constraint *pebs_constraints;
         void            (*pebs_aliases)(struct perf_event *event);